KR100342864B1 - Method For Forming The Dual Gate Of Analogue Semiconductor Device - Google Patents
Method For Forming The Dual Gate Of Analogue Semiconductor Device Download PDFInfo
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- KR100342864B1 KR100342864B1 KR1019990008639A KR19990008639A KR100342864B1 KR 100342864 B1 KR100342864 B1 KR 100342864B1 KR 1019990008639 A KR1019990008639 A KR 1019990008639A KR 19990008639 A KR19990008639 A KR 19990008639A KR 100342864 B1 KR100342864 B1 KR 100342864B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 24
- 230000009977 dual effect Effects 0.000 title claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- -1 phosphorus ions Chemical class 0.000 claims abstract description 17
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 15
- 239000011574 phosphorus Substances 0.000 claims abstract description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 29
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000010030 laminating Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 9
- 238000000137 annealing Methods 0.000 abstract description 6
- 229910052796 boron Inorganic materials 0.000 abstract description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 5
- 238000002425 crystallisation Methods 0.000 abstract description 4
- 230000008025 crystallization Effects 0.000 abstract description 4
- 230000005465 channeling Effects 0.000 abstract description 3
- 230000000149 penetrating effect Effects 0.000 abstract description 3
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 47
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
Abstract
본 발명은 본 발명에 따른 아날로그반도체소자의 듀얼게이트 형성방법을 이용하게 되면, PMOS게이트의 폴리실리콘층의 그레인사이즈를 인이온을 도핑하여 조대화시키므로 후속공정에서 보론이 침투하는 것을 방지하고, NMOS게이트의 폴리실리콘층에는 어닐링공정으로 조직을 결정화시킨 후에 인이온을 도핑하므로 폴리실리콘층의 조직 조대화를 차단하여 게이트의 채널링을 방지하므로 아날로그 반도체소자의 전기적인 특성을 향상시키도록 하는 발명에 관한 것이다.When the dual gate forming method of the analog semiconductor device according to the present invention is used, the grain size of the polysilicon layer of the PMOS gate is coarsened by doping with ions, thereby preventing boron from penetrating in a subsequent process and preventing NMOS. Since the polysilicon layer of the gate is doped with phosphorus ions after crystallization by an annealing process, blocking the coarsening of the polysilicon layer prevents channeling of the gate, thereby improving the electrical characteristics of the analog semiconductor device. will be.
Description
본 발명은 듀얼게이트(Dual Gate)를 형성하는 방법에 관한 것으로서, 특히, PMOS게이트의 폴리실리콘층의 그레인사이즈를 인이온을 도핑하여 조대화시키므로 후속공정에서 보론이 침투하는 것을 방지하고, NMOS게이트의 폴리실리콘층에는 어닐링공정으로 조직을 결정화시킨 후에 인이온을 도핑하므로 조직을 조대화를 완화시키도록 하는 반도체소자의 듀얼게이트 형성방법에 관한 것이다.The present invention relates to a method of forming a dual gate, and in particular, the grain size of the polysilicon layer of the PMOS gate is doped and coarsened to prevent penetration of boron in a subsequent process, and the NMOS gate The polysilicon layer of the present invention relates to a method of forming a dual gate of a semiconductor device to reduce the coarsening of the structure by doping the ion after crystallization of the structure by an annealing process.
일반적으로, 모스형전계효과 트랜지스터는 반도체기판에 필드산화막을 형성한 후에 그 전면에 게이트산화막 및 폴리실리콘층을 활성영역(Active Region)에 형성하고서 마스킹식각으로 트랜지스터의 전극역할을 하는 게이트전극을 형성하여 이 기이트전극의 측면부분에 있는 반도체기판에 이온을 주입하여 소오스/드레인영역을 형성하므로 트랜지스터로서 사용될 수 있게 된다.In general, a MOS type field effect transistor forms a field oxide film on a semiconductor substrate, and then forms a gate oxide film and a polysilicon layer on an active region in an active region, and forms a gate electrode that acts as an electrode of the transistor by masking etching. As a result, a source / drain region is formed by implanting ions into the semiconductor substrate on the side of the base electrode, so that it can be used as a transistor.
이러한 트랜지스터에서 게이트산화막은 상부와 하부사이를 전기적으로 차단하는 절연역할을 하게 되는 것으로서, 반도체소자에서 전기적으로 전압이 높은 고전압영역과 전압이 낮은 저전압영역이 동시에 사용되는 듀얼게이트산화막(Dual Gate Oxide)을 갖는 트랜지스터에서는 PMOS게이트와 NMOS게이트를 동시에 형성하도록 한다.In this transistor, the gate oxide film serves as an insulating role to electrically cut off the upper and lower portions, and a dual gate oxide film in which a high voltage region with a high voltage and a low voltage region with a low voltage is used simultaneously in a semiconductor device. In the transistor having the PMOS gate and the NMOS gate to be formed at the same time.
우선, 듀얼게이트에서 PMOS게이트(PMOS Gate)를 형성하는 공정을 개략적으로 살펴 보면, 반도체기판에 게이트산화막(Gate Oxide)을 적층한 후 그 위에 비정질상태의 폴리실리콘층(Amorphous Poly Silicon)을 적층한다.First of all, a process of forming a PMOS gate in a dual gate is schematically described. A gate oxide layer is deposited on a semiconductor substrate, and then an amorphous polysilicon layer is stacked thereon. .
그리고, 연속하여 상기 결과물을 850℃의 온도로, 40분 동안 제1차 어닐링(Annealing)을 한 후 보론(Boron)이온을 비정질실리콘층에 주입시키도록 하고, 그 후 1050℃ 10초 동안 어닐링하면서 형성되는 것이다.Subsequently, the resultant was first annealed at a temperature of 850 ° C. for 40 minutes, followed by injection of boron ions into the amorphous silicon layer, followed by annealing at 1050 ° C. for 10 seconds. It is formed.
또한, NMOS게이트를 형성하는 공정을 살펴 보면, 반도체기판에 게이트산화막을 적층한 후 그 위에 비정질실리콘층이 적층되어지고, 인 이온을 비정질실리콘층에 도핑하여 주입하고 850℃의 온도로, 40분 동안 어닐링 한 후 폴리실리콘층을 식각하여 게이트를 형성하고, 액티브영역에 As이온을 주입하여 형성하게 된다.In addition, in the process of forming the NMOS gate, after the gate oxide film is deposited on the semiconductor substrate, an amorphous silicon layer is stacked thereon, and phosphorus ions are doped and implanted into the amorphous silicon layer, followed by 40 minutes at a temperature of 850 ° C. After the annealing, the polysilicon layer is etched to form a gate, and As ion is implanted into the active region.
그런데. 상기한 공정에서 PMOS를 형성하는 데 있어서, 비정질실리콘층을 증착하고 850℃에서 어닐링을 할 때, 그레인사이즈가 너무 미세하여 후속공정에서 비정질실리콘층에 주입되는 보론이 다른 열공정에서 비정질실리콘층로 부터 게이트산화화막으로 이동하여 게이트산화막의 GOI특성(Gate Oxide Integrity)이 열화시킬 뿐만아니라 심한 경우에는 반도체기판으로 까지 침투하여서 트랜지스터의 써브 쓰레쇼올드 전압(Subthreshold Voltage)을 변화시켜 소자의 전기적인 특성을 저하시키도록 하는 문제점을 지니고 있었다.By the way. In forming the PMOS in the above process, when the amorphous silicon layer is deposited and annealed at 850 ° C., the grain size is too fine so that the boron injected into the amorphous silicon layer in the subsequent process is transferred to the amorphous silicon layer in another thermal process. From the gate oxide layer to the gate oxide layer, and not only deteriorates the gate oxide integrity, but also penetrates into the semiconductor substrate in severe cases and changes the subthreshold voltage of the transistor to change the electrical characteristics of the device. It had a problem to lower the.
또한, NMOS의 경우에는 비정질실리콘층에 이을 주입한 후에 어닐링하므로 폴리게이트의 그레인사이즈가 조대화되어 후속공정에서 LDD영역에 이온을 주입할 때, 채널링(Channeling)에 취약한 문제점을 지니고 있었다.In addition, in the case of NMOS, since the amorphous silicon layer is implanted and then annealed, the grain size of the polygate is coarsened, and thus, when implanting ions into the LDD region in a subsequent process, the NMOS has a problem of weak channeling.
따라서, NMOS 폴리 게이트층은 그레인사이즈(Grain Size)를 줄여야 하고, PMOS 폴리 게이트층은 그레인 사이즈를 늘려야 하는 새로운 방법을 제시하여야 하는 필요성이 대두 되었다. 특히, 트랜지스터와 커패시터가 동시에 형성되는 아날로그 반도체소자에서는 그 필요성이 더욱 더 절실한 실정이다.Therefore, there is a need for the NMOS poly gate layer to reduce the grain size, and the PMOS poly gate layer needs to propose a new method for increasing the grain size. In particular, the need for an analog semiconductor device in which a transistor and a capacitor are formed at the same time is even more urgent.
본 발명은 이러한 점을 감안하여 안출한 것으로서, PMOS게이트의 폴리실리콘층의 그레인사이즈를 인이온을 도핑하여 조대화시키므로 후속공정에서 보론이 침투하는 것을 방지하고, NMOS게이트의 폴리실리콘층에는 어닐링공정으로 조직을 결정화시킨 후에 인이온을 도핑하므로 조직을 조대화를 완화시키도록 하는 것이 목적이다.The present invention has been made in view of this point, and the grain size of the polysilicon layer of the PMOS gate is coarsened by doping with ions, thereby preventing boron from penetrating in a subsequent process, and annealing the polysilicon layer of the NMOS gate. The purpose is to reduce the coarsening of the tissue by doping the phosphorus ion after crystallization.
도 1 내지 도 8은 본 발명에 따른 아날로그 반도체소자의 듀얼게이트 형성방법을 순차적으로 보인 도면이다.1 to 8 are views sequentially showing a method of forming a dual gate of an analog semiconductor device according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 반도체기판 20 : 필드산화막10: semiconductor substrate 20: field oxide film
30 : 비정질실리콘층 40 : 제1마스크30: amorphous silicon layer 40: first mask
50 : 제2마스크 60 ; 절연산화막50: second mask 60; Insulation Oxide
70 : 상부폴리실리콘층 80 : 제3마스크70: upper polysilicon layer 80: third mask
90 : 제4마스크 100 : NMOS게이트90: fourth mask 100: NMOS gate
110 : PMOS게이트 120 : 커패시터110: PMOS gate 120: capacitor
130 : 제5마스크130: fifth mask
본 발명의 목적은 반도체기판에 PMOS영역, NMOS영역 및 커패시터영역으로 이루어진 반도체소자에서, 상기 반도체기판 상에 비정질실리콘층을 적층한 후 커패시터가 형성될 부위가 개방된 제1마스크를 적층하는 단계와; 상기 단계 후에 제1마스크의 개방된 부위를 통하여 인 이온을 비정질실리콘층에 주입한 후 제1마스크를 제거하는 단계와; 상기 단계 후에 비정질실리콘층의 PMOS영역 상에 PMOS게이트가 형성될 부위를 개방하도록 제2마스크를 적층한 후 개방된 부위로 인 이온을 비정질실리콘층에 주입하는 단계와; 상기 제2마스크를 제거한 후 비정질실리콘층의 상부면에 고온으로 절연산화막을 적층하면서 비정질실리콘층을 동시에 결정화시키도록 하는 단계와; 상기 절연산화막 상에 상부폴리실리콘층을 적층한 후 커패시터가 형성될 부위에 제3마스크를 적층한 후 식각하여 폴리실리콘층을 노출하는 단계와; 상기 결과물의 NMOS영역에 NMOS게이트가 형성될 부위를 개방하도록 제4마스크를 적층한 후 폴리실리콘층에 인이온을 주입하여 마스킹식각으로 NMOS게이트, PMOS게이트 및커패시터를 형성하는 단계를 포함한 아날로그반도체소자의 듀얼게이트 형성방법을 제공함으로써 달성된다.SUMMARY OF THE INVENTION An object of the present invention is a semiconductor device comprising a PMOS region, an NMOS region, and a capacitor region on a semiconductor substrate, and after laminating an amorphous silicon layer on the semiconductor substrate, laminating a first mask having an open portion where a capacitor is to be formed; ; Injecting phosphorus ions into the amorphous silicon layer through the open portion of the first mask after the step, and then removing the first mask; After the step of laminating a second mask so as to open the site where the PMOS gate is to be formed on the PMOS region of the amorphous silicon layer and implanting phosphorus ions into the amorphous silicon layer to the open site; Removing the second mask and simultaneously crystallizing the amorphous silicon layer while laminating an insulating oxide film on the upper surface of the amorphous silicon layer at a high temperature; Stacking an upper polysilicon layer on the insulating oxide film, and then laminating a third mask on a portion where a capacitor is to be formed and etching to expose the polysilicon layer; Stacking a fourth mask so as to open a portion where the NMOS gate is to be formed in the resultant NMOS region, and injecting ions into the polysilicon layer to form an NMOS gate, a PMOS gate, and a capacitor by masking etching. It is achieved by providing a method for forming a dual gate of.
그리고, 상기 PMOS영역에서 PMOS게이트가 형성될 부위에 주입되는 인이온은 1E13 ∼ 1E15/㎠의 도오스량으로 진행하도록 하고, 상기 절연산화막을 적층하면서 비정질실리콘층을 결정화시킬 때, 600 ∼ 800℃의 온도범위에서 진행하도록 한다.In the PMOS region, phosphorus ions implanted in a portion where a PMOS gate is to be formed are allowed to proceed at a dose of 1E13 to 1E15 / cm 2, and when the amorphous silicon layer is crystallized while laminating the insulating oxide layer, 600 to 800 ° C. Proceed in the temperature range of.
이하, 본 발명에 따른 층간절연막 형성방법을 일실시예에 의거하여 상세하게 살펴 보도록 한다.Hereinafter, a method of forming an interlayer insulating film according to the present invention will be described in detail with reference to an embodiment.
도 1 내지 도 8은 본 발명에 따른 아날로그 반도체소자의 듀얼게이트 형성방법을 순차적으로 보인 도면이다.1 to 8 are views sequentially showing a method of forming a dual gate of an analog semiconductor device according to the present invention.
도 1 및 도 2는 반도체기판(10) 상에 비정질실리콘층(30)을 적층한 후 커패시터가 형성될 부위(45)가 개방된 제1마스크(40)를 적층하는 상태를 도시하고 있다.1 and 2 illustrate a state in which an amorphous silicon layer 30 is stacked on the semiconductor substrate 10, and then a first mask 40 having an open portion 45 where a capacitor is to be formed is stacked.
그리고, 상기 제1마스크(40)의 개방된 부위(45)를 통하여 인 이온을 비정질실리콘층(30)에 주입한 후 제1마스크(40)를 제거하도록 한다.In addition, after the phosphorus ions are injected into the amorphous silicon layer 30 through the open portion 45 of the first mask 40, the first mask 40 is removed.
도 3은 상기 단계 후에 비정질실리콘층(30)의 PMOS영역 상에 PMOS게이트가 형성될 부위를 개방하도록 제2마스크(50)를 적층한 후 개방된 부위로 인 이온을 비정질실리콘층(30)에 주입하는 상태를 도시하고 있다.FIG. 3 shows that the second mask 50 is stacked to open a portion where the PMOS gate is to be formed on the PMOS region of the amorphous silicon layer 30 after the above step, and then phosphorus ions are transferred to the amorphous silicon layer 30. The state to inject is shown.
이때, 상기 PMOS영역에서 PMOS게이트가 형성될 부위에 주입되는 인이온은 1E13 ∼ 1E15/㎠의 도오스(Dose)량으로 진행하도록 한다.At this time, the phosphorus ion implanted in the PMOS region in which the PMOS gate is to be formed has a dose of 1E13 to 1E15 / cm 2.
도 4는 상기 제2마스크(50)를 제거한 후 비정질실리콘층(30)의 상부면에 600∼ 800℃의 온도범위로 절연산화막(60)을 적층하면서 비정질실리콘층(30)을 동시에 결정화시켜 폴리실리콘층(30a)으로 형성하는 상태를 도시하고 있다.4 shows that the amorphous silicon layer 30 is simultaneously crystallized while the insulating mask 60 is laminated on the upper surface of the amorphous silicon layer 30 in a temperature range of 600 to 800 ° C. after removing the second mask 50. The state which forms with the silicon layer 30a is shown.
이때, 상기 제1,제2마스크(40)(50)의 개방부위(45)(55)로 주입된 인이온을 인하여 비정질실리콘층(30)의 그레인사이즈가 커지게 되어 PMOS게이트와 커패시터가 형성될 부위에 그레인사이즈 조대화영역(35)이 형성되어진다.At this time, the grain size of the amorphous silicon layer 30 is increased due to the phosphorus ion injected into the open portions 45 and 55 of the first and second masks 40 and 50 to form a PMOS gate and a capacitor. The grain size coarsening area | region 35 is formed in the site | part to be made.
그리고, 도 5는 상기 절연산화막(60) 상에 상부폴리실리콘층(70)을 적층한 후 커패시터가 형성될 부위에 제3마스크(80)를 적층한 후 식각하여 폴리실리콘층 (30)을 노출하는 상태를 도시하고 있다.5, after stacking the upper polysilicon layer 70 on the insulating oxide layer 60, the third mask 80 is laminated on the portion where the capacitor is to be formed and then etched to expose the polysilicon layer 30. The state of doing is shown.
그리고, 도 6은 상기 결과물의 NMOS영역에 NMOS게이트가 형성될 부위를 개방하도록 제4마스크(90)을 적층한 후 폴리실리콘층(30)에 인이온을 주입하는 상태를 도시하고 있다.6 illustrates a state in which in-ion is implanted into the polysilicon layer 30 after stacking the fourth mask 90 to open a portion where the NMOS gate is to be formed in the resultant NMOS region.
도 7은 상기 단계 후에 마스킹식각으로 NMOS게이트(100), PMOS게이트(110) 및 커패시터(120)를 형성하는 상태를 도시하고 있다.FIG. 7 illustrates a state in which the NMOS gate 100, the PMOS gate 110, and the capacitor 120 are formed by masking etching after the step.
도 8은 상기 결과물의 NMOS영역에서 액티브지역이 개방되도록 제5마스크 (130)을 적층한 후 LDD영역(135)에 아르세닉(As;Arsenic)이온을 주입하는 상태를 도시하고 있다.FIG. 8 illustrates a state in which Arsnic (As) ions are implanted into the LDD region 135 after the fifth mask 130 is stacked in such a manner that the active region is opened in the NMOS region.
따라서, 상기한 바와 같이, 본 발명에 따른 아날로그반도체소자의 듀얼게이트 형성방법을 이용하게 되면, PMOS게이트의 폴리실리콘층의 그레인사이즈를 인이온을 도핑하여 조대화시키므로 후속공정에서 보론이 침투하는 것을 차단하여 써브 쓰레쇼올드 전압의 변화를 방지하고, NMOS게이트의 폴리실리콘층에는 어닐링공정으로 조직을 결정화시킨 후에 인이온을 도핑하므로 폴리실리콘층의 조직 조대화를 방지하여 게이트의 채널링(Channeling)을 방지하므로 아날로그 반도체소자의 전기적인 특성을 향상시키도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when the dual gate formation method of the analog semiconductor device according to the present invention is used, the grain size of the polysilicon layer of the PMOS gate is coarsened by doping with ions, thereby preventing boron from penetrating in a subsequent process. Blocking prevents the change in the subthreshold voltage, and the polysilicon layer of the NMOS gate is doped with phosphorus ions after crystallization by annealing to prevent the coarsening of the polysilicon layer, thereby preventing the channeling of the gate. It is a very useful and effective invention to improve the electrical characteristics of the analog semiconductor device.
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