JPH11214687A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain reverse short channel effect due to increase of electric field and parasitic resistance, by forming halo injection layers on a channel surface with low concentration without contact with a source/drain. SOLUTION: After a gate electrode 3 is formed on a substrate or the surface of well 1 via a gate insulating film 2, ions are implanted by using the gate electrode 3 as a mask, and a low concentration region 4 of a source/drain is formed. Ions having the same conductivity type as the substrate or the well are obliquely implanted from a region side turning to a low concentration region of a drain or a source by using the gate electrode 3 as a mask, in such a manner that halo injection layers 5a, 5b as injection regions are formed just below the gate electrode 3 between an end portion of a region turning to a low concentration region of the source or the drain and a gate electrode center. After that, a side wall 6 is formed on a gate electrode side wall, and a high concentration region 7 of a source/drain is formed by using the gate electrode 3 and a side wall 6 as masks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a MOS transistor having a fine structure.

[0002]

2. Description of the Related Art In recent years, with the increasing integration of LSIs, transistors used have been increasingly miniaturized.
A transistor having a gate length of 0.2 to 0.3 μm has been required. When a transistor is miniaturized, problems such as lowering of threshold voltage and punch-through between a source and a drain become more severe due to a short channel effect. Therefore, various transistor structures that do not cause a short channel effect have been proposed.

[0003] One of the widely used methods is a halo injection method. This is a method in which a high-concentration impurity region of the same type as the substrate is formed so as to surround the source / drain portion, thereby suppressing punch-through between the source and drain.

Various types of halo injection have been proposed. For example, if a halo injection layer is present on the drain side, the electric field becomes large. Therefore, a method of halo injection only on the source side is disclosed in JP-A-6-349854 and JP-A-6-34985.
-350042 and JP-A-8-236758.

Conversely, if a halo injection layer is present on the source side, current characteristics are degraded due to parasitic resistance.
No. 307, for example. These methods have a problem in that a halo injection layer is provided only in one of the source and the drain, so that some implantation mask is required, and the method cannot be applied to a bidirectional transistor.
Therefore, a method of providing a halo injection layer on both the source and the drain is practical, and is disclosed in Japanese Patent Application Laid-Open No. Hei 5-347408.

Here, the manufacturing method will be described using a PMOS transistor as an example with reference to FIG.

First, as shown in FIG. 5A, a gate oxide film 52 is formed on an N-type substrate or N-type well 51, and thereafter, a gate electrode 53 is patterned. Next, FIG.
As shown in FIG. 4B, a P-type impurity is ion-implanted to form an impurity layer 54 which becomes a low concentration (P ⁻ ) region of source / drain.
To form Next, as shown in FIG. 5C, after a sidewall 55 is formed on the side wall of the gate electrode 53, an N-type impurity is ion-implanted, and an N impurity having a higher concentration than the substrate or the well 51 serving as a halo implanted layer is formed. The layer 56 is formed. Next, as shown in FIG. 5D, a P-type impurity is ion-implanted and the impurity region 5 serving as a high-concentration source / drain region is formed.
7 is formed. Thus, a PMOS transistor having a halo injection layer is formed.

Further, in the present structure, since the P ⁻ layer 54 in the LDD structure exists near the channel surface, there is an effect that the resistance due to the halo injection layer does not affect the current characteristics.

[0009]

However, in the above-mentioned conventional method, the punch-through is suppressed by the halo injection layer surrounding the source / drain, so that the concentration of the halo injection layer must be considerably high. Region X in FIG.
Is equivalent to Increasing the concentration of the halo injection layer increases the electric field, lowering the breakdown voltage and deteriorating the hot carrier breakdown voltage, increasing the junction capacitance, and increasing the threshold voltage when the gate length is shortened. There is a problem that stable characteristics cannot be obtained due to the channel effect.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a method of manufacturing a MOS transistor having stable characteristics, which suppresses an increase in electric field and junction capacitance and does not cause an inverse short channel effect. .

[0011]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a gate electrode on a surface of a substrate or a well via a gate insulating film; By ion implantation, the source /
Forming a low-concentration region of the drain, and using the gate electrode as a mask, forming a source region such that an implantation region is formed immediately below the gate electrode between the end of the low-concentration region of the drain and the center of the gate electrode. Injecting ions of the same conductivity type as that of the substrate or well in the oblique direction from the side of the low concentration region, and using the gate electrode as a mask, the end of the low concentration region of the source and the center of the gate electrode. Implanting ions of the same conductivity type as that of the substrate or well in an oblique direction from the side of the low concentration region of the drain so that an implantation region is formed immediately below the gate electrode between the gate electrode and the gate electrode. A sidewall is formed on the side wall, and the source / source is formed using the gate electrode and the sidewall as a mask.
It is characterized in that a high concentration region of the drain is formed.

According to a second aspect of the present invention, in a method of manufacturing a semiconductor device according to the present invention, after a gate electrode is formed on a substrate or a well surface via a gate insulating film, ions are implanted using the gate electrode as a mask. After forming a low concentration region of the source / drain, a sidewall is formed on the side wall of the gate electrode, and then, using the gate electrode and the sidewall as a mask, an end portion of the region to be a low concentration region of the drain and the center of the gate electrode. Implant ions of the same conductivity type as the substrate or the well in a direction oblique to the substrate or the well from the side where the source is a low-concentration region so that an implantation region is formed immediately below the gate electrode between the substrate and the well. And using the gate electrode and the sidewalls as masks, just below the gate electrode between the end of the region that becomes the low concentration region of the source and the center of the gate electrode. Injecting ions of the same conductivity type as the substrate or the well in an oblique direction from the side of the low concentration region of the drain so that an implantation region is formed, and using the gate electrode and the sidewall as a mask. A high-concentration source / drain region is formed.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the present invention, after forming the high-concentration region of the source / drain, an impurity concentration is formed in a junction region between the high-concentration region of the source / drain and the substrate. 3. The semiconductor device according to claim 1, wherein an impurity of the same conductivity type as that of the source / drain is implanted at a lower concentration than that of the high concentration region of the source / drain so that a peak of the peak comes. It is a manufacturing method.

Further, according to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the present invention, after forming the high-concentration regions of the source / drain, an interlayer insulating film is formed. Then, a contact hole for contact is formed, and thereafter, the source / drain has the same conductivity type as the source / drain so that the impurity concentration peaks at the junction region between the high concentration region of the source / drain and the substrate. 3. The method according to claim 1, wherein an impurity having a lower concentration than the high concentration region is implanted.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a partial sectional view of a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention, and FIG. FIG. 4 is a partial cross-sectional view of a manufacturing process of the semiconductor device according to the third embodiment of the present invention, and FIG. 4 is a partial cross-sectional view of the manufacturing process of the semiconductor device of the fourth embodiment of the present invention. 1 to 4,
1 is an N-type silicon substrate or N-type well, 2 is a gate oxide film, 3 is a gate electrode, 4 is a low concentration impurity region of source / drain, 5 is a halo injection layer, 6 is a side wall, 7
Is a high concentration impurity region of source / drain, and 8 is a first P
Reference numeral 9 denotes a CVD oxide film, 10 denotes a contact hole, and 11 denotes a second P-type low concentration impurity region.

Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 1A, a gate oxide film 2 is formed on an N-type silicon substrate (or N-type well) 1 by 8.
The film is formed at a temperature of 50 to 80 ° by a thermal oxidation method at 00 to 900 ° C., and then phosphorus-doped polysilicon is deposited by CVD at a temperature of 20 ° C.
After the formation, the gate electrode 3 is patterned by a known photolithography / etching technique. In this embodiment, the gate length is 0.3 μm. The gate electrode is not limited, and may have a single-layer structure of polysilicon or silicide, or a salicide structure.

Next, as shown in FIG. 1 (b), boron difluoride is applied at 1 × 10 ^{13 to} 3 × 10 ¹³ c at 20 to 30 keV.
Ion implantation is performed under the condition of m ^-2 to form a low concentration source / drain region 4 made of a P ^- layer.

Next, as shown in FIG. 1C, phosphorus is used for a punch-through stopper at an inclination of 50 to 80 °, an acceleration energy of 200 to 300 keV, and a total dose of 1
× rotated implanted with ^{10 13 ~3 × 10 13 cm -2} , N +
The mold halo injection layers 5a and 5b are formed. Note that, depending on the ion implanter, split implantation (step implantation) may be performed. Here, the rotary ion implantation means that oblique ion implantation is first performed from one side of the source / drain in the channel direction.
Next, oblique ion implantation is performed in the channel direction from the other side of the source / drain.

This condition is a condition that easily penetrates through the gate electrode, and the halo injection layers 5a and 5b are formed immediately below the gate electrode between the low concentration region 4 of the source / drain and the center of the gate electrode. In addition, the opposite direction of the implanted side (the source side when implanted from the drain side)
There is also a region which is implanted through the gate electrode 3 in the silicon substrate 1, but this region is canceled by the later ion implantation for forming high-concentration impurities in the source and drain, so that
Not shown in the figure.

Next, as shown in FIG. 1D, after depositing a CVD oxide film at 500 to 1000.degree., The sidewall 6 is formed by etching back. Here, a sidewall width of 0.05 to 0.1 μm was obtained. Then, boron difluoride is added at 20 to 40 keV, 1 ×
The source / drain high concentration region 7 is formed by ion implantation under the condition of 10 ¹⁵ to 4 × 10 ¹⁵ cm ⁻² .
Actually, there is a heat treatment step for activating the impurity regions after this.

In this embodiment, the injection of the punch-through stopper (formation of the halo injection layers 5a and 5b) is performed before the formation of the sidewalls. However, as a second embodiment of the present invention,
The injection of the punch-through stopper may be performed after the formation of the sidewall. In this case, as shown in FIG. 2, the concentration profile in the channel region reflects the shape of the sidewall, and is particularly applicable to the case where the electric field at the source / drain ends needs to be relaxed.

As a third embodiment, as shown in FIG. 3, after forming the high-concentration source / drain regions in the present invention, boron difluoride is added at 80 to 100 ke.
V, by ion implantation under the condition of 0.1 × 10 ¹³ to 1 × 10 ¹³ cm ⁻² , ion implantation is performed so that an impurity peak comes to a junction region between the source / drain and the silicon substrate. This is effective when it is necessary to reduce the parasitic capacitance between the silicon substrate.

Further, as a fourth embodiment, as shown in FIG. 4, after forming the high-concentration source / drain regions in the present invention, a CVD oxide film 9 as an interlayer insulating film is formed.
Is deposited, a contact hole for connection between the wiring and the source / drain is opened, and boron
By performing ion implantation under the conditions of 0 keV and 0.1 × 10 ¹² to 1 × 10 ¹² cm ⁻² , depending on the transistor used for halo implantation, the bottom surface side of the source / drain is affected, and substantial source / drain This is effective when it is necessary to prevent penetration of metal that occurs when the depth becomes shallow.

In the above embodiment, a PMOS transistor has been described as an example. However, it is needless to say that the present invention can be applied to an NMOS transistor.

[0027]

As described in detail above, by using the present invention, the halo injection layer has a low concentration at the channel surface without contacting the source / drain, so that the halo injection layer may have an increased electric field or parasitic resistance. Halo implantation is particularly effective in the region where the punch-through occurs (in the direction of the channel in the direction of the substrate, which is about the same as the depth of the source / drain). (The injection from the source side and the injection from the drain side overlap), so that it effectively functions as a stopper layer.

Also, due to the structure in which the concentration distribution increases from the source / drain ends toward the center of the channel (low concentration regions 5b of source / drain, N-type silicon substrate or N-type well 1, halo injection layers 5a, 5b). In addition, unlike the conventional halo injection method, problems such as an increase in junction capacitance and a decrease in withstand voltage are eliminated, and a highly reliable MOS transistor having stable characteristics can be obtained.

According to the second aspect of the present invention, the layer injected into the lower portion of the channel reflects the shape of the sidewall and is formed at a position further away from the drain end. This is effective when electric field relaxation is required.

Further, by using the present invention described in claim 3 or claim 4, the junction capacitance can be further reduced. Further, by using the present invention described in claim 4, the impurity channel can be reduced. Exudation to the part can be suppressed.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional view of a manufacturing step diagram of the semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a partial cross-sectional view of a manufacturing step of a semiconductor device according to a third embodiment of the present invention;

FIG. 4 is a partial cross-sectional view of a manufacturing step of a semiconductor device according to a fourth embodiment of the present invention;

FIG. 5 is a manufacturing process diagram of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 N-type silicon substrate or N-type well 2 Gate oxide film 3 Gate electrode 4 Low-concentration region of source / drain 5a, 5b Halo injection layer 6 Sidewall 7 High-concentration region of source / drain 8 First P-type low-concentration impurity Region 9 CVD oxide film 10 Contact hole 11 Second P-type low concentration region

Claims (4)

[Claims] A gate electrode is formed on a surface of a substrate or a well via a gate insulating film, and then ion implantation is performed using the gate electrode as a mask to form a low-concentration source / drain region. Using the electrode as a mask,
An oblique direction from the side of the low concentration region of the source, such that the injection region is formed immediately below the gate electrode between the end of the region to be the low concentration region of the drain and the center of the gate electrode,
Implanting ions of the same conductivity type as the substrate or well, and using the gate electrode as a mask, an implantation region is formed immediately below the gate electrode between the end of the region that becomes the low concentration region of the source and the center of the gate electrode. As described above, ions of the same conductivity type as that of the substrate or well are implanted obliquely from the side of the drain region where the low-concentration region is formed, and then a sidewall is formed on the side wall of the gate electrode. A method for manufacturing a semiconductor device, comprising forming a high-concentration source / drain region using the side wall as a mask. 2. After forming a gate electrode on a surface of a substrate or a well via a gate insulating film, ion-implanting is performed using the gate electrode as a mask to form a low-concentration source / drain region. A sidewall is formed on the side wall of the electrode, and then, using the gate electrode and the sidewall as a mask, an injection region is formed immediately below the gate electrode between the end of the region to be a low concentration region of the drain and the center of the gate electrode. Implanting ions of the same conductivity type as the substrate or the well in a direction oblique to the substrate or the well from the side of the low concentration region of the source, and using the gate electrode and the sidewall as a mask, The low-concentration region of the drain is formed so that the injection region is formed immediately below the gate electrode between the end of the region that becomes the low-concentration region and the center of the gate electrode. Ions of the same conductivity type as the substrate or the well are implanted obliquely from the side of the region to be formed, and a high-concentration source / drain region is formed using the gate electrode and the sidewall as a mask. , A method of manufacturing a semiconductor device. 3. After the formation of the high-concentration source / drain region, the source / drain has the same conductivity type as the source / drain so that the impurity concentration peaks at a junction region between the high-concentration source / drain region and the substrate. / Implanting impurities at a lower concentration than the high concentration region of the drain,
A method for manufacturing a semiconductor device according to claim 1. 4. After the formation of the high-concentration source / drain regions, an interlayer insulating film is formed, and a contact hole for contact between a source / drain and a wiring is formed in the interlayer insulating film. Injecting impurities of the same conductivity type as that of the source / drain and lower concentration than the source / drain high concentration region so that a peak of the impurity concentration comes to a junction region between the high concentration region of the drain and the substrate. The method for manufacturing a semiconductor device according to claim 1, wherein