JP4118255B2 - Manufacturing method of MOS transistor - Google Patents

Description

The present invention particularly relates to a method of manufacturing a MOS transistor suitable for miniaturization.

  Conventionally, an N-channel MOS transistor mounted on a semiconductor device is generally known as shown in FIG. In FIG. 67, 1 is a semiconductor substrate which is a P-type silicon (Si) substrate, 2 surrounds an N-channel MOS transistor formation region for forming an N-channel MOS transistor on one main surface of the semiconductor substrate, It is an element isolation oxide film for electrically insulating elements adjacent to each other.

  3 is a channel stopper region made of a P (+) type impurity region formed under the element isolation oxide film, and 4 and 5 are a pair of channels formed on one main surface of the semiconductor substrate with the channel region 6 interposed therebetween. A source / drain region 7 is a gate electrode formed on one main surface of the semiconductor substrate 1 located between the pair of source / drain regions 4 and 5 via a gate insulating film 7. The pair of source / drain regions 4 and 5 and the gate electrode 7 constitute an N-channel MOS transistor.

  However, in the N-channel type MOS transistor configured as described above, the following problems occur as the size is reduced. That is, when the N-channel MOS transistor is in a non-conducting state, one of the pair of source / drain regions 4 and 5 that functions as the drain (hereinafter, uniquely defined as the drain region 4, The hot / carrier is generated by a high electric field generated at an end portion in contact with the channel region 6 of the source / drain region is uniquely defined as the source region 5), and the generated hot carrier is injected into the gate insulating film 7. . The hot carriers injected into and trapped in the gate insulating film 7 cause deterioration of the transistor characteristics over time, such as a change in the threshold voltage of the transistor and a decrease in drain current, so-called hot carrier deterioration.

  That is, the above-described hot carrier deterioration is caused by electrons in the channel region 6 gaining energy from the electric field in the direction along the channel and becomes hot, and is higher than the energy barrier height at the interface between the semiconductor substrate 1 and the gate insulating film 7. High energy was obtained by channel hot electron (CHE) injection, which is a phenomenon in which hot electrons having large energy are injected into the gate insulating film 7 across the energy barrier, or by a large electric field in the vicinity of the drain region 4. Drain which is a phenomenon in which electrons in the channel region 6 generate electron-hole pairs by ionization collision with the lattice or avalanche multiplication, and these electrons or holes or both become hot and are injected into the gate insulating film 7 Avalanche hot carrier (DAHC) injection causes electrons or holes to drain An interface state or trap in the interface between the semiconductor substrate 1 and the gate insulating film 7 in the vicinity and the gate insulating film 7 in the vicinity thereof is trapped or generates an interface state. As a result, transistor characteristics (threshold voltage) Change, drain current decrease, etc.).

  As one measure for alleviating such a problem, a MOS transistor called a so-called LDD structure shown in FIG. 67 is known. 67, the same reference numerals as those shown in FIG. 66 denote the same or corresponding parts. Reference numerals 4 and 5 denote a pair of source / drains formed on one main surface of the semiconductor substrate with the channel region 6 interposed therebetween. In each of the regions, the low concentration diffusion regions 4a and 5a whose ends are in contact with the channel region 6 are located outside the channel region 6 and are integrally formed with the low concentration diffusion regions 4a and 5a. It consists of high concentration diffusion regions 4b and 5b. Reference numeral 9 denotes a side wall made of an oxide film formed in contact with the side surface of the gate electrode 8, the side surface of the gate insulating film 7, and one main surface of the semiconductor substrate, that is, the source / drain regions 4 and 5. The pair of source / drain regions 4 and 5, the gate electrode 7 and the sidewall constitute an N channel type MOS transistor.

  The N-channel MOS transistor configured as described above is manufactured as follows. First, a gate insulating film 7 and a gate electrode 8 are formed on one main surface of the semiconductor substrate 1, and an N-type conductivity impurity is implanted into one main surface of the semiconductor substrate 1 using the gate electrode 8 as a part of a mask. Thus, a pair of low concentration diffusion regions 4a and 5a is formed. Next, an oxide film layer is formed on the surface of the gate electrode 8 and on the pair of low-concentration diffusion regions 4a and 5a by the CVD method, and the oxide film layer is etched by anisotropic etching to form side surfaces of the gate electrode 8. A side wall 9 is formed in contact with the side surface of the gate insulating film 7 and the pair of low concentration diffusion regions 4a and 5a.

  Then, as shown in FIG. 68, N-type conductivity type impurities are implanted into one main surface of the semiconductor substrate 1 using the gate electrode 8 and the side wall 9 as a part of the mask to form the high concentration diffusion regions 4b and 5b. In this way, an N-channel MOS transistor is obtained. That is, the sidewall 9 functions as a mask for forming the high concentration regions 4b and 5b of the pair of source / drain regions 4 and 5 in a self-aligning manner.

  However, in the N-channel MOS transistor configured as described above, the end of the drain region 4 (uniquely defined) in contact with the channel region 6 is the low concentration region 4a. Although the electric field of the portion is relaxed and hot carrier injection into the gate insulating film 7 is suppressed and the reliability is improved, as the miniaturization is further advanced, the side wall 9 required for the LDD structure is formed. Drain caused by mobility reduction due to generation of interface states at the interface between the sidewall 9 and the semiconductor substrate 1 (source / drain regions 4 and 5) due to hot carriers injected into the sidewall 9 and trapped in the sidewall 9 The current deteriorated.

The present invention has been made in view of the above points, and in the case of having a sidewall, the interface state at the interface between the sidewall and the semiconductor substrate is suppressed even when miniaturized, and hot carriers are generated. An object of the present invention is to obtain a method of manufacturing a MOS transistor in which the probability of trapping at the interface state is reduced and hot carrier deterioration is unlikely to occur, that is, hot carrier resistance is improved.

  The MOS transistor according to the first aspect of the present invention has a sidewall formed in contact with the side surface of the gate electrode, the side surface of the gate insulating film, and one main surface of the semiconductor substrate. This is made of an oxide film into which nitrogen is introduced so that the concentration distribution in the cross section perpendicular to the one principal surface has a peak at the interface with the one principal surface of the semiconductor substrate.

  The MOS transistor according to the second aspect of the present invention has a sidewall formed in contact with the side surface of the gate electrode, the side surface of the gate insulating film, and one main surface of the semiconductor substrate. An oxide film having a substantially L-shaped longitudinal section having a vertical portion in contact with the side surface of the gate insulating film and a side surface of the gate insulating film and a bottom portion in contact with one main surface of the semiconductor substrate; and the vertical portion and the bottom portion of the oxide film And polysilicon having nitrogen introduced therein.

  The MOS transistor according to the third aspect of the present invention has a sidewall formed in contact with the side surface of the gate electrode, the side surface of the gate insulating film, and one main surface of the semiconductor substrate, and nitrogen is introduced into the gate electrode. In addition, the sidewall has an oxide film into which nitrogen is introduced.

  A semiconductor device according to a fourth aspect of the present invention includes an N-channel MOS transistor having a sidewall and a P-channel MOS transistor having a sidewall, and includes an N-channel MOS transistor and a P-channel MOS transistor. Each side wall of the MOS transistor is made of an oxide film into which nitrogen is introduced.

  According to a fifth aspect of the present invention, there is provided a semiconductor device including an N channel type MOS transistor having a sidewall and a P channel type MOS transistor having a sidewall. Each sidewall of the MOS transistor is made of an oxide film into which nitrogen is introduced, a metal silicide layer is formed on the gate electrode and the pair of source / drain regions of the N-channel MOS transistor, and the P-channel A metal silicide layer is formed on the gate electrode and the pair of source / drain regions of the type MOS transistor.

  According to a sixth aspect of the present invention, there is provided a MOS transistor manufacturing method comprising: forming an oxide film layer on a surface of a gate electrode and an exposed surface of a semiconductor substrate by a CVD method; and forming nitrogen ions from the surface of the oxide film layer. Etching the oxide film layer implanted with nitrogen to form a sidewall in contact with the side surface of the gate electrode, the side surface of the gate insulating film, and one main surface of the semiconductor substrate. It is provided.

  According to a seventh aspect of the present invention, there is provided a MOS transistor manufacturing method comprising: forming an oxide film layer on a surface of a gate electrode and an exposed surface of a semiconductor substrate by a CVD method; and forming polysilicon on the surface of the oxide film layer. A step of forming a layer, a step of injecting nitrogen ions into the polysilicon layer from the surface of the polysilicon layer, a step of diffusing nitrogen injected into the polysilicon layer into the oxide film layer, and removing the polysilicon layer And a step of etching the oxide film layer into which nitrogen has been implanted to form a sidewall in contact with the side surface of the gate electrode, the side surface of the gate insulating film, and one main surface of the semiconductor substrate.

  According to an eighth aspect of the present invention, there is provided a MOS transistor manufacturing method comprising: forming an oxide film layer on a surface of a gate electrode and an exposed surface of a semiconductor substrate by a CVD method; and forming a polysilicon film on the surface of the oxide film layer. Forming a layer, injecting nitrogen ions into the polysilicon layer from the surface of the polysilicon layer, etching the polysilicon layer into which nitrogen has been implanted, etching the oxide film layer, and And an oxide film having a vertical section having a substantially L-shape with a vertical portion in contact with the side surface of the gate insulating film and a bottom portion in contact with one main surface of the semiconductor substrate, and in contact with the vertical portion and the bottom portion of the oxide film. And a step of forming a sidewall having polysilicon into which nitrogen has been introduced.

  According to a ninth aspect of the present invention, there is provided a MOS transistor manufacturing method comprising: forming an oxide film layer on a surface of a gate electrode and an exposed surface of a semiconductor substrate by a CVD method; and forming nitrogen ions from the surface of the oxide film layer. In the oxide film layer at least on the side surface of the gate electrode and the inner region in contact with the side surface of the gate oxide film, the main surface of the semiconductor substrate where the exposed surface of the gate electrode and the semiconductor substrate is located, and the oxide film layer Etching to form a sidewall having an oxide film into which nitrogen is introduced in contact with the side surface of the gate electrode, the side surface of the gate insulating film, and one main surface of the semiconductor substrate.

  According to a tenth aspect of the present invention, there is provided a method of manufacturing an N channel type MOS transistor, wherein a gate electrode is used as a part of a mask and an N type conductivity type impurity is implanted into one main surface of a semiconductor substrate to form a pair of source / drain. A step of forming a low concentration diffusion region of the region, a step of forming an oxide film layer on the surface of the gate electrode and the low concentration diffusion region of the pair of source / drain regions by a CVD method, and from the surface of the oxide film layer A step of injecting nitrogen ions into the oxide film layer, and a side of the oxide film layer into which nitrogen has been implanted is in contact with the side surface of the gate electrode, the side surface of the gate insulating film, and the low concentration diffusion region of the pair of source / drain regions A step of forming a wall, and an impurity of an N-type conductivity type is implanted into one main surface of the semiconductor substrate using the gate electrode and the sidewall as a part of a mask to It is provided with a forming a doped diffusion region.

  According to an eleventh aspect of the present invention, there is provided a method of manufacturing an N channel type MOS transistor, wherein a gate electrode is used as a part of a mask and an N type conductivity type impurity is implanted into one main surface of a semiconductor substrate. A step of forming a low concentration diffusion region of the drain region, a step of forming an oxide film layer on the surface of the gate electrode and the low concentration diffusion region of the pair of source / drain regions by a CVD method, and on the surface of the oxide film layer Forming a polysilicon layer on the surface, injecting nitrogen ions from the surface of the polysilicon layer into the polysilicon layer, diffusing nitrogen injected into the polysilicon layer into the oxide film layer, and polysilicon layer The oxide film layer into which nitrogen has been implanted is etched to remove side walls in contact with the side surfaces of the gate electrode, the side surfaces of the gate insulating film, and the low concentration diffusion regions of the pair of source / drain regions. And forming a high concentration diffusion region of the pair of source / drain regions by implanting an N-type conductivity type impurity into one main surface of the semiconductor substrate using the gate electrode and the sidewall as a part of the mask. Forming a process.

  According to a twelfth aspect of the present invention, there is provided a method of manufacturing an N channel type MOS transistor, wherein a gate electrode is used as a part of a mask and an N type conductivity type impurity is implanted into one main surface of a semiconductor substrate. A step of forming a low concentration diffusion region of the drain region, a step of forming an oxide film layer on the surface of the gate electrode and the low concentration diffusion region of the pair of source / drain regions by a CVD method, and on the surface of the oxide film layer Forming a polysilicon layer, injecting nitrogen ions into the polysilicon layer from the surface of the polysilicon layer, etching the polysilicon layer into which nitrogen has been implanted, etching the oxide film layer, and A longitudinal section having a vertical portion in contact with the side surface of the electrode and the side surface of the gate insulating film and a bottom portion in contact with the low concentration diffusion region of the pair of source / drain regions is substantially L-shaped. A step of forming a sidewall having an oxide film and a polysilicon formed in contact with a vertical portion and a bottom portion of the oxide film and introduced with nitrogen; and a gate electrode and the sidewall are part of a mask And a step of forming a high-concentration diffusion region of a pair of source / drain regions by injecting an N-type conductivity type impurity into one main surface of the semiconductor substrate.

  According to a thirteenth aspect of the present invention, there is provided a method of manufacturing an N channel type MOS transistor, wherein a gate electrode is used as a part of a mask and an N type conductivity type impurity is implanted into one main surface of a semiconductor substrate. A step of forming a low concentration diffusion region of the drain region, a step of forming an oxide film layer by a CVD method on the surface of the gate electrode and the low concentration diffusion region of the pair of source / drain regions, and on the surface of the oxide film layer A step of implanting nitrogen ions from at least a side surface of the gate electrode and the side surface of the gate oxide film, a gate electrode, and a low concentration diffusion region of the pair of source / drain regions; The sidewall having an oxide film into which nitrogen is introduced in contact with the side surface of the gate electrode, the side surface of the gate insulating film, and the low concentration diffusion region of the pair of source / drain regions And forming a high concentration diffusion region of a pair of source / drain regions by implanting an N-type conductivity type impurity into one main surface of the semiconductor substrate using the gate electrode and the sidewall as a part of the mask. Process.

  According to a fourteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a first gate electrode of an N-channel MOS transistor; a second gate electrode of a P-channel MOS transistor; and an exposed surface of a semiconductor substrate. A step of forming an oxide film layer by a CVD method, covering the surface of the oxide film layer located on the P-channel MOS transistor formation region, and nitrogen from the surface of the oxide film layer located on the N-channel MOS transistor formation region A step of implanting ions into the oxide film layer, and etching the oxide film layer located on the N-channel MOS transistor formation region into which nitrogen has been implanted to form the side surfaces of the first gate electrode and the first gate insulating film Forming a sidewall of the N-channel MOS transistor in contact with the side surface and one main surface of the semiconductor substrate.

  According to a fifteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a first gate electrode of an N-channel MOS transistor; a second gate electrode of a P-channel MOS transistor; and an exposed surface of a semiconductor substrate. A step of forming an oxide film layer by a CVD method, a step of injecting nitrogen ions into the oxide film layer from the surface of the oxide film layer, and etching the oxide film layer into which nitrogen has been implanted to form a first gate electrode Forming a first sidewall of the N-channel MOS transistor in contact with the side surface, the side surface of the first gate insulating film, and one main surface of the semiconductor substrate; and the side surface of the second gate electrode and the second gate insulating film And a step of forming a second side wall of the P-channel MOS transistor in contact with one main surface of the semiconductor substrate.

  According to a sixteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein an N type conductivity impurity is formed by covering a P channel type MOS transistor formation region and using the first gate electrode of the N channel type MOS transistor as a part of a mask. Forming a low-concentration diffusion region of the pair of first source / drain regions of the N-channel MOS transistor, and on the surface of the first gate electrode and the second gate electrode of the P-channel MOS transistor And a step of forming an oxide film layer on the exposed surface of the semiconductor substrate by a CVD method and a surface of the oxide film layer located on the P-channel MOS transistor formation region and located on the N-channel MOS transistor formation region A step of injecting nitrogen ions into the oxide film layer from the surface of the oxide film layer; and an N-channel MOS transistor in which nitrogen is implanted An N-channel type in which the oxide film layer located on the formation region is etched to contact the side surface of the first gate electrode, the side surface of the first gate insulating film, and the low concentration diffusion region of the pair of first source / drain regions The first sidewall of the MOS transistor is formed, and the oxide film layer located on the P-channel MOS transistor formation region is etched so that the side surface of the second gate electrode, the side surface of the second gate insulating film, and the semiconductor substrate Forming a second sidewall of the P-channel MOS transistor in contact with the exposed surface of the semiconductor substrate, covering the P-channel MOS transistor formation region, and using the first gate electrode and the first sidewall as part of the mask A step of implanting an N-type conductivity type impurity to form a high-concentration diffusion region of the pair of first source / drain regions, and an N-channel MOS transistor A pair of P-channel MOS transistors are formed by implanting a P-type conductivity type impurity into one main surface of the semiconductor substrate, covering the transistor formation region and using the second gate electrode and the second sidewall as a part of the mask. And a step of forming a second source / drain region.

  According to a seventeenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of covering a P channel type MOS transistor formation region and removing an N type conductivity type impurity using the first gate electrode of the N channel type MOS transistor as a part of a mask. Implanting and forming a low-concentration diffusion region of the pair of first source / drain regions of the N-channel MOS transistor, on the surface of the first gate electrode and the second gate electrode of the P-channel MOS transistor, and Forming an oxide film layer on the exposed surface of the semiconductor substrate by a CVD method, injecting nitrogen ions into the oxide film layer from the surface of the oxide film layer, and etching the oxide film layer into which nitrogen has been implanted; The N-channel MOS transistor is in contact with the side surface of the first gate electrode, the side surface of the first gate insulating film, and the low concentration diffusion region of the pair of first source / drain regions. Forming a first sidewall of the transistor, and forming a second sidewall of the P-channel MOS transistor in contact with the side surface of the second gate electrode, the side surface of the second gate insulating film, and one main surface of the semiconductor substrate. And a step of forming an n-type conductivity type impurity, covering the P-channel MOS transistor formation region and using the first gate electrode and the first sidewall as a part of the mask to form a pair of first source / A step of forming a high-concentration diffusion region in the drain region and an N-channel MOS transistor formation region are implanted, and a P-type conductivity type impurity is implanted using the second gate electrode and the second sidewall as part of the mask. And a step of forming a pair of second source / drain regions of the P-channel MOS transistor.

  According to an eighteenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein an N-type conductivity type impurity is covered with a first gate electrode of an N-channel MOS transistor as a part of a mask covering a P-channel MOS transistor formation region. Implanting and forming a low-concentration diffusion region of the pair of first source / drain regions of the N-channel MOS transistor, on the surface of the first gate electrode and the second gate electrode of the P-channel MOS transistor, and Forming an oxide film layer on the exposed surface of the semiconductor substrate by a CVD method, injecting nitrogen ions into the oxide film layer from the surface of the oxide film layer, and etching the oxide film layer into which nitrogen has been implanted; The N-channel MOS transistor is in contact with the side surface of the first gate electrode, the side surface of the first gate insulating film, and the low concentration diffusion region of the pair of first source / drain regions. Forming a first sidewall of the transistor, and forming a second sidewall of the P-channel MOS transistor in contact with the side surface of the second gate electrode, the side surface of the second gate insulating film, and one main surface of the semiconductor substrate. And a step of forming an n-type conductivity type impurity, covering the P-channel MOS transistor formation region and using the first gate electrode and the first sidewall as a part of the mask to form a pair of first source / A step of forming a high-concentration diffusion region in the drain region and an N-channel MOS transistor formation region are implanted, and a P-type conductivity type impurity is implanted using the second gate electrode and the second sidewall as part of the mask. Forming a pair of second source / drain regions of the P-channel MOS transistor, the surface of the first gate electrode, the surface of the second gate electrode, Surface of the source / drain regions, and the surface of the second source / drain region is provided with a forming a metal silicide layer.

(Function)
In the first aspect of the present invention, even if nitrogen introduced into the sidewall and having a peak at the interface with the semiconductor substrate is miniaturized, the interface state at the interface between the sidewall and the semiconductor substrate is reduced. Suppresses and reduces the probability that generated hot carriers are trapped in the interface state.

  In the second invention of the present invention, nitrogen having a peak at the interface with the semiconductor substrate, which is introduced into the polysilicon constituting the sidewall, is refined at the interface between the sidewall and the semiconductor substrate. The interface state is suppressed, and the probability that generated hot carriers are trapped in the interface state is reduced.

  In the third invention of the present invention, the nitrogen introduced into the gate electrode suppresses the diffusion of impurities introduced into the gate electrode to reduce the resistance, and the nitrogen introduced into the sidewall is fine. Even if the temperature is increased, the interface state at the interface between the sidewall and the semiconductor substrate is suppressed, and the probability that generated hot carriers are captured by the interface state is reduced.

  In the fourth invention of the present invention, even if the nitrogen introduced into each of the sidewalls of the N-channel MOS transistor and the P-channel MOS transistor is miniaturized, the interface at the interface between the sidewall and the semiconductor substrate. The level is suppressed, and the probability that generated hot carriers are trapped in the interface state is reduced.

  According to a fifth aspect of the present invention, there is provided a semiconductor device according to a fifth aspect of the present invention, wherein nitrogen introduced into the sidewalls of the N-channel MOS transistor and the P-channel MOS transistor is reduced at the interface between the sidewall and the semiconductor substrate. The interface state is suppressed, and the probability that generated hot carriers are trapped in the interface state is reduced.

  In the sixth aspect of the present invention, an oxide film layer is formed by a CVD method, nitrogen ions are implanted into the oxide film layer, and then the oxide film layer implanted with nitrogen is etched to form a sidewall. Therefore, nitrogen having a peak at the interface between the sidewall and the semiconductor substrate can be easily introduced into the sidewall.

  In the seventh aspect of the present invention, an oxide film layer is formed by a CVD method, a polysilicon layer is formed on the surface of the oxide film layer, and nitrogen ions are implanted into the polysilicon layer to form a polysilicon layer. After the nitrogen implanted into the oxide layer is diffused into the oxide film layer, the oxide film layer implanted with nitrogen is etched to form a sidewall. Can be installed on the wall.

  In the eighth invention of the present invention, an oxide film layer is formed by a CVD method, a polysilicon layer is formed on the surface of the oxide film layer, nitrogen ions are implanted into the polysilicon layer, Since the sidewalls are formed by etching the polysilicon layer and the oxide film layer into which nitrogen has been implanted, nitrogen having a peak at the interface between the sidewalls and the semiconductor substrate can be easily introduced into the sidewalls.

  In the ninth aspect of the present invention, an oxide film layer is formed by a CVD method, nitrogen ions are implanted into the oxide film layer, and then the oxide film layer is etched to form sidewalls. Nitrogen having a peak at the interface between the wall and the semiconductor substrate can be easily introduced into the sidewall.

  In the tenth aspect of the present invention, an oxide film layer is formed by a CVD method, nitrogen ions are implanted into the oxide film layer, and the oxide film layer into which nitrogen is implanted is etched to form a sidewall. Therefore, nitrogen having a peak at the interface between the sidewall and the semiconductor substrate can be easily introduced into the sidewall.

  In the eleventh aspect of the present invention, an oxide film layer is formed by a CVD method, a polysilicon layer is formed on the surface of the oxide film layer, and nitrogen ions are implanted into the polysilicon layer. After the nitrogen implanted into the layer is diffused into the oxide film layer, the oxide film layer into which nitrogen is implanted is etched to form a sidewall, so that nitrogen having a peak at the interface between the sidewall and the semiconductor substrate can be easily formed. Can be installed on the sidewall.

  In the twelfth aspect of the present invention, an oxide film layer is formed by a CVD method, a polysilicon layer is formed on the surface of the oxide film layer, nitrogen ions are implanted into the polysilicon layer, Since the implanted polysilicon layer and oxide film layer are etched to form the sidewall, nitrogen having a peak at the interface between the sidewall and the semiconductor substrate can be easily introduced into the sidewall.

  In the thirteenth aspect of the present invention, an oxide film layer is formed by a CVD method, nitrogen ions are implanted into the oxide film layer, and then the oxide film layer is etched to form sidewalls. Nitrogen having a peak at the interface between the wall and the semiconductor substrate can be easily introduced into the sidewall.

  In the fourteenth aspect of the present invention, an oxide film layer is formed by a CVD method, nitrogen ions are implanted into the oxide film layer located on the N-channel MOS transistor formation region, and then the nitrogen is implanted. Since the oxide film layer is etched to form the sidewall of the N-channel MOS transistor, nitrogen having a peak at the interface between the sidewall of the N-channel MOS transistor and the semiconductor substrate can be easily introduced into the sidewall.

  In the fifteenth aspect of the present invention, an oxide film layer is formed by a CVD method, nitrogen ions are implanted into the oxide film layer, and then the oxide film layer implanted with nitrogen is etched to form an N channel type. Since the first sidewall of the MOS transistor and the second sidewall of the P-channel MOS transistor are formed, nitrogen having a peak at the interface between each sidewall and the semiconductor substrate can be easily introduced into the sidewall.

  In the sixteenth aspect of the present invention, an oxide film layer is formed by a CVD method, nitrogen ions are implanted into the oxide film layer located on the N-channel MOS transistor formation region, and then the nitrogen is implanted. The oxide film layer is etched to form the first sidewall of the N-channel MOS transistor and the second sidewall of the P-channel MOS transistor. Nitrogen having a peak at the interface can be easily introduced into the sidewall.

  In the seventeenth aspect of the present invention, an oxide film layer is formed by a CVD method, nitrogen ions are implanted into the oxide film layer, and then the oxide film layer implanted with nitrogen is etched to form an N channel type. In order to form the first sidewall of the MOS transistor and the second sidewall of the P-channel MOS transistor, nitrogen having a peak at the interface between each sidewall and the semiconductor substrate can be easily added to the sidewall. Can be introduced.

  In the eighteenth aspect of the present invention, an oxide film layer is formed by a CVD method, nitrogen ions are implanted into the oxide film layer, and then the oxide film layer into which nitrogen has been implanted is etched to form an N channel type MOS. In order to form the first sidewall of the transistor and the second sidewall of the P-channel MOS transistor, nitrogen having a peak at the interface between each sidewall and the semiconductor substrate is easily introduced into the sidewall. it can.

Example 1.
A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a cross-sectional view showing a portion of an N-channel MOS transistor of a semiconductor device on which an N-channel MOS transistor suitable for miniaturization is mounted. In FIG. 1, 1 is a P-type silicon (Si) substrate. A semiconductor substrate 2 encloses an N-channel MOS transistor formation region for forming an N-channel MOS transistor on one main surface of the semiconductor substrate, and is an element for electrically insulating an adjacent element. It is a separation oxide film.

3 is a channel stopper region made of a P ⁺ -type impurity region formed under the element isolation oxide film, and 4 and 5 are a pair formed by sandwiching the channel region 6 on one main surface of the semiconductor substrate (1). The low concentration diffusion regions 4a and 5a each having an end in contact with the channel region 6 are located outside the channel region 6 and are integrated with the low concentration diffusion regions 4a and 5a. And high concentration diffusion regions 4b and 5b. A gate electrode 8 is formed on one main surface of the semiconductor substrate 1 located between the pair of source / drain regions 4 and 5 with a gate insulating film 7 interposed therebetween.

  9 is a side wall made of an oxide film formed by contacting the side surface of the gate electrode 8, the side surface of the gate insulating film 7, and one main surface of the semiconductor substrate, that is, the source / drain regions 4 and 5 and introducing nitrogen. In the embodiment 1 shown in FIG. 2, the concentration distribution of nitrogen in the cross section in the direction perpendicular to one main surface of the semiconductor substrate 1, that is, in the II cross section shown in FIG. Nitrogen is introduced into the oxide film serving as the sidewall 9 so that it has a peak at the interface with the surface and has a concentration peak at a position slightly higher than one principal surface at a position above this peak position. Is. The pair of source / drain regions 4 and 5, the gate electrode 8, and the sidewall 9 constitute an N-channel MOS transistor.

The nitrogen concentration at the peak located at the interface between the sidewall 9 and one main surface of the semiconductor substrate 1 is desirably set in the range of 10 ¹⁹ / cm ³ to 10 ²¹ / cm ^3. When 10 ¹⁹ / cm ³ to less than not make much suppressed interface state at the interface between the side walls 9 and the main surface of the semiconductor substrate 1, the hot-carrier degradation easily occurs, to 10 ²¹ / cm ³ Higher than that, the channel electron mobility deteriorates, or the transistor activation characteristics such as an increase in the resistance of the source / drain regions 4 and 5 due to a decrease in the activation rate of the impurities in the source / drain regions 4 and 5 described above. It deteriorated.

  10 is formed on one main surface of the semiconductor substrate 1, that is, on the element isolation oxide film 2, the pair of source / drain regions 4 and 5, the gate electrode 8 and the sidewalls 9, respectively. The interlayer insulating layer 11 in which contact holes 10a and 10b are formed at the respective positions of the source / drain regions 4 and 5 are electrically connected to the source / drain region 4 through the contact hole 10a of the interlayer insulating layer. The wiring layer formed on the interlayer insulating layer 10 is formed of a conductor such as aluminum or polysilicon. A wiring layer 12 is electrically connected to the source / drain region 5 through the contact hole 10b of the interlayer insulating layer and is formed on the interlayer insulating layer 10 and is formed of a conductor such as aluminum or polysilicon. It is what has been.

Next, a method for manufacturing the semiconductor device configured as described above will be described with reference to FIGS. First, as shown in FIG. 3, an element isolation oxide film 2 is formed using a normal technique so as to surround an N-channel MOS transistor formation region on one main surface of a semiconductor substrate 1, and this element isolation oxide film After forming a channel stopper region 3 made of a P ⁺ -type impurity region by performing ion implantation under 2, a gate insulating film 7 having a thickness of, for example, about 100 mm is formed on the entire main surface of the semiconductor substrate 1. An oxide film layer 107 for formation is formed.

  Next, as shown in FIG. 4, a polysilicon layer 108 for forming the gate electrode 8 is formed on the entire upper surface of the oxide film layer 107 to a thickness of about 1000 mm, for example. A resist pattern 13 made of a photoresist is formed on the polysilicon layer 108, the polysilicon layer 108 is anisotropically etched using the resist pattern 13 as a mask, a gate electrode 8 is formed, and the oxide film layer 107 is further etched. Thus, the gate insulating film 7 is formed. Thereafter, the resist pattern 13 is removed.

Then, as shown in FIG. 5, with the gate electrode 8 as a part of the mask, an N-type conductivity type impurity such as arsenic (As) is applied to one main surface of the semiconductor substrate 1, for example, 50 KeV, 5 × 10 13 / cm. Ion implantation is performed under the condition ² to form a pair of low-concentration diffusion regions 104a and 105a. Next, as shown in FIG. 6, an oxide film layer 109 having a thickness of, for example, about 1000 mm is formed on the surface of the gate electrode 8 and the pair of low-concentration diffusion regions 104a and 105a by a CVD method.

Thereafter, as shown in FIG. 7, nitrogen ions (N ⁺ ) are applied at 30 KeV and 4 × 10 ¹⁵ / cm ² so that the center of the range comes from the surface of the oxide film layer 109 to the inside of the oxide film layer 109 and approximately the center. Ions are implanted into the oxide film layer 109 under the following conditions. The concentration distribution of nitrogen in the oxide film layer 109 at this time is as shown in FIGS. 8 shows the concentration distribution in the II section shown in FIG. 7, FIG. 9 shows the concentration distribution in the II-II section shown in FIG. 7, and FIG. 10 shows the concentration distribution in the III-III section shown in FIG. The center of the range of nitrogen ions at this time, that is, the peak shown in FIG. 8 is the peak located on the surface side of the sidewall 9 shown in FIG.

  Then, as shown in FIG. 11, the oxide film layer 109 implanted with nitrogen is etched by anisotropic reactive ion etching to form a side surface of the gate electrode 8, a side surface of the gate insulating film 7, and a pair of low concentration diffusion regions. Sidewalls 9 in contact with 104a and 105a are formed.

After that, as shown in FIG. 12, an N-type conductivity impurity, for example, arsenic (As), for example, 50 KeV, 4 is applied to one main surface of the semiconductor substrate 1 using the gate electrode 8 and the sidewall 9 as a part of the mask. High concentration diffusion regions 104b and 105b are formed by ion implantation under the condition of × 10 ¹⁵ / cm ² . Then, heat treatment is performed at 850 ° C. for about 20 minutes to activate the arsenic ions forming the low concentration diffusion regions 104a and 105a and the high concentration diffusion regions 104b and 105b. A pair of source / drains comprising low-concentration diffusion regions 4a and 5a and high-concentration diffusion regions 4b and 5b which are located outside the channel region 6 and are integrated with the low-concentration diffusion regions 4a and 5a. Regions 4 and 5 will be formed.

  By the heat treatment at this time, the nitrogen in the sidewall 9 is diffused, and the nitrogen is segregated at the interface between the sidewall 9 and one main surface of the semiconductor substrate 1, and the sidewall 9 and the semiconductor substrate 1 as shown in FIG. The concentration distribution of nitrogen has a peak at the interface with one main surface. In this way, an N-channel MOS transistor having a pair of source / drain regions 4 and 5, a gate insulating film 7, a gate electrode 8, and a sidewall 9 into which nitrogen is implanted is obtained.

  Thereafter, an interlayer insulating film 10 is formed on the entire main surface of the semiconductor substrate 1, contact holes 10a and 10b are formed in the interlayer insulating film 10, and the source / drain regions 4 are electrically connected to the contact hole 10a. Is electrically connected to the source / drain region 5 through the contact hole 10b of the interlayer insulating layer 10 and the wiring layer 11 formed on the interlayer insulating layer 10, and formed on the interlayer insulating layer 10. The wiring layer 12 is formed to obtain the semiconductor device shown in FIG.

  In the semiconductor device having the N-channel MOS transistor configured as described above, nitrogen is implanted into the sidewall 9 by ion implantation, and then the sidewall 9 and one main surface of the semiconductor substrate 1 are subjected to heat treatment. Concentration distribution in which nitrogen is segregated at the interface, that is, the nitrogen concentration distribution having a peak at the interface between the sidewall 9 and one main surface of the semiconductor substrate 1, so that the N-channel MOS transistor is in a non-conductive state. Since the generation of interface states in the gate insulating film 7 in the vicinity of the interface between the semiconductor substrate 1 and the gate insulating film 7 in the vicinity of the drain region 4 (uniquely defined) is suppressed, hot carriers generated by a high electric field are suppressed. The trapping in the gate insulating film 7 is suppressed, and the hot carrier resistance is improved. That is, when hot carriers are trapped in the gate insulating film 7, transistor characteristics such as a change in threshold voltage and a decrease in drain current of an N-channel MOS transistor, that is, so-called hot carrier deterioration can be suppressed. It is.

Further, in the first embodiment, since nitrogen is implanted into the sidewall 9 by ion implantation, for example, annealing is performed in a nitrogen atmosphere (in an atmosphere containing nitrogen such as N ₂ O or NH ₃ ). It is easy to optimize the depth and concentration of nitrogen doping in the side wall 9 with respect to the method of performing the implantation, and the selectivity of the nitrogen doping region is high and no extra heat treatment is required. It has advantages.

Example 2
FIGS. 13 and 14 show Embodiment 2 of the present invention. In contrast to what is shown in Embodiment 1 above, the method of injecting nitrogen into the sidewall 9 shown in Embodiment 1 is the sidewall. 9 is different from that in which the ion implantation is performed perpendicularly to the oxide film layer 109 for forming the oxide film 9 in that the oxide film layer 109 is formed by rotational oblique ion implantation. The other points are the same as those in the first embodiment.

  That is, what was shown in this Example 2 is manufactured as follows. First, the gate electrode 8 and a pair of low concentration diffusion regions 104a and 105a are formed in the same manner as shown in FIGS. 3 to 6, and the surface of the gate electrode 8 and the pair of low concentration diffusion regions 104a and 105a are formed. An oxide film layer 109 having a thickness of, for example, about 1000 mm is formed thereon by CVD.

Thereafter, as shown in FIG. 13, the inside of the oxide film layer 109 from the surface of the oxide film layer 109, 40 KeV to approximately center projected range center comes as nitrogen ions ^{(N +), 5.6 × 10} 15 / Under the condition of cm ² , 45 ° rotation oblique ion implantation is performed on the oxide film layer 109. At this time, the nitrogen concentration distribution in the II cross section shown in FIG. 13 in the oxide film layer 109 is as shown in FIG. It should be noted that the concentration distributions of the portions corresponding to the II-II cross section and the III-III cross section shown in FIG. 7 are the same as those shown in FIG. 10 and FIG. As shown.

  As is clear from comparison between FIG. 14 and FIG. 8, the oxide film layer 109 and the semiconductor substrate 1 in the II cross section in the second embodiment are different from those in the first embodiment. The concentration of nitrogen is high in the vicinity of the interface with the main surface, that is, in the vicinity of the end portion of the gate insulating film 7.

  Thereafter, as in the first embodiment, that is, in the same manner as shown in FIGS. 11 and 12, the oxide film layer 109 implanted with nitrogen is etched by anisotropic reactive ion etching to form the gate electrode 8. Side wall 9 in contact with the side surface of gate insulating film 7 and the pair of low-concentration diffusion regions 104a and 105a is formed, and N-type conductivity type impurity ions are formed using gate electrode 8 and side wall 9 as part of the mask. Implanted to form high-concentration diffusion regions 104b and 105b, heat treatment is applied to form low-concentration diffusion regions 4a and 5a whose ends are in contact with the channel region 6, and the low-concentration diffusion regions located outside the channel region 6 A pair of source / drain regions 4 and 5 consisting of high concentration diffusion regions 4b and 5b integrally formed with regions 4a and 5a are formed, and side walls are formed. A pair of source / drain regions 4 and 5 and a gate insulating film are formed by diffusing nitrogen in the substrate 9 so that the nitrogen concentration distribution has a peak at the interface between the sidewall 9 and one main surface of the semiconductor substrate 1. 7, an N-channel MOS transistor having a gate electrode 8 and a side wall 9 implanted with nitrogen is obtained, and thereafter an interlayer insulating film 10 and wiring layers 11 and 12 are formed to obtain a semiconductor device. is there.

  Even in the second embodiment configured as described above, the same effect as that of the first embodiment is obtained, and in order to obtain the sidewall 9 into which nitrogen is implanted, the oxide film layer 109 is subjected to rotational oblique ion implantation. Therefore, the concentration of nitrogen injected into the oxide film layer 109 close to the end of the gate insulating film 7 can also be increased, and then the interface between the sidewall 9 and one main surface of the semiconductor substrate 1 is performed by heat treatment. Since the concentration peak formed by the segregation of nitrogen is higher than that shown in Example 1, further hot carrier resistance is improved.

Example 3
FIGS. 15 to 27 show a third embodiment of the present invention. Compared with the first embodiment, the method of injecting nitrogen into the sidewall 9 is different from the first embodiment. As a result, the concentration distribution of nitrogen in the sidewall 9 is different, and the other points are the same as in the first embodiment.

  In FIG. 15, reference numeral 9 denotes a side surface of the gate electrode 8, a side surface of the gate insulating film 7, and one main surface of the semiconductor substrate, that is, an oxide film into which nitrogen is introduced, formed in contact with the source / drain regions 4 and 5. In the side wall shown in the third embodiment, the cross section in the direction perpendicular to one main surface of the semiconductor substrate 1, that is, the nitrogen concentration distribution in the II cross section shown in FIG. In a direction parallel to the main surface of the semiconductor substrate 1 so as to have a peak at the interface with the main surface of the semiconductor substrate 1 and to have a concentration peak on the surface of the main surface above the position of the peak. As shown in FIG. 17, the nitrogen concentration distribution in the cross section of FIG. 4, i.e., the IV-IV cross section has a peak at the interface with the side surface of the gate electrode 8, and the concentration further increases on the surface, that is, the interface with the interlayer insulating film 9. peak Nitrogen is introduced into the oxide film to be the sidewall 9 so as to have the following.

The nitrogen concentration at the peak located at the interface between the sidewall 9 and one main surface of the semiconductor substrate 1 is set in the range of 10 ¹⁹ / cm ³ to 10 ²¹ / cm ³ as in the first embodiment. It is desirable to do. In addition, the same reference numerals as those in FIG. 1 shown as the first embodiment denote the same or corresponding parts.

  Next, a method for manufacturing the semiconductor device configured as described above will be described with reference to FIGS. First, the gate electrode 8 and the pair of low-concentration diffusion regions 104a and 105a are formed on the basis of the one shown in FIGS. 3 to 5 as in the first embodiment. Then, as shown in FIG. 18, an oxide film layer 109 having a thickness of, for example, about 800 mm is formed on the surface of the gate electrode 8 and the pair of low-concentration diffusion regions 104a and 105a by the CVD method. For example, a polysilicon layer 14 having a thickness of about 1000 mm is formed on the entire surface by CVD.

Thereafter, as shown in FIG. 19, nitrogen ions (N ⁺ ) are applied at 30 KeV and 4 × 10 ¹⁵ / cm ² so that the center of the range comes from the surface of the polysilicon layer 14 to the inside of the polysilicon layer 14 and approximately the center. Ions are implanted into the polysilicon layer 14 under the following conditions. The nitrogen concentration distribution in the polysilicon layer 14 at this time is as shown in FIGS. 20 shows the concentration distribution in the VV section shown in FIG. 19, and FIG. 21 shows the concentration distribution in the II-II section and the III-III section shown in FIG.

  Then, heat treatment is performed at 850 ° C. for about 20 minutes to diffuse nitrogen ions implanted into the polysilicon layer 14 into the oxide film layer 109. After that, as shown in FIG. 22, the polysilicon layer 14 is removed by etching the entire surface. The nitrogen concentration distribution in the oxide film layer 109 at this time is as shown in FIGS. 23 shows the concentration distribution in the II section shown in FIG. 22, FIG. 24 shows the concentration distribution in the II-II section shown in FIG. 22, and FIG. 25 shows the concentration distribution in the III-III section shown in FIG.

  That is, nitrogen is segregated at the interface between the oxide film layer 109 and one main surface of the semiconductor substrate 1, the interface between the oxide film layer 109 and the gate electrode 8, and the interface between the oxide film layer 109 and the polysilicon layer 14. A peak of nitrogen concentration occurs at each interface. As a result, when the sidewall 9 is formed, a peak appears at the interface between the sidewall 9 and one main surface of the semiconductor substrate 1 as apparent from the nitrogen concentration distribution in the II cross section of FIG. 22 shown in FIG. And has a concentration peak on the surface of one principal surface at a position above the peak position.

  Next, as shown in FIG. 26, the oxide film layer 109 implanted with nitrogen is etched by anisotropic reactive ion etching to form a pair of low-concentration diffusions on the side surface of the gate electrode 8 and the side surface of the gate insulating film 7. Sidewalls 9 in contact with the regions 104a and 105a are formed.

Thereafter, as shown in FIG. 27, an N-type conductivity type impurity such as arsenic (As), for example, 50 KeV, 4 High concentration diffusion regions 104b and 105b are formed by ion implantation under the condition of × 10 ¹⁵ / cm ² . Then, heat treatment is performed at 850 ° C. for about 20 minutes to activate the arsenic ions forming the low concentration diffusion regions 104a and 105a and the high concentration diffusion regions 104b and 105b. A pair of source / drains comprising low-concentration diffusion regions 4a and 5a and high-concentration diffusion regions 4b and 5b which are located outside the channel region 6 and are integrated with the low-concentration diffusion regions 4a and 5a. Regions 4 and 5 will be formed.

  In this way, an N-channel MOS transistor having a pair of source / drain regions 4 and 5, a gate insulating film 7, a gate electrode 8, and a sidewall 9 into which nitrogen is implanted is obtained.

  Thereafter, an interlayer insulating film 10 is formed on the entire main surface of the semiconductor substrate 1, contact holes 10a and 10b are formed in the interlayer insulating film 10, and the source / drain regions 4 are electrically connected to the contact hole 10a. And is electrically connected to the source / drain region 5 through the contact hole 10b of the interlayer insulating layer 10 and the wiring layer 11 formed on the interlayer insulating layer 10, and formed on the interlayer insulating layer 10. The wiring layer 12 is formed to obtain the semiconductor device shown in FIG. Even in the third embodiment configured as described above, the same effects as in the first embodiment are achieved.

Example 4
28 and 29 show Embodiment 4 of the present invention. In contrast to what is shown in Embodiment 3 above, the method of injecting nitrogen into the side wall 9 shown in Embodiment 3 is polysilicon. In contrast to what is introduced into the oxide film layer 109 for forming the sidewalls 9 by heat treatment after ion implantation is performed perpendicularly to the layer 14, the structure shown in this embodiment 4 is rotated obliquely to the polysilicon layer 14. The only difference is that it is introduced into the oxide film layer 109 by heat treatment after ion implantation, and the other points are the same as in the third embodiment.

  That is, what was shown in this Example 4 is manufactured as follows. First, the gate electrode 8 and a pair of low-concentration diffusion regions 104a and 105a are formed in the same manner as shown in FIGS. 3 to 5, and the surface of the gate electrode 8 and a pair of low-concentration regions are formed as shown in FIG. An oxide film layer 109 having a thickness of, for example, about 200 mm is formed on the concentration diffusion regions 104a and 105a by the CVD method, and a polysilicon layer 14 having a thickness of, for example, about 1000 mm is formed on the entire surface of the oxide film layer 109 by the CVD method. .

After that, as shown in FIG. 28, the interior of the polysilicon layer 14 from over the surface of the polysilicon layer 14, the nitrogen ions (N ⁺⁾ to come projected range centered substantially at the center 40 KeV, 5.6 × 10 ¹⁵ / A 45 ° rotation oblique ion implantation is performed on the polysilicon layer 14 under the condition of cm ² . At this time, the concentration distribution of nitrogen in the section taken along the line II in FIG. 28 in the polysilicon layer 109b is as shown in FIG. It should be noted that the concentration distributions of the portions corresponding to the II-II section and the III-III section shown in FIG. 19 are the same as those shown in Example 3, respectively, so as to show the same concentration distribution as the concentration portion shown in FIG. It has become.

  As is clear from comparison between FIG. 29 and FIG. 20, the polysilicon layer 14 and the oxide film layer 109 in the II cross section of the fourth embodiment is different from that of the third embodiment. The concentration of nitrogen in the vicinity of the interface is high.

  Thereafter, in the same manner as in the third embodiment, that is, in the same manner as shown in FIG. In the same manner as shown in FIGS. 26 and 27, the oxide film layer 109 implanted with nitrogen is etched by anisotropic reactive ion etching, and the side surface of the gate electrode 8 and the side surface of the gate insulating film 7 are formed. Side walls 9 in contact with the pair of low-concentration diffusion regions 104a and 105a are formed, and N-type conductivity type impurity ions are implanted using the gate electrode 8 and the side walls 9 as a part of the mask to form the high-concentration diffusion regions 104b and 105b. The low concentration diffusion regions 4a and 5a whose ends are in contact with the channel region 6 by applying heat treatment and the low concentration diffusion located outside the channel region 6 A pair of source / drain regions 4 and 5 consisting of high-concentration diffusion regions 4b and 5b integrally formed with regions 4a and 5a are formed, and the pair of source / drain regions 4 and 5, gate insulating film 7, gate An N-channel MOS transistor having an electrode 8 and a side wall 9 implanted with nitrogen is obtained, and thereafter an interlayer insulating film 10 and wiring layers 11 and 12 are formed to obtain a semiconductor device.

  Even in the second embodiment configured as described above, the same effect as that of the third embodiment can be obtained. In addition, in order to obtain the sidewall 9 in which nitrogen is implanted, the polysilicon layer 14 is subjected to rotational oblique ion implantation. Therefore, the concentration of nitrogen injected into the oxide film layer 109 near the end of the gate insulating film 7 is also increased, and the peak of the nitrogen concentration at the interface between the sidewall 9 and one main surface of the semiconductor substrate 1 is increased. Since this is higher than that shown in Example 3, further hot carrier resistance is improved.

Example 5 FIG.
30 to 39 show the fifth embodiment of the present invention. The structure of the sidewall 9 is different from that shown in the first embodiment, and the other points are different from those of the first embodiment. The same. In FIG. 30, reference numeral 9 denotes an oxide film 9a having a substantially L-shaped longitudinal section having a vertical portion in contact with the side surface of the gate electrode 8 and the side surface of the gate insulating film 7 and a bottom portion in contact with one main surface of the semiconductor substrate 1. As shown in the fourth embodiment, the oxide film 9a is framed, that is, formed in contact with the vertical and bottom portions of the oxide film 9a and has a side wall having polysilicon 9b into which nitrogen is introduced. As shown in FIG. 31, the cross section in the direction perpendicular to one main surface of the semiconductor substrate 1, that is, the cross section taken along the line II in FIG. 31, shows a peak at the interface between the polysilicon 9b and the oxide film 9a. So as to have a further concentration peak near the surface of the polysilicon 9b at a position above the peak position, and to have a peak at the interface between the oxide film 9a and one main surface of the semiconductor substrate 1. Nitro There are those that have been introduced to the side wall 9.

Note that the nitrogen concentration of the peak located at the interface between the polysilicon 9b and the oxide film 9a and the peak located at the interface between the oxide film 9a and one main surface of the semiconductor substrate 1 are 10 ¹⁹ as in the first embodiment. It is desirable to set in the range of from / cm ³ to -10 ²¹ / cm ³ . In addition, the same reference numerals as those in FIG. 1 shown as the first embodiment denote the same or corresponding parts.

  Next, a method for manufacturing the semiconductor device configured as described above will be described with reference to FIGS. First, the gate electrode 8 and the pair of low-concentration diffusion regions 104a and 105a are formed on the basis of the one shown in FIGS. 3 to 5 as in the first embodiment. Thereafter, as shown in FIG. 32, an oxide film layer 109a having a thickness of, for example, about 200 mm is formed by CVD on the surface of the gate electrode 8 and the pair of low-concentration diffusion regions 104a and 105a. A polysilicon layer 109b having a thickness of, for example, about 1000 mm is formed on the entire surface by CVD.

After that, as shown in FIG. 33, nitrogen ions (N ⁺ ) are applied at 30 KeV and 4 × 10 ¹⁵ / cm ² so that the center of the range comes from the surface of the polysilicon layer 109b to the inside of the polysilicon layer 109b and approximately the center. Ions are implanted into the polysilicon layer 109b under the following conditions. The nitrogen concentration distribution in the polysilicon layer 109b and the oxide film layer 109a at this time is as shown in FIGS. 34 shows the concentration distribution in the II section shown in FIG. 33, FIG. 35 shows the concentration distribution in the II-II section shown in FIG. 33, and FIG. 36 shows the concentration distribution in the III-III section shown in FIG. The center of the range of nitrogen ions at this time, that is, the peak shown in FIG. 34 is the peak located on the surface side of the polysilicon 9b shown in FIG. 31 as a result.

  Thereafter, as shown in FIG. 37, the polysilicon layer 109b implanted with nitrogen is etched by anisotropic reactive ion etching to form a polysilicon 9b framed on the oxide film layer 109a. Further, as shown in FIG. 38, the oxide film layer 109a implanted with nitrogen is etched by anisotropic reactive ion etching, and a pair of a vertical portion in contact with the side surface of the gate electrode 8 and the side surface of the gate insulating film 7 An oxide film 9a having a bottom portion in contact with the low concentration diffusion regions 104a and 105a is formed, and a sidewall 9 having an oxide film 9a and polysilicon 9b is formed.

After that, as shown in FIG. 39, an N-type conductivity type impurity, for example, arsenic (As), for example, 50 KeV, 4 is applied to one main surface of the semiconductor substrate 1 using the gate electrode 8 and the sidewall 9 as a part of the mask. High concentration diffusion regions 104b and 105b are formed by ion implantation under the condition of × 10 ¹⁵ / cm ² . Then, heat treatment is performed at 850 ° C. for about 20 minutes to activate the arsenic ions forming the low concentration diffusion regions 104a and 105a and the high concentration diffusion regions 104b and 105b. A pair of source / drains comprising low-concentration diffusion regions 4a and 5a and high-concentration diffusion regions 4b and 5b which are located outside the channel region 6 and are integrated with the low-concentration diffusion regions 4a and 5a. Regions 4 and 5 will be formed.

  By the heat treatment at this time, the nitrogen in the sidewall 9 is diffused, and the nitrogen is segregated at the interface between the polysilicon 9b and the oxide film 9a and the interface between the oxide film 9a and one main surface of the semiconductor substrate 1, as shown in FIG. As shown, the nitrogen concentration distribution has a peak at the interface between the polysilicon 9b and the oxide film 9a and the interface between the oxide film 9a and one main surface of the semiconductor substrate 1. In this way, an N-channel MOS transistor having a pair of source / drain regions 4 and 5, a gate insulating film 7, a gate electrode 8, and a sidewall 9 into which nitrogen is implanted is obtained.

  Thereafter, an interlayer insulating film 10 is formed on the entire main surface of the semiconductor substrate 1, contact holes 10a and 10b are formed in the interlayer insulating film 10, and the source / drain regions 4 are electrically connected to the contact hole 10a. And is electrically connected to the source / drain region 5 through the contact hole 10b of the interlayer insulating layer 10 and the wiring layer 11 formed on the interlayer insulating layer 10, and formed on the interlayer insulating layer 10. The wiring layer 12 is formed to obtain the semiconductor device shown in FIG.

  Even in the fifth embodiment configured as described above, the same effects as those of the first embodiment can be obtained, and the side wall 9 is composed of the oxide film 9a and the polysilicon 9b. When the contact holes 10a and 10b of the film 10 are formed, even if a mask shift occurs, the polysilicon 9b is not etched, and the wiring layers 11 and 12 and the gate electrode 8 are reliably electrically connected by the sidewall 9. It has the advantage that it can be electrically insulated.

Example 6
40 and 41 show Embodiment 6 of the present invention. In contrast to the embodiment 5 described above, the method of injecting nitrogen into the side wall 9 shown in Embodiment 5 is polysilicon. In contrast to the case where the ion implantation is performed perpendicularly to the layer 109b, the one shown in this embodiment 6 is different only in that the polysilicon layer 14 is subjected to the rotational oblique ion implantation. Same as Example 5.

  That is, what was shown in this Example 6 is manufactured as follows. First, the gate electrode 8 and a pair of low-concentration diffusion regions 104a and 105a are formed in the same manner as that shown in FIGS. 3 to 5, and as shown in FIG. An oxide film layer 109a having a thickness of about 200 mm is formed on the concentration diffusion regions 104a and 105a by the CVD method, and a polysilicon layer 109b having a thickness of about 1000 mm is formed on the entire surface of the oxide film layer 109a by the CVD method. .

Thereafter, as shown in FIG. 40, the interior of the polysilicon layer 109b from the surface of the polysilicon layer 109b, nitrogen ions (N ⁺⁾ to come projected range centered substantially centrally 40KeV, 5.6 × 10 ¹⁵ / Under the condition of cm ² , 45 ° rotation oblique ion implantation is performed on the polysilicon layer 109b. At this time, the nitrogen concentration distribution in the II cross section shown in FIG. 40 in the polysilicon layer 109b is as shown in FIG. Note that the nitrogen concentration distribution in the II-II section and the III-III section shown in FIG. 40 shows the same concentration distribution as the concentration portion shown in FIG. 35 and FIG. It has become.

  As is clear from comparison between FIG. 41 and FIG. 34, in the sixth embodiment, the polysilicon layer 109b and the oxide film layer 109a in the II section are different from the fifth embodiment. The concentration of nitrogen in the vicinity of the interface is high.

  Thereafter, in the same manner as in the fifth embodiment, that is, as shown in FIGS. 37 to 39, the polysilicon layer 109b implanted with nitrogen is etched by anisotropic reactive ion etching to form the oxide film layer 109a. The polysilicon film 9b is formed in a frame, and the oxide film layer 109a implanted with nitrogen is etched by anisotropic reactive ion etching to form the oxide film 9a, and the gate electrode 8 and the sidewall 9 are masked. As a part of this, N type conductivity type impurity ions are implanted to form high concentration diffusion regions 104b and 105b, and heat treatment is applied to form low concentration diffusion regions 4a and 5a whose ends are in contact with the channel region 6, and the channel region. 6 is a pair of saws which are located on the outside of the base plate 6 and are composed of the high concentration diffusion regions 4b and 5b integrally formed with the low concentration diffusion regions 4a and 5a / Drain regions 4 and 5 are formed, and an N-channel MOS transistor having a pair of source / drain regions 4 and 5, a gate insulating film 7, a gate electrode 8, and a sidewall 9 into which nitrogen is implanted is obtained. The semiconductor device is obtained by forming the interlayer insulating film 10 and the wiring layers 11 and 12.

  Even in the sixth embodiment configured as described above, the same effect as in the fifth embodiment is obtained, and in addition, in order to obtain the sidewall 9 implanted with nitrogen, the polysilicon layer 109b is subjected to rotational oblique ion implantation. As a result, the concentration of nitrogen injected into the oxide film 9a near the edge of the gate insulating film 7 increases, and the peak of the nitrogen concentration at the interface between the sidewall 9 and one main surface of the semiconductor substrate 1 also increases. Since it becomes high compared with what was shown in Example 5, the further hot carrier tolerance improves.

Example 7
FIGS. 42 to 49 show Embodiment 7 of the present invention. In contrast to that shown in Embodiment 1 above, Embodiment 1 introduces nitrogen into the side wall 9. In the seventh embodiment, nitrogen is introduced into the pair of source / drain regions 4 and 5, the gate insulating film 7 and the gate electrode 8 in addition to the sidewall 9. Is the same.

  In FIG. 42, reference numerals 4 and 5 denote a pair of source / drain regions which are formed on one main surface of the semiconductor substrate 1 with the channel region 6 interposed therebetween and into which nitrogen is introduced in addition to the first conductivity type (N-type) impurities. , Each of the low concentration diffusion regions 4a and 5a whose end portions are in contact with the channel region 6, and the high concentration diffusion region located outside the channel region 6 and integrally formed with the low concentration diffusion regions 4a and 5a 44, the nitrogen concentration distribution in the cross section perpendicular to one main surface of the semiconductor substrate 1, that is, the II-II cross section shown in FIG. 44 is shown in FIG. As shown, it has a peak in the vicinity of one main surface of the semiconductor substrate 1 and gradually decreases.

  8 is a gate electrode formed with nitrogen introduced on one main surface of the semiconductor substrate 1 located between the pair of source / drain regions 4 and 5 and introduced with nitrogen. In the embodiment 7 shown in FIG. 45, the nitrogen concentration distribution in the cross section in the direction perpendicular to one main surface of the semiconductor substrate 1, that is, in the III-III cross section shown in FIG. And has a peak in the vicinity of the surface.

  9 is a side wall made of an oxide film formed by contacting the side surface of the gate electrode 8, the side surface of the gate insulating film 7, and one main surface of the semiconductor substrate, that is, the source / drain regions 4 and 5 and introducing nitrogen. In the embodiment 7 shown in FIG. 43, the main surface of the semiconductor substrate 1 has a nitrogen concentration distribution in a cross section perpendicular to the main surface of the semiconductor substrate 1, that is, a cross section taken along the line II in FIG. Nitrogen is introduced into the oxide film serving as the sidewall 9 so that it has a peak at the interface and a concentration peak at a position above the peak position and below one main surface. is there.

  Next, a manufacturing method of the semiconductor device configured as described above will be described with reference to FIG. First, a gate electrode 8 and a pair of low-concentration diffusion regions 104a and 105a are formed on the surface of the gate electrode 8 and a pair based on the one shown in FIGS. An oxide film layer 109 having a thickness of about 1000 mm is formed on the low concentration diffusion regions 104a and 105a by a CVD method.

Thereafter, as shown in FIG. 46, nitrogen ions (N ⁺⁾ are arranged so that the center of the range comes from the surface of the oxide film layer 109 to the inside of the oxide film layer 109, the gate electrode 8, and the pair of low concentration diffusion regions 104a and 105a. ) Is implanted into the oxide film layer 109, the gate electrode 8, and the pair of low-concentration diffusion regions 104a and 105a under the conditions of 100 KeV and 4 × 10 ¹⁵ / cm ² . The concentration distribution of nitrogen in the oxide film layer 109, the gate electrode 8, and the pair of low concentration diffusion regions 104a and 105a at this time is as shown in FIGS. 47 shows the concentration distribution in the II section shown in FIG. 46, FIG. 48 shows the concentration distribution in the II-II section shown in FIG. 46, and FIG. 49 shows the concentration distribution in the III-III section shown in FIG. The center of the range of nitrogen ions at this time, that is, the peak shown in FIG. 47 is the peak located on the surface side of the sidewall 9 shown in FIG. 43 and the peak shown in FIG. 49 is shown in FIG. The peak is located on the surface side of the gate electrode 8.

  It should be noted that the nitrogen implantation conditions are such that the projected range Rp of nitrogen is a position above 5 × ΔRp from the interface between the gate electrode 8 and the gate insulating film 7, and the standard deviation is ΔRp. The source / drain regions 4 and 5 are set to be positioned above the projected range of N-type impurities (arsenic in this example) for forming the low concentration diffusion regions 104a and 105a. . By setting in this way, the gate insulating film 7 is not damaged by the nitrogen implantation, and the defects generated by the nitrogen implantation are the low concentration diffusion regions 104a and 105a of the source / drain regions 4 and 5, the semiconductor substrate 1, and the like. Therefore, junction leakage current is less likely to occur during the operation of the MOS transistor.

Thereafter, as in the first embodiment, the oxide film layer 109 implanted with nitrogen is etched by anisotropic reactive ion etching to form the sidewall 9 based on FIGS. 11 and 12, and the gate electrode 8 and With the sidewall 9 as a part of the mask, an N-type conductivity type impurity such as arsenic (As) is ion-implanted into one main surface of the semiconductor substrate 1 under conditions of, for example, 50 KeV and 4 × 10 ¹⁵ / cm ^2. High concentration diffusion regions 104b and 105b are formed. Then, heat treatment is performed at 850 ° C. for about 20 minutes to activate the arsenic ions forming the low concentration diffusion regions 104a and 105a and the high concentration diffusion regions 104b and 105b. A pair of source / drains comprising low-concentration diffusion regions 4a and 5a and high-concentration diffusion regions 4b and 5b which are located outside the channel region 6 and are integrated with the low-concentration diffusion regions 4a and 5a. Regions 4 and 5 will be formed.

  By the heat treatment at this time, the nitrogen in the sidewall 9 is diffused, and the nitrogen is segregated at the interface between the sidewall 9 and one main surface of the semiconductor substrate 1, and as shown in FIG. As shown in FIG. 45, the nitrogen concentration distribution has a peak at the interface with one main surface, nitrogen in the gate electrode 8 diffuses into the gate insulating film 7, and nitrogen segregates in the gate insulating film 7. Thus, the concentration distribution of nitrogen having a peak in the gate insulating film 7 is obtained. Thus, a pair of source / drain regions 4 and 5 into which nitrogen has been introduced, a gate insulating film 7 into which nitrogen has been introduced, a gate electrode 8 into which nitrogen has been introduced, and a sidewall 9 into which nitrogen has been introduced are provided. The obtained N channel type MOS transistor is obtained.

  Thereafter, an interlayer insulating film 10 is formed on the entire main surface of the semiconductor substrate 1, contact holes 10a and 10b are formed in the interlayer insulating film 10, and the source / drain regions 4 are electrically connected to the contact hole 10a. And is electrically connected to the source / drain region 5 through the contact hole 10b of the interlayer insulating layer 10 and the wiring layer 11 formed on the interlayer insulating layer 10, and formed on the interlayer insulating layer 10. The wiring layer 12 is formed, and the semiconductor device shown in FIG. 42 is obtained.

  Even in the seventh embodiment configured as described above, the same effect as that of the first embodiment is obtained, and nitrogen is also precipitated in the gate insulating film 7, so that the interface in the gate insulating film 7 is The generation of levels is further suppressed, hot carrier resistance is further improved, and the following advantages are also obtained. That is, since nitrogen is also introduced into the pair of source / drain regions 4 and 5, diffusion of N-type impurities (arsenic in this example) is suppressed, and lateral diffusion of N-type impurities into the channel region 6 is prevented. As a result, an effective gate length can be increased, and an N-channel MOS transistor resistant to punch-through due to the short channel effect can be obtained. This is because the diffusion mechanism of nitrogen is the same as that of the N-type impurity, and the diffusion coefficient is larger than that of the N-type impurity. This is because the diffusion of N-type impurities is suppressed as a result of nitrogen being first occupied in the holes.

Example 8 FIG.
50 and 51 show an eighth embodiment of the present invention. In contrast to the seventh embodiment, the method of injecting nitrogen into the side wall 9 shown in the seventh embodiment is an oxide film. In contrast to the case where ion implantation is performed perpendicularly to the layer 109, the embodiment 8 is different from that in which the oxide film layer 109 is subjected to rotational oblique ion implantation in other respects. Same as Example 7.

  That is, the one shown in Example 8 is manufactured as follows. First, in the same manner as shown in FIGS. 3 to 6, a gate electrode 8 and a pair of low concentration diffusion regions 104a and 105a are formed, and on the surface of the gate electrode 8 and a pair of low concentration diffusion regions 104a and 105a. An oxide film layer 109 having a thickness of about 1000 mm, for example, is formed thereon by CVD.

Thereafter, as shown in FIG. 50, the same implantation conditions as in Example 7 are considered from the surface of the oxide film layer 109 into the oxide film layer 109, the gate electrode 8, and the pair of low concentration diffusion regions 104a and 105a. Then, 45 ° rotation oblique ion implantation is performed on the oxide film layer 109, the gate electrode 8, and the pair of low-concentration diffusion regions 104a and 105a with nitrogen ions (N ⁺ ) at 140 KeV and 5.6 × 10 ¹⁵ / cm ^2. . At this time, the nitrogen concentration distribution in the II section shown in FIG. 50 in the oxide film layer 109 is as shown in FIG. Note that the nitrogen concentration distribution in the II-II section and the III-III section shown in FIG. 50 shows the same concentration distribution as the concentration portion shown in FIG. 44 and FIG. It has become.

  As is clear from a comparison between FIG. 51 and FIG. 43, in the eighth embodiment, the oxide film layer 109 and the semiconductor substrate 1 in the II section are different from the seventh embodiment. The nitrogen concentration in the vicinity of the interface with one principal surface is high.

  Thereafter, as in the seventh embodiment, the oxide film layer 109 implanted with nitrogen is etched by anisotropic reactive ion etching to form the sidewall 9, and the gate electrode 8 and the sidewall 9 are part of the mask. N type conductivity type impurity ions are implanted to form high concentration diffusion regions 104b and 105b, and heat treatment is applied to the low concentration diffusion regions 4a and 5a whose ends are in contact with the channel region 6, and the channel region 6 A pair of source / drain regions 4 and 5 consisting of high concentration diffusion regions 4b and 5b integrally formed with the low concentration diffusion regions 4a and 5a are formed. And 5, an N-channel MOS transistor having a gate insulating film 7, a gate electrode 8, and a side wall 9 implanted with nitrogen is obtained, and then interlayer insulation is obtained. 10 and forming a wiring layer 11 and 12 is that obtained the semiconductor device.

  Even in the eighth embodiment configured as described above, the same effect as that of the seventh embodiment is obtained, and in addition, in order to obtain the sidewall 9 into which nitrogen is implanted, the oxide film layer 109 is subjected to rotational oblique ion implantation. As a result, the concentration of nitrogen injected into the sidewall 9 near the end of the gate insulating film 7 increases, and the peak of the concentration of nitrogen at the interface between the sidewall 9 and one main surface of the semiconductor substrate 1 also increases. Since it becomes high compared with what was shown in Example 7, the further hot carrier tolerance improves.

Example 9
FIGS. 52 to 60 show Embodiment 9 of the present invention. FIG. 52 shows an N-channel MOS transistor of a semiconductor device on which an N-channel MOS transistor and a P-channel MOS transistor suitable for miniaturization are mounted. FIG. 1 is a cross-sectional view showing a portion of a P-channel MOS transistor. In FIG. 1, reference numeral 1 denotes a semiconductor substrate which is a P-type silicon (Si) substrate, and N for forming an N-channel MOS transistor on one main surface thereof. P well region 1a formed to include a channel type MOS transistor formation region and N well region 1b formed to include a P channel type MOS transistor formation region for forming a P channel type MOS transistor. It is what you are doing.

  An element isolation oxide film 2 surrounds the N-channel MOS transistor formation region and the P-channel MOS transistor formation region on one main surface of the semiconductor substrate, and is electrically insulated from adjacent elements. is there.

  Reference numerals 4 and 5 denote a pair of first source / drain regions formed on one main surface of the semiconductor substrate 1 with the first channel region 6 sandwiched therebetween, each of which has an end in contact with the first channel region 6. Consisting of the low concentration diffusion regions 4a and 5a and the high concentration diffusion regions 4b and 5b that are located outside the first channel region 6 and are integrally formed with the low concentration diffusion regions 4a and 5a. It is. Reference numeral 8 denotes a gate electrode formed on one main surface of the semiconductor substrate 1 located between the pair of first source / drain regions 4 and 5 via a first gate insulating film 7.

  9 is formed in contact with the side surface of the first gate electrode 8, the side surface of the first gate insulating film 7, and one main surface of the semiconductor substrate 1, that is, the first source / drain regions 4 and 5, and nitrogen is introduced. In the first sidewall made of the oxidized film shown in the ninth embodiment, the cross section in the direction perpendicular to one main surface of the semiconductor substrate 1 is the same as that shown in the first embodiment. That is, the concentration distribution of nitrogen in the II section shown in the figure has a peak at the interface with one main surface of the semiconductor substrate 1 as shown in FIG. 2, and is slightly lower than one main surface at a position above this peak position. Nitrogen is introduced into the oxide film serving as the first sidewall 9 so as to further have a concentration peak at the position. The pair of first source / drain regions 4 and 5, the first gate electrode 8, and the first sidewall 9 constitute an N-channel MOS transistor.

Note that the nitrogen concentration at the peak located at the interface between the first sidewall 9 and one main surface of the semiconductor substrate 1 is set in the range of 10 ¹⁹ / cm ³ to 10 ²¹ / cm ^3. Desirably, if it is lower than 10 ¹⁹ / cm ³ , the interface state at the interface between the first sidewall 9 and one main surface of the semiconductor substrate 1 cannot be suppressed so much, and hot carrier deterioration is likely to occur. If it is higher than −10 ²¹ / cm ³ , the mobility of channel electrons deteriorates, or the activation rate of the impurities in the source / drain regions 4 and 5 decreases and the resistance of the source / drain regions 4 and 5 increases. The transistor characteristics such as the deterioration were deteriorated.

  Reference numerals 24 and 25 denote a pair of second source / drain regions formed on one main surface of the semiconductor substrate 1 with the second channel region 26 interposed therebetween. Reference numeral 28 denotes a pair of the second source / drain regions 24 and 25. 2 is a gate electrode formed on one main surface of the semiconductor substrate 1 located between them via a second gate insulating film 27. 29 denotes an oxide film formed in contact with the side surface of the second gate electrode 28, the side surface of the second gate insulating film 27, and one main surface of the semiconductor substrate 1, that is, the second source / drain regions 24 and 25. This is the second sidewall. The pair of second source / drain regions 24 and 25, the second gate electrode 28, and the second sidewall 29 constitute a P-channel MOS transistor.

  Reference numeral 10 denotes one main surface of the semiconductor substrate 1, that is, the element isolation oxide film 2, the pair of first source / drain regions 4 and 5, the first gate electrode 8, and the first sidewall 9. The pair of second source / drain regions 24 and 25, the second gate electrode 28 and the second sidewall 29 are formed on the pair of first source / drain regions 4 and 5 respectively. Contact holes 10a and 10b are formed at the respective positions, and the interlayer insulating layers are formed with contact holes 10c and 10d at the positions of the pair of second source / drain regions 24 and 25, respectively.

  A wiring layer 11 is electrically connected to the first source / drain region 4 through the contact hole 10a of the interlayer insulating layer, and is formed on the interlayer insulating layer 10, and is made of a conductive material such as aluminum or polysilicon. It is formed by the body. A wiring layer 12 is electrically connected to the first source / drain region 5 through the contact hole 10b of the interlayer insulating layer, and is formed on the interlayer insulating layer 10, and is made of a conductive material such as aluminum or polysilicon. It is formed by the body. A wiring layer 15 is electrically connected to the second source / drain region 24 through the contact hole 10c of the interlayer insulating layer, and is formed on the interlayer insulating layer 10, and is made of a conductive material such as aluminum or polysilicon. It is formed by the body. A wiring layer 16 is electrically connected to the second source / drain region 25 through the contact hole 10d of the interlayer insulating layer, and is formed on the interlayer insulating layer 10, and is made of conductive material such as aluminum or polysilicon. It is formed by the body.

  Next, a method for manufacturing the semiconductor device configured as described above will be described with reference to FIGS. First, as shown in FIG. 53, a P well region 1a includes an N channel MOS transistor formation region on one main surface of a semiconductor substrate 1, and an N well region 1b includes a P channel MOS transistor formation region. And an element isolation oxide film 2 is formed using a normal technique so as to surround each of the N-channel MOS transistor formation region and the P-channel MOS transistor formation region, and then the entire main surface of the semiconductor substrate 1 is formed. An oxide film layer 107 for forming the first gate insulating film 7 and the second gate insulating film 27 having a thickness of, for example, about 100 mm is formed thereon.

  Next, as shown in FIG. 54, a polysilicon layer 108 for forming the first gate electrode 8 and the second gate 28 is formed on the entire upper surface of the oxide film layer 107 to a thickness of about 1000 mm, for example. To do. A resist pattern 13 made of a photoresist is formed on the polysilicon layer 108, and the polysilicon layer 108 is anisotropically etched using the resist pattern 13 as a mask to form first and second gate electrodes 8 and 28. Then, the oxide film layer 107 is further etched to form the first and second gate insulating films 7 and 27. Thereafter, the resist pattern 13 is removed.

Then, as shown in FIG. 55, the P-channel MOS transistor formation region is covered with a resist 17, the N-channel MOS transistor formation region is exposed, and the semiconductor substrate 1 An N-type conductivity type impurity, for example, arsenic (As) is ion-implanted into one main surface of the P well region 1a under the conditions of, for example, 50 KeV and 5 × 10 13 / cm ^2. Diffusion regions 104a and 105a are formed.

  Next, as shown in FIG. 56, the resist 17 formed on the P-channel MOS transistor formation region is removed, and the surface of the first gate electrode 8, the pair of low-concentration diffusion regions 104a and 105a, and the first On the exposed surface of one main surface of the semiconductor substrate 1 in the gate electrode 28 and the P channel type MOS transistor formation region, an oxide film layer 109 having a thickness of, for example, about 1000 mm is formed by CVD.

Thereafter, as shown in FIG. 57, the oxide film layer 109 on the P-channel MOS transistor formation region is covered with a resist 18, and the surface of the oxide film layer 109 on the N-channel MOS transistor formation region not covered with the resist 18 Oxide film on the N channel MOS transistor formation region with nitrogen ions (N ⁺ ) of 30 KeV and 4 × 10 ¹⁵ / cm ² so that the center of the range comes to the center of the oxide film layer 109 from the top. Ion implantation is performed on the layer 109. The nitrogen concentration distribution in the oxide film layer 109 on the N channel type MOS transistor formation region at this time is as shown in FIGS.

  Then, as shown in FIG. 58, the resist 18 formed on the P channel type MOS transistor formation region is removed, and the oxide film layer 109 is etched by anisotropic reactive ion etching to form the first gate electrode 8. And the first gate insulating film 7 and the side wall of the first gate insulating film 7 and the side wall of the second gate electrode 28 are formed. A second sidewall 9 is formed in contact with the side surface of the second gate insulating film 27 and one main surface of the semiconductor substrate 1.

Thereafter, as shown in FIG. 59, the P-channel MOS transistor formation region is covered with a resist 19, the N-channel MOS transistor formation region is exposed, and the first gate electrode 8 and the first sidewall 9 are masked. As a part, an impurity of N-type conductivity, for example, arsenic (As) is ion-implanted into one main surface of the semiconductor substrate 1 under the conditions of, for example, 50 KeV, 4 × 10 ¹⁵ / cm ² , and the high concentration diffusion region 104b and 105b is formed.

Next, as shown in FIG. 60, the N-channel MOS transistor formation region is covered with a resist 20, the P-channel MOS transistor formation region is exposed, and the second gate electrode 28 and the second sidewall 29 are masked. As one part, a P-type conductivity type impurity such as boron fluoride ion (BF ₂ ⁺ ) is ion-implanted into one main surface of the semiconductor substrate 1 under the conditions of, for example, 20 KeV and 4 × 10 ¹⁵ / cm ^2. Second source / drains 24 and 25 are formed.

  Then, heat treatment is performed at 850 ° C. for about 20 minutes to activate the arsenic ions forming the low-concentration diffusion regions 104a and 105a and the high-concentration diffusion regions 104b and 105b, and the second source / drains 24 and 25 By activating the boron fluoride ions forming the low-concentration diffusion regions 4a and 5a whose ends are in contact with the first channel region 6 and the first channel region 6 are located outside. A pair of first source / drain regions 4 and 5 composed of high concentration diffusion regions 4b and 5b integrally formed with the low concentration diffusion regions 4a and 5a are formed, and in the second channel region 26, The second source / drains 24 and 25 having the ends in contact with each other are formed.

  By the heat treatment at this time, nitrogen in the first sidewall 9 is diffused, and nitrogen is segregated at the interface between the first sidewall 9 and one main surface of the semiconductor substrate 1, and as shown in FIG. 1 is a nitrogen concentration distribution having a peak at the interface between one sidewall 9 and one main surface of the semiconductor substrate 1. In this way, the N channel having the pair of first source / drain regions 4 and 5, the first gate insulating film 7, the first gate electrode 8, and the first sidewall 9 into which nitrogen is implanted. A P-type MOS transistor having a pair of second source / drain regions 24 and 25, a second gate insulating film 27, a second gate electrode 28, and a second sidewall 29 is obtained. It is what you get.

  Thereafter, an interlayer insulating film 10 is formed on the entire main surface of the semiconductor substrate 1, contact holes 10a to 10d are formed in the interlayer insulating film 10, and the first source / drain regions 4 are formed via the contact holes 10a. Are electrically connected to the first source / drain region 5 through the contact hole 10b of the interlayer insulating layer 10 and the wiring layer 11 formed on the interlayer insulating layer 10. A wiring layer 12 formed on the interlayer insulating film 10 and a wiring layer 15 electrically connected to the second source / drain region 24 through the contact hole 10c of the interlayer insulating film 10 and formed on the interlayer insulating layer 10; The wiring layer 16 formed on the interlayer insulating layer 10 is formed by being electrically connected to the second source / drain region 5 through the contact hole 10d of the interlayer insulating layer 10, and FIG. It is that obtained the semiconductor device shown in.

  In the semiconductor device having the N-channel MOS transistor and the P-channel MOS transistor configured as described above, nitrogen is implanted into the first sidewall 9 constituting the N-channel MOS transistor by ion implantation. The concentration distribution in which nitrogen segregates at the interface between the first sidewall 9 and one main surface of the semiconductor substrate 1 by the subsequent heat treatment, that is, the interface between the first sidewall 9 and one main surface of the semiconductor substrate 1. Since the concentration distribution of nitrogen having a peak is obtained, the same effects as those of the first embodiment described above can be obtained.

Example 10
FIG. 61 shows Embodiment 10 of the present invention. In contrast to that shown in Embodiment 9 above, the method of injecting nitrogen into the first side wall 9 shown in Embodiment 9 is the first embodiment. In contrast to the case where the ion implantation is performed perpendicularly to the oxide film layer 109 for forming the side wall 9 of this embodiment, the embodiment 10 shows only that the oxide film layer 109 is subjected to the rotational oblique ion implantation. The other points are the same as in the ninth embodiment.

  That is, what was shown in this Example 10 is manufactured as follows. First, in the same manner as shown in FIGS. 53 to 56, the first gate electrode 8, the pair of low-concentration diffusion regions 104a and 105a, and the second gate electrode 28 are formed, and the first gate electrode 8 is formed. An oxide film layer 109 having a thickness of, for example, about 1000 mm is formed by CVD on the surface of the silicon substrate, the pair of low-concentration diffusion regions 104a and 105a, the second gate electrode 28, and the exposed surface of one main surface of the semiconductor substrate 1. To do.

Thereafter, as shown in FIG. 61, the oxide film layer 109 on the P-channel MOS transistor formation region is covered with a resist 18, and the surface of the oxide film layer 109 on the N-channel MOS transistor formation region not covered with the resist 18 is covered. Oxidation on the N-channel MOS transistor formation region with nitrogen ions (N ⁺ ) of 40 KeV and 5.6 × 10 ¹⁵ / cm ² so that the center of the range comes to the center of the oxide film layer 109 from the top. The film layer 109 is subjected to 45 ° rotation oblique ion implantation. At this time, the nitrogen concentration distribution in the II, II-II, and III-III cross sections shown in FIG. 61 in the oxide film layer 109 on the N channel type MOS transistor formation region is the same as that shown in the second embodiment. The same concentration distribution is shown.

  The tenth embodiment shown in the tenth embodiment is similar to that shown in the ninth embodiment, in the vicinity of the interface between the oxide film layer 109 and one main surface of the semiconductor substrate 1 in the II cross section, that is, the first gate insulating film 7. The nitrogen concentration in the vicinity of the end is high.

  Thereafter, the oxide film layer 109 is etched by anisotropic reactive ion etching in the same manner as in the ninth embodiment, that is, as shown in FIGS. And a side wall of the first gate insulating film 7 and a first sidewall 9 in contact with the pair of low-concentration diffusion regions 104a and 105a, and a side surface of the second gate electrode 28 and the second gate insulating film 27 A second side wall 29 in contact with the side surface and the exposed surface of one main surface of the semiconductor substrate 1 is formed, and the first gate electrode 8 and the first side wall 9 are used as part of the mask to form an N-type conductivity type. Impurities are ion-implanted to form high-concentration diffusion regions 104b and 105b, and P-type conductivity type impurities are ion-implanted using the second gate electrode 28 and the second sidewall 29 as part of the mask. Second source / drain regions 24 and 25 are formed, heat treatment is applied, and lightly doped diffusion regions 4a and 5a whose ends are in contact with first channel region 6 are formed, and outward from first channel region 6 A pair of first source / drain regions 4 and 5, which are formed of high concentration diffusion regions 4 b and 5 b, which are integrated with the low concentration diffusion regions 4 a and 5 a, are formed in the second channel region 26. Second source / drain regions 24 and 25 in contact with the end portions are formed, and further, nitrogen in the first sidewall 9 is diffused to form the first sidewall 9 and one main surface of the semiconductor substrate 1. A pair of first source / drain regions 4 and 5, a first gate insulating film 7, a first gate electrode 8, and nitrogen were implanted so as to obtain a nitrogen concentration distribution having a peak at the interface. First side war 9 and an N channel type MOS transistor and a pair of second source / drain regions 24 and 25, a second gate insulating film 27, a second gate electrode 28, and a P channel having a second sidewall 29 A type MOS transistor is obtained, and then an interlayer insulating film 10 and wiring layers 11, 12, 15 and 16 are formed to obtain a semiconductor device.

  Even in the tenth embodiment configured as described above, the N-channel MOS transistor forming region is provided in order to obtain the first sidewall 9 implanted with nitrogen in addition to the same effects as the ninth embodiment. Since the upper oxide film layer 109 is formed by rotational oblique ion implantation, the concentration of nitrogen implanted into the oxide film layer 109 near the end of the first gate insulating film 7 can be also implanted high, and thereafter by heat treatment. Since the concentration peak formed by the segregation of nitrogen at the interface between the first sidewall 9 and one main surface of the semiconductor substrate 1 is higher than that shown in Example 9, the hot carrier resistance is further improved. It is.

Example 11
62 to 67 show an eleventh embodiment of the present invention. Compared to the ninth embodiment, nitrogen is also introduced into the second sidewall 29 constituting the P-channel MOS transistor. 62 (the concentration distribution in the VV cross section shown in FIG. 62 is the same as the concentration distribution in the II cross section), and the surfaces of the pair of first source / drain regions 4 and 5 constituting the N-channel MOS transistor and Cobalt silicide (CoSi ₂ ) or titanium on the surface of one gate electrode 8, the surfaces of the pair of second source / drain regions 24 and 25 and the surface of the second gate electrode 28 constituting the P-channel MOS transistor silicide (TiSi ₂₎ is in the different embodiments 9 in that the refractory metal silicide layer 31 to 36 are formed, other Is the same as that of Example 9 for the point.

  Next, a method for manufacturing the semiconductor device configured as described above will be described with reference to FIGS. First, the first gate electrode 8 and the pair of low-concentration diffusion regions 104a and 105a constituting the N-channel MOS transistor are formed on the basis of the one shown in FIGS. The second gate electrode 28 constituting the P-channel MOS transistor is formed, and the surface of the first gate electrode 8 and the pair of low-concentration diffusion regions 104a and 105a and the second gate electrode 28 are formed. An oxide film layer 109 having a thickness of, for example, about 1000 mm is formed by CVD on the surface and on the exposed surface of one main surface of the semiconductor substrate 1.

Thereafter, as shown in FIG. 63, nitrogen ions (N ⁺ ) are applied at 30 KeV and 4 × 10 ¹⁵ / cm ² so that the center of the range comes from the surface of the oxide film layer 109 to the inside and almost the center of the oxide film layer 109. Ions are implanted into the oxide film 109 under these conditions. The nitrogen concentration distribution in the II section or the III-III section in the oxide film layer 109 at this time is as shown in FIGS. 8 to 10 as in the ninth embodiment. Is the same as the concentration distribution of nitrogen in the II section.

  Then, the oxide film layer 109 introduced with nitrogen is etched by anisotropic reactive ion etching based on the one shown in FIGS. A side wall of the gate electrode 8, a side surface of the first gate insulating film 7, and a first sidewall 9 in which nitrogen is in contact with the pair of low-concentration diffusion regions 104 a and 105 a are formed, and a second gate electrode 28 is formed. The second side wall 9 in contact with the side surface of the second gate insulating film 27 and the main surface of the semiconductor substrate 1 is formed, and the first gate electrode 8 and the first side wall 9 are formed as a mask. As a part, ions are implanted to form the high concentration diffusion regions 104b and 105b, and the second gate electrode 28 and the second sidewall 29 are used as part of the mask to implant the second source / drain. To form an in-24 and 25.

  Then, heat treatment is performed at 850 ° C. for about 20 minutes to activate the arsenic ions forming the low-concentration diffusion regions 104a and 105a and the high-concentration diffusion regions 104b and 105b, and the second source / drains 24 and 25 By activating the boron fluoride ions forming the low-concentration diffusion regions 4a and 5a whose ends are in contact with the first channel region 6 and the first channel region 6 are located outside. A pair of first source / drain regions 4 and 5 composed of high concentration diffusion regions 4b and 5b integrally formed with the low concentration diffusion regions 4a and 5a are formed, and in the second channel region 26, The second source / drains 24 and 25 having the ends in contact with each other are formed.

  By the heat treatment at this time, nitrogen in the first sidewall 9 and the second sidewall 29 is diffused, and the interface between the first sidewall 9 and one main surface of the semiconductor substrate 1, and the second sidewall. Nitrogen is segregated at the interface between the main surface 29 and one main surface of the semiconductor substrate 1, and as shown in FIG. 2, the nitrogen concentration distribution has a peak at these interfaces.

  Next, as shown in FIG. 64, over the entire main surface of the semiconductor substrate 1, that is, the element isolation insulating film 2, the pair of first source / drain regions 4 and 5, the first gate electrode 8, the first A refractory metal such as cobalt or titanium is formed on the surface of one side wall 9, the pair of second source / drain regions 24 and 25, the second gate electrode 28, and the second side wall 29 by sputtering, for example. A pair of first source / drain regions 4 and 5, a first gate electrode 8, a pair of second source / drain regions 24 and 25, and a second gate are deposited by about 500 ° C. and lamp annealing of about 500 degrees. A refractory metal of cobalt or titanium in contact with the surface of the electrode 28 is reacted to form a refractory metal silicide layer of cobalt silicide or titanium silicide.

  Thereafter, selective etching of the refractory metal and the refractory metal silicide is performed to remove the refractory metal, and then, as shown in FIG. 65, the pair of first source / drain regions 4 and the pair of first source / drain regions 4 and 5, the low temperature of the refractory metal silicide layers 31 to 36 of cobalt silicide or titanium silicide formed on the surface of the first gate electrode 8, the pair of second source / drain regions 24 and 25, and the second gate electrode 28. Aim at resistance.

  In this manner, the pair of first source / drain regions 4 and 5, the first gate insulating film 7, the first gate electrode 8, the first sidewall 9 into which nitrogen is implanted, and the refractory metal silicide. An N-channel MOS transistor having layers 31 to 33 is obtained, and a pair of second source / drain regions 24 and 25, a second gate insulating film 27, a second gate electrode 28, a second sidewall 29, In addition, a P-channel MOS transistor having refractory metal silicide layers 34 to 36 is obtained.

  Thereafter, an interlayer insulating film 10 is formed on the entire main surface of the semiconductor substrate 1, contact holes 10a to 10d are formed in the interlayer insulating film 10, and the refractory metal silicide layer 31 is electrically connected to the contact hole 10a. Connected to and electrically connected to the first source / drain region 4, a wiring layer 11 formed on the interlayer insulating layer 10, and a refractory metal silicide layer via a contact hole 10 b in the interlayer insulating layer 10. 32 and is electrically connected to the first source / drain region 5, and has a high melting point via the wiring layer 12 formed on the interlayer insulating layer 10 and the contact hole 10 c of the interlayer insulating film 10. A wiring layer 15 electrically connected to the metal silicide layer 34 and electrically connected to the second source / drain region 24 and formed on the interlayer insulating layer 10, and interlayer insulation The wiring layer 16 formed on the interlayer insulating layer 10 is formed by being electrically connected to the refractory metal silicide layer 35 through the 10 contact holes 10 d and electrically connected to the second source / drain region 5. Thus, the semiconductor device shown in FIG. 62 is obtained.

  At this time, the refractory metal silicides 31, 32, 34, and 35 make the electrical connection between the wiring layers 11 and 12 and the first source / drain regions 4 and 5 with a low resistance and the first source / drain. It functions as a diffusion barrier layer from the wiring layers 11 and 12 to the regions 4 and 5, and makes the electrical connection between the wiring layers 15 and 16 and the second source / drain regions 24 and 25 with a low resistance and the second. It functions as a diffusion barrier layer from the wiring layers 15 and 16 for the source / drain regions 24 and 25.

  Even in the eleventh embodiment configured as described above, in addition to the same effects as the ninth embodiment, the following advantages are also obtained. Since nitrogen is introduced into each of the first and second sidewalls 9 and 29, when the refractory metal and silicon are reacted by lamp annealing to form the refractory metal silicide, The source / drain regions 4 and 5 are laterally grown on the first sidewall 9 to suppress the formation of refractory metal silicide on the first sidewall 9 and the first gate electrode 8. The first source / drain regions 4 and 5 and the first source / drain regions 4 and 5 are prevented from growing laterally on the first side wall 9 and suppressing the formation of refractory metal silicide on the first side wall 9. A refractory metal silicide is prevented from being formed on the first side wall 9 that short-circuits the gate electrode 8, and the pair of second source / drain regions 24 and 25. The second side wall 29 is laterally grown to suppress the formation of a refractory metal silicide on the second side wall 9 and the first gate electrode 28 to the second side wall 29 are suppressed. The second source / drain regions 24 and 25 and the second gate electrode 28 are short-circuited by suppressing the formation of refractory metal silicide on the second sidewall 29 by growing in the horizontal direction. The formation of the refractory metal silicide on the second sidewall 29 is prevented.

Example 12 FIG.
FIG. 66 shows a twelfth embodiment of the present invention. A method of injecting nitrogen into the first sidewall 9 and the second sidewall 29 is different from that shown in the eleventh embodiment in the eleventh embodiment. The one shown in FIG. 2 differs from the one in which ion implantation is performed perpendicularly to the oxide film layer 109, whereas the one shown in this embodiment 12 differs only in that the ion implantation is performed on the oxide film layer 109 by rotational oblique ion implantation. The other points are the same as those of the eleventh embodiment.

  That is, what was shown in this Example 12 is manufactured as follows. First, in the same manner as shown in FIGS. 53 to 56, the first gate electrode 8 and the pair of low-concentration diffusion regions 104a and 105a constituting the N-channel MOS transistor are formed, and the P-channel MOS transistor is formed. The second gate electrode 28 is formed on the surface of the first gate electrode 8, the pair of low-concentration diffusion regions 104a and 105a, the surface of the second gate electrode 28, and one main part of the semiconductor substrate 1. An oxide film layer 109 having a thickness of, for example, about 1000 mm is formed on the exposed surface of the surface by a CVD method.

Thereafter, as shown in FIG. 66, nitrogen ions (N ⁺ ) are applied at 40 KeV, 5.6 × 10 ¹⁵ / cm so that the center of the range comes from the surface of the oxide film layer 109 to the inside and almost the center of the oxide film 109. ^Under the condition of ² , a 45 ° rotation oblique ion implantation is performed on the polysilicon layer 14. The nitrogen concentration distribution in the II section and the VV section shown in FIG. 66 in the oxide film 109 at this time is as shown in FIG. Note that the concentration distributions in the portions corresponding to the II-II section and the III-III section shown in FIG. 66 are the same as those shown in Example 11.

  In the example 12, the nitrogen concentration in the vicinity of the interface between the polysilicon layer 14 and the oxide film layer 109 in the II section is higher than that in the example 11. .

  Thereafter, similarly to the embodiment 11, the oxide film layer 109 introduced with nitrogen is etched by anisotropic reactive ion etching based on the one shown in FIGS. And the second side wall 9 are formed, and ion implantation is performed using the first gate electrode 8 and the first side wall 9 as a part of the mask to form the high concentration diffusion regions 104b and 105b, and the second gate electrode The second source / drains 24 and 25 are formed by ion implantation using the 28 and the second sidewall 29 as a part of the mask, and heat treatment is performed at 850 ° C. for about 20 minutes, and the low-concentration diffusion regions 104a and 105a. And arsenic ions forming the high-concentration diffusion regions 104b and 105b are activated, and second source / drains 24 and 25 are formed. By activating boron nitride ions, a pair of first source / drain regions 4 and 5 composed of low-concentration diffusion regions 4a and 5a and high-concentration diffusion regions 4b and 5b are formed and second source / drain regions are formed. Drains 24 and 25 are formed.

  By the heat treatment at this time, nitrogen in the first sidewall 9 and the second sidewall 29 is diffused, and the interface between the first sidewall 9 and one main surface of the semiconductor substrate 1, and the second sidewall. Nitrogen is segregated at the interface between the main surface 29 and one main surface of the semiconductor substrate 1, and as shown in FIG. 2, the nitrogen concentration distribution has a peak at these interfaces. Thereafter, as shown in FIGS. 64 and 65, the pair of first source / drain regions 4 and 5, the first gate electrode 8, the pair of second source / drain regions 24 and 25, and the second gate electrode. Refractory metal silicide layers 31 to 36 of cobalt silicide or titanium silicide formed on the surface 28 are formed.

  In this manner, the pair of first source / drain regions 4 and 5, the first gate insulating film 7, the first gate electrode 8, the first sidewall 9 into which nitrogen is implanted, and the refractory metal silicide. An N-channel MOS transistor having layers 31 to 33 is obtained, and a pair of second source / drain regions 24 and 25, a second gate insulating film 27, a second gate electrode 28, a second sidewall 29, In addition, a P-channel MOS transistor having refractory metal silicide layers 34 to 36 is obtained.

  Thereafter, an interlayer insulating film 10 is formed on the entire main surface of the semiconductor substrate 1, contact holes 10a to 10d are formed in the interlayer insulating film 10, and the first source / drain regions 4 are formed via the contact holes 10a. Is electrically connected to the first source / drain region 5 through the contact hole 10b of the interlayer insulating layer 10 and the wiring layer 11 formed on the interlayer insulating layer 10, and is connected to the interlayer insulating layer. A wiring layer 12 formed on the interlayer insulating film 10 and a wiring layer 15 electrically connected to the second source / drain region 24 through the contact hole 10c of the interlayer insulating film 10 and formed on the interlayer insulating layer 10; The wiring layer 16 formed on the interlayer insulating layer 10 is formed by being electrically connected to the second source / drain region 5 through the contact hole 10d of the interlayer insulating layer 10, and FIG. It is that obtained the semiconductor device shown in.

  Even in the twelfth embodiment configured as described above, the same effect as that of the eleventh embodiment can be obtained. In addition, in order to obtain the first sidewall 9 in which nitrogen is implanted, the oxide film layer 109 is rotated obliquely. Since the ion implantation is performed, the concentration of nitrogen implanted into the oxide film layer 109 near the end of the first gate insulating film 7 also increases, and the first sidewall 9 and one main surface of the semiconductor substrate 1 Since the peak of the nitrogen concentration at the interface with the substrate becomes higher than that shown in Example 11, further hot carrier resistance is improved.

  In addition, the concentration of nitrogen implanted into the oxide film layer 109 near the end of the first gate insulating film 7 and the concentration of nitrogen implanted into the oxide film layer 109 near the end of the second gate insulating film 27. The concentration also increases, and the peaks of the nitrogen concentration at the interface between the first sidewall 9 and one principal surface of the semiconductor substrate 1 and the interface between the second sidewall 29 and one principal surface of the semiconductor substrate 1 are also shown in Example 11. Therefore, when the refractory metal silicide layer is formed, the first and second side walls 9 and 29 are formed from the first and second source / drain regions 4 and 5, 24 and 25. The growth of the refractory metal silicide layer in the lateral direction on the surface can be further suppressed.

  Other Embodiments In the first to twelfth embodiments, the pair of source / drain regions 4 and 5 constituting the N-channel MOS transistor are formed by ion implantation of arsenic. Instead of arsenic, phosphorus (P) may be formed by ion implantation, and low concentration diffusion regions 104a and 105a are formed by arsenic, and high concentration diffusion regions 104b and 105b are formed by ion implantation of phosphorus. Is also good. Further, as these ion implantations, rotation oblique ion implantation may be used instead of vertical ion implantation.

  In the embodiments 9 to 12, a pair of second source / drain regions 24 and 25 constituting a P-channel MOS transistor are formed by implanting boron fluoride ions. As shown, boron (B) ions may be implanted instead of boron fluoride ions, and the pair of second source / drain regions 24 and 25 are formed after the second sidewall 29 is formed. However, it may be performed before the second sidewall 29 is formed.

  Further, in the examples shown in the examples 11 and 12, the first and second sidewalls 9 and 29 having a desired nitrogen concentration distribution are formed by ion-implanting nitrogen into the oxide film layer 109 and then performing heat treatment. The polysilicon layer 14 is formed on the oxide film layer 109 as shown in the third embodiment, and nitrogen is ion-implanted into the polysilicon layer 14 and then heat-treated. The first and second sidewalls 9 and 29 having a nitrogen concentration distribution may be formed. In this case, since the nitrogen concentration distribution peaks on the surfaces of the first and second sidewalls 9 and 29, the first and second sidewalls 9 and 29 are formed when the refractory metal silicide layer is formed. 29 can further suppress the lateral growth of the refractory metal silicide layer on the surface.

  Furthermore, in the examples shown in Examples 11 and 12, in which nitrogen is introduced into the first and second sidewalls 9 and 29, arsenic ions, boron ions, and phosphorus ions are further implanted. Is also good. In this case, arsenic ions, boron ions, or phosphorus ions may be ion-implanted before or after nitrogen is ion-implanted into the oxide film layer 109 for forming the first and second sidewalls 9 and 29. Thus, when arsenic, boron, or phosphorus is implanted in addition to nitrogen, the high melting point in the lateral direction on the surfaces of the first and second sidewalls 9 and 29 is formed during the formation of the refractory metal silicide layer. The growth of the metal silicide layer can be further suppressed.

(effect)
According to a first aspect of the present invention, there is provided a side wall formed on a side surface of a gate electrode, a side surface of a gate insulating film, and one main surface of a semiconductor substrate. Since the concentration distribution in the cross section in the direction perpendicular to the gate electrode is made of an oxide film into which nitrogen is introduced so that a peak is present at the interface with one main surface of the semiconductor substrate, the concentration distribution with the semiconductor substrate introduced into the sidewall is Nitrogen having a peak at the interface suppresses the interface state at the interface between the sidewall and the semiconductor substrate even if it is miniaturized, and reduces the probability that generated hot carriers are captured by the interface state. Transients such as changes in the threshold voltage of the MOS transistor and a decrease in drain current due to improved resistance, that is, hot carriers are trapped in the gate insulating film. Aging of the characteristics, and has the effect of so-called hot carrier deterioration can be suppressed.

  According to a second aspect of the present invention, there is provided a sidewall having a sidewall formed in contact with the side surface of the gate electrode, the side surface of the gate insulating film, and one main surface of the semiconductor substrate. An oxide film having a vertical section having a vertical portion in contact with the side surface of the insulating film and a bottom portion in contact with one main surface of the semiconductor substrate is formed in contact with the vertical portion and the bottom portion of the oxide film. Both of them have polysilicon introduced with nitrogen, so that the nitrogen introduced into the polysilicon constituting the sidewall and having a peak at the interface with the semiconductor substrate is reduced even when the sidewall is refined. Suppresses the interface state at the interface with the semiconductor substrate, reduces the probability that generated hot carriers are trapped in the interface state, and improves hot carrier resistance, that is, hot carrier deterioration It is those having the effect of being able to control.

  According to a third aspect of the present invention, there is provided a sidewall having a side surface formed in contact with the side surface of the gate electrode, the side surface of the gate insulating film, and one main surface of the semiconductor substrate, wherein the gate electrode is introduced with nitrogen. In addition, since the sidewall has an oxide film into which nitrogen is introduced, the nitrogen introduced into the gate electrode suppresses diffusion of impurities introduced into the gate electrode to reduce resistance, and the sidewall Even if the nitrogen introduced into the substrate is miniaturized, it suppresses the interface state at the interface between the sidewall and the semiconductor substrate, reduces the probability that generated hot carriers are trapped in the interface state, and resists hot carriers. Is improved, that is, hot carrier deterioration can be suppressed.

  According to a fourth aspect of the present invention, there is provided an N channel type MOS transistor having a sidewall and a P channel type MOS transistor having a sidewall. Since each of the walls is made of an oxide film into which nitrogen is introduced, even if the nitrogen introduced into the sidewall of the N-channel MOS transistor is miniaturized, the interface state at the interface between the sidewall and the semiconductor substrate is reduced. This reduces the probability that the generated hot carriers are trapped at the interface state and improves the hot carrier resistance in the N-channel MOS transistor, that is, has the effect of suppressing the hot carrier deterioration. .

  According to a fifth aspect of the present invention, an N-channel MOS transistor having a sidewall and a P-channel MOS transistor having a sidewall are provided. Each wall is made of an oxide film into which nitrogen is introduced, a metal silicide layer is formed on the gate electrode and the pair of source / drain regions of the N-channel MOS transistor, and the P-channel MOS transistor Since the metal silicide layer is formed on the gate electrode and the pair of source / drain regions, even if the nitrogen introduced into the sidewall of the N-channel MOS transistor is miniaturized, the sidewall and the semiconductor substrate are formed. Suppress the interface state at the interface with The probability that the generated hot carriers are trapped at the interface state is reduced, the hot carrier resistance in the N channel type MOS transistor is improved, that is, the hot carrier deterioration can be suppressed, and the N channel type MOS transistor and the P channel type transistor can be suppressed. Nitrogen introduced into each side wall of the MOS transistor suppresses lateral growth of the metal silicide layer on the side wall for reducing resistance, and prevents electrical short circuit between the gate electrode and the source / drain region. It has the effect of damaging.

  According to a sixth aspect of the present invention, an oxide film layer is formed by CVD on the surface of the gate electrode and the exposed surface of the semiconductor substrate, and nitrogen ions are implanted into the oxide film layer from the surface of the oxide film layer. And a step of etching the oxide film layer implanted with nitrogen to form a sidewall in contact with the side surface of the gate electrode, the side surface of the gate insulating film, and one main surface of the semiconductor substrate. Nitrogen having a peak at the interface with the semiconductor substrate can be easily introduced into the sidewall, thereby improving the hot carrier resistance, that is, obtaining an MOS transistor in which hot carrier deterioration can be suppressed.

  A seventh invention of the present invention includes a step of forming an oxide film layer on the surface of the gate electrode and the exposed surface of the semiconductor substrate by a CVD method, a step of forming a polysilicon layer on the surface of the oxide film layer, A step of implanting nitrogen ions into the polysilicon layer from the surface of the polysilicon layer, a step of diffusing nitrogen implanted into the polysilicon layer into the oxide film layer, and an oxidation in which the polysilicon layer is removed and nitrogen is implanted Since the film layer is etched to form a sidewall in contact with the side surface of the gate electrode, the side surface of the gate insulating film, and one main surface of the semiconductor substrate, the interface between the sidewall and the semiconductor substrate has a peak. Nitrogen can be easily introduced into the sidewall, and the hot carrier resistance is improved, that is, it is possible to obtain a MOS transistor that can suppress hot carrier deterioration. Than is.

  According to an eighth aspect of the present invention, a step of forming an oxide film layer by a CVD method on the surface of the gate electrode and the exposed surface of the semiconductor substrate, a step of forming a polysilicon layer on the surface of the oxide film layer, Implanting nitrogen ions into the polysilicon layer from the surface of the polysilicon layer, etching the polysilicon layer implanted with nitrogen, and etching the oxide film layer to the side surface of the gate electrode and the side surface of the gate insulating film An oxide film having an approximately L-shaped longitudinal section having a vertical portion in contact with a bottom portion in contact with one main surface of a semiconductor substrate, and a vertical portion and a bottom portion of the oxide film are formed in contact with nitrogen. A step of forming a sidewall having the polysilicon formed, nitrogen having a peak at the interface between the sidewall and the semiconductor substrate can be easily introduced into the sidewall, Yaria resistance improvement, i.e., those having the effect that it is possible to obtain a MOS transistor which hot carrier degradation was suppressed.

  According to a ninth aspect of the present invention, there is provided a step of forming an oxide film layer by a CVD method on the surface of the gate electrode and the exposed surface of the semiconductor substrate, and nitrogen ions from at least the oxide film layer on the surface of the oxide film layer. Injecting into the main surface of the semiconductor substrate where the side surface of the gate electrode and the side surface of the gate oxide film are in contact with each other, the exposed surface of the gate electrode and the semiconductor substrate are located, and etching the oxide film layer to form the side surface of the gate electrode And a step of forming a sidewall having an oxide film into which nitrogen is introduced in contact with a side surface of the gate insulating film and one main surface of the semiconductor substrate, nitrogen having a peak at the interface between the sidewall and the semiconductor substrate is provided. Can be easily introduced into the sidewall, nitrogen can be introduced into the gate electrode, and diffusion of impurities introduced to the gate electrode to reduce resistance can be suppressed and hot. Yaria resistance improvement, i.e., those having the effect that it is possible to obtain a MOS transistor which hot carrier degradation was suppressed.

  According to a tenth aspect of the present invention, a low concentration diffusion region of a pair of source / drain regions is formed by implanting an N-type conductivity type impurity into one main surface of a semiconductor substrate using a gate electrode as a part of a mask. A step of forming an oxide film layer by a CVD method on the surface of the gate electrode and the low concentration diffusion region of the pair of source / drain regions, and implanting nitrogen ions into the oxide film layer from the surface of the oxide film layer A step of etching the oxide film layer implanted with nitrogen to form a sidewall in contact with the side surface of the gate electrode, the side surface of the gate insulating film, and the low concentration diffusion region of the pair of source / drain regions; And a step of forming a high-concentration diffusion region of a pair of source / drain regions by implanting N-type conductivity type impurities into one main surface of the semiconductor substrate using the sidewall as a part of the mask. Nitrogen having a peak at the interface between the side wall and the semiconductor substrate can be easily introduced into the side wall, improving the hot carrier resistance, that is, having an effect of obtaining a MOS transistor that can suppress hot carrier deterioration. is there.

  In an eleventh aspect of the present invention, an N-type conductivity type impurity is implanted into one main surface of a semiconductor substrate using a gate electrode as a part of a mask to form a low concentration diffusion region of a pair of source / drain regions. A step, a step of forming an oxide film layer by a CVD method on the surface of the gate electrode and a low concentration diffusion region of the pair of source / drain regions, a step of forming a polysilicon layer on the surface of the oxide film layer, A step of implanting nitrogen ions into the polysilicon layer from the surface of the polysilicon layer, a step of diffusing nitrogen implanted into the polysilicon layer into the oxide film layer, and an oxidation in which the polysilicon layer is removed and nitrogen is implanted Etching the film layer to form a sidewall in contact with the side surface of the gate electrode, the side surface of the gate insulating film, and the low concentration diffusion region of the pair of source / drain regions; And forming a high-concentration diffusion region of the pair of source / drain regions by injecting an N-type conductivity type impurity into one main surface of the semiconductor substrate, using the sidewall as a part of the mask. Nitrogen having a peak at the interface with the semiconductor substrate can be easily introduced into the sidewall, thereby improving the hot carrier resistance, that is, obtaining an MOS transistor in which hot carrier deterioration can be suppressed.

  According to a twelfth aspect of the present invention, a low concentration diffusion region of a pair of source / drain regions is formed by implanting an N-type conductivity type impurity into one main surface of a semiconductor substrate using a gate electrode as a part of a mask. A step, a step of forming an oxide film layer by a CVD method on the surface of the gate electrode and a low concentration diffusion region of the pair of source / drain regions, a step of forming a polysilicon layer on the surface of the oxide film layer, Implanting nitrogen ions into the polysilicon layer from the surface of the polysilicon layer, etching the polysilicon layer implanted with nitrogen, and etching the oxide film layer to the side surface of the gate electrode and the side surface of the gate insulating film An oxide film having a substantially L-shaped longitudinal section having a vertical portion in contact and a bottom portion in contact with the low concentration diffusion region of the pair of source / drain regions, and a shape in contact with the vertical portion and the bottom portion of the oxide film At the same time, a step of forming a sidewall having polysilicon into which nitrogen has been introduced, and an N-type conductivity type impurity on one main surface of the semiconductor substrate using the gate electrode and the sidewall as a part of the mask. And a step of forming a high concentration diffusion region of the pair of source / drain regions by implantation, nitrogen having a peak at the interface between the sidewall and the semiconductor substrate can be easily introduced into the sidewall, and hot carrier resistance is improved. This has the effect of improving, that is, obtaining a MOS transistor in which deterioration of hot carriers can be suppressed.

  In a thirteenth aspect of the present invention, an N-type conductivity type impurity is implanted into one main surface of a semiconductor substrate using a gate electrode as a part of a mask to form a low concentration diffusion region of a pair of source / drain regions. A step of forming an oxide film layer by a CVD method on the surface of the gate electrode and on the low-concentration diffusion region of the pair of source / drain regions; and nitrogen ions from at least the oxide film layer on the surface of the oxide film layer Implanting the gate electrode side surface and the inner region in contact with the side surface of the gate oxide film, the gate electrode, and the low concentration diffusion region of the pair of source / drain regions, etching the oxide film layer, Forming a sidewall having an oxide film into which nitrogen is introduced in contact with the side surface of the insulating film and the low-concentration diffusion region of the pair of source / drain regions, and the gate electrode and the sidewall As a part of the mask, a step of injecting N-type conductivity type impurities into one main surface of the semiconductor substrate to form a high concentration diffusion region of a pair of source / drain regions is provided. Nitrogen having a peak at the interface can be easily introduced into the sidewall, nitrogen can also be introduced into the gate electrode, diffusion of impurities introduced to the gate electrode for low resistance can be suppressed, and hot carrier resistance can be achieved. This has the effect of improving, that is, obtaining a MOS transistor in which deterioration of hot carriers can be suppressed.

  In a fourteenth aspect of the present invention, an oxide film layer is formed on the surface of the first gate electrode of the N channel type MOS transistor and the second gate electrode of the P channel type MOS transistor and on the exposed surface of the semiconductor substrate by a CVD method. A step of forming and covering the surface of the oxide film layer located on the P-channel MOS transistor formation region, and applying nitrogen ions to the oxide film layer from the surface of the oxide film layer located on the N-channel MOS transistor formation region A step of implanting, etching the oxide film layer located on the N-channel MOS transistor formation region into which nitrogen has been implanted, and etching the side surface of the first gate electrode, the side surface of the first gate insulating film, and one main part of the semiconductor substrate A step of forming a sidewall of the N-channel MOS transistor in contact with the surface. Can be introduced easily sidewall nitrogen having, improved hot carrier resistance, i.e., those having an effect that it is possible to obtain a semiconductor device having an N-channel type MOS transistor hot carrier degradation was suppressed.

  According to a fifteenth aspect of the present invention, an oxide film layer is formed on the surface of the first gate electrode of the N channel type MOS transistor and the second gate electrode of the P channel type MOS transistor and on the exposed surface of the semiconductor substrate by a CVD method. A step of forming, a step of implanting nitrogen ions into the oxide film layer from the surface of the oxide film layer, and etching the oxide film layer into which nitrogen has been implanted to form a side surface of the first gate electrode and the first gate insulation. Forming a first sidewall of the N-channel MOS transistor in contact with the side surface of the film and one main surface of the semiconductor substrate, and forming a side surface of the second gate electrode, a side surface of the second gate insulating film, and one side of the semiconductor substrate; Forming a second sidewall of the P-channel MOS transistor in contact with the main surface, so that nitrogen having a peak at the interface between the sidewall and the semiconductor substrate is stored. To be introduced into the sidewalls, improve the hot carrier resistance, i.e., those having an effect that it is possible to obtain a semiconductor device having an N-channel type MOS transistor hot carrier degradation was suppressed.

  According to a sixteenth aspect of the present invention, an N channel type impurity is implanted by covering the P channel type MOS transistor forming region and implanting an N type conductivity type impurity using the first gate electrode of the N channel type MOS transistor as a part of a mask. A step of forming a low concentration diffusion region of the pair of first source / drain regions of the MOS transistor, a surface of the first gate electrode and the second gate electrode of the P-channel MOS transistor, and an exposed surface of the semiconductor substrate; A step of forming an oxide film layer by CVD, and covering the surface of the oxide film layer located on the P-channel MOS transistor formation region and from above the surface of the oxide film layer located on the N-channel MOS transistor formation region A step of implanting nitrogen ions into the oxide film layer, and an oxide film layer located on the N channel MOS transistor formation region into which nitrogen is implanted Etching to form the first sidewall of the N-channel MOS transistor in contact with the side surface of the first gate electrode, the side surface of the first gate insulating film, and the low concentration diffusion region of the pair of first source / drain regions In addition, the oxide film layer located on the P channel type MOS transistor formation region is etched to contact the side surface of the second gate electrode, the side surface of the second gate insulating film, and the exposed surface of the semiconductor substrate. A step of forming a second sidewall of the transistor, and an N-type conductivity impurity are implanted using the first gate electrode and the first sidewall as a part of the mask, covering the P-channel MOS transistor formation region. Forming a high concentration diffusion region of the pair of first source / drain regions, covering the N channel type MOS transistor formation region, A pair of second source / drain regions of the P-channel MOS transistor are formed by injecting a P-type conductivity type impurity into one main surface of the semiconductor substrate using the gate electrode and the second sidewall as a part of the mask. Therefore, nitrogen having a peak at the interface between the first sidewall and the semiconductor substrate can be easily introduced into the first sidewall, and hot carrier resistance can be improved, that is, hot carrier deterioration can be suppressed. In addition, the semiconductor device having the N channel type MOS transistor can be obtained.

  According to a seventeenth aspect of the present invention, an N-type MOS impurity is implanted by covering the P-channel MOS transistor formation region and implanting an N-type conductivity impurity using the first gate electrode of the N-channel MOS transistor as a part of a mask. Forming a low-concentration diffusion region of the pair of first source / drain regions of the transistor, on the surface of the first gate electrode and the second gate electrode of the P-channel MOS transistor, and on the exposed surface of the semiconductor substrate; A step of forming an oxide film layer by a CVD method, a step of injecting nitrogen ions into the oxide film layer from the surface of the oxide film layer, and etching the oxide film layer into which nitrogen has been implanted to form a first gate electrode The first sidewall of the N-channel MOS transistor is in contact with the side surface, the side surface of the first gate insulating film, and the low concentration diffusion region of the pair of first source / drain regions. Forming a second side wall of the P-channel MOS transistor in contact with the side surface of the second gate electrode, the side surface of the second gate insulating film, and one main surface of the semiconductor substrate; High-concentration diffusion regions of the pair of first source / drain regions by covering the type MOS transistor formation region and implanting N-type conductivity type impurities using the first gate electrode and the first sidewall as part of the mask And a step of forming a P-type MOS transistor by covering the N-channel MOS transistor formation region and implanting a P-type conductivity type impurity using the second gate electrode and the second sidewall as a part of the mask. And forming a pair of second source / drain regions, so that nitrogen having a peak at the interface between the first sidewall and the semiconductor substrate can be easily formed. Can be introduced into the first side wall, it improves the hot carrier resistance, i.e., those having an effect that it is possible to obtain a semiconductor device having an N-channel type MOS transistor hot carrier degradation was suppressed.

  According to an eighteenth aspect of the present invention, an N type conductivity impurity is implanted by covering the P channel type MOS transistor formation region and implanting an N type conductivity type impurity using the first gate electrode of the N channel type MOS transistor as a part of a mask. Forming a low-concentration diffusion region of the pair of first source / drain regions of the transistor, on the surface of the first gate electrode and the second gate electrode of the P-channel MOS transistor, and on the exposed surface of the semiconductor substrate; A step of forming an oxide film layer by a CVD method, a step of injecting nitrogen ions into the oxide film layer from the surface of the oxide film layer, and etching the oxide film layer into which nitrogen has been implanted to form a first gate electrode The first sidewall of the N-channel MOS transistor is in contact with the side surface, the side surface of the first gate insulating film, and the low concentration diffusion region of the pair of first source / drain regions. Forming a second side wall of the P-channel MOS transistor in contact with the side surface of the second gate electrode, the side surface of the second gate insulating film, and one main surface of the semiconductor substrate; High-concentration diffusion regions of the pair of first source / drain regions by covering the type MOS transistor formation region and implanting N-type conductivity type impurities using the first gate electrode and the first sidewall as part of the mask And a step of forming a P-type MOS transistor by covering the N-channel MOS transistor formation region and implanting a P-type conductivity type impurity using the second gate electrode and the second sidewall as a part of the mask. A step of forming a pair of second source / drain regions, a surface of the first gate electrode, a surface of the second gate electrode, and a table of the first source / drain regions; And a step of forming a metal silicide layer on the surface of the second source / drain region, nitrogen having a peak at the interface between the first sidewall and the semiconductor substrate can be easily formed on the first sidewall. Introduced and improved hot carrier resistance, that is, has an N-channel MOS transistor that can suppress hot carrier deterioration, and suppresses lateral growth of the metal silicide layer on the side wall to reduce resistance In addition, a semiconductor device having an N-channel MOS transistor and a P-channel MOS transistor that can prevent an electrical short circuit between the gate electrode and the source / drain region can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. The figure which shows the density | concentration distribution of nitrogen in the II cross section of FIG. Sectional drawing which shows the principal part which shows Example 1 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 1 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 1 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 1 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 1 of this invention in order of a process. The figure which shows the density | concentration distribution of nitrogen in the II cross section of FIG. The figure which shows the density | concentration distribution of nitrogen in the II-II cross section of FIG. The figure which shows the density | concentration distribution of the nitrogen in the III-III cross section of FIG. Sectional drawing which shows the principal part which shows Example 1 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 1 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 2 of this invention in order of a process. The figure which shows the density | concentration distribution of nitrogen in the II cross section of FIG. Sectional drawing which shows the principal part which shows Example 3 of this invention. The figure which shows the density | concentration distribution of nitrogen in the II cross section of FIG. The figure which shows the density | concentration distribution of nitrogen in the IV-IV cross section of FIG. Sectional drawing which shows the principal part which shows Example 3 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 3 of this invention in order of a process. The figure which shows the density | concentration distribution of nitrogen in the VV cross section of FIG. The figure which shows the density | concentration distribution of the nitrogen in the II-II cross section and III-III cross section of FIG. Sectional drawing which shows the principal part which shows Example 3 of this invention in order of a process. The figure which shows the density | concentration distribution of nitrogen in the II cross section of FIG. The figure which shows the density | concentration distribution of nitrogen in the II-II cross section of FIG. The figure which shows the density | concentration distribution of the nitrogen in the III-III cross section of FIG. Sectional drawing which shows the principal part which shows Example 3 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 3 of this invention in order of a process. The principal part sectional drawing which shows Example 4 of this invention in order of a process. FIG. 29 is a diagram showing a nitrogen concentration distribution in the II cross section of FIG. 28. Sectional drawing which shows the principal part which shows Example 5 of this invention. The figure which shows the density | concentration distribution of the nitrogen in the II cross section of FIG. Sectional drawing which shows the principal part which shows Example 5 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 5 of this invention in order of a process. The figure which shows the density | concentration distribution of nitrogen in the II cross section of FIG. The figure which shows the density | concentration distribution of nitrogen in the II-II cross section of FIG. The figure which shows the density | concentration distribution of the nitrogen in the III-III cross section of FIG. Sectional drawing which shows the principal part which shows Example 5 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 5 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 5 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 6 of this invention in process order. The figure which shows the density | concentration distribution of nitrogen in the II cross section of FIG. Sectional drawing which shows the principal part which shows Example 7 of this invention. The figure which shows the density | concentration distribution of nitrogen in the II cross section of FIG. The figure which shows the density | concentration distribution of nitrogen in the II-II cross section of FIG. The figure which shows the density | concentration distribution of nitrogen in the III-III cross section of FIG. Sectional drawing which shows the principal part which shows Example 7 of this invention in process order. The figure which shows the density | concentration distribution of the nitrogen in the II cross section of FIG. The figure which shows the density | concentration distribution of the nitrogen in the II-II cross section of FIG. The figure which shows the density | concentration distribution of the nitrogen in the III-III cross section of FIG. The principal part sectional drawing which shows Example 8 of this invention in order of a process. The figure which shows the density | concentration distribution of nitrogen in the II cross section of FIG. Sectional drawing which shows the principal part which shows Example 9 of this invention. Sectional drawing which shows the principal part which shows Example 9 of this invention in process order. Sectional drawing which shows the principal part which shows Example 9 of this invention in process order. Sectional drawing which shows the principal part which shows Example 9 of this invention in process order. Sectional drawing which shows the principal part which shows Example 9 of this invention in process order. Sectional drawing which shows the principal part which shows Example 9 of this invention in process order. Sectional drawing which shows the principal part which shows Example 9 of this invention in process order. Sectional drawing which shows the principal part which shows Example 9 of this invention in process order. Sectional drawing which shows the principal part which shows Example 9 of this invention in process order. Sectional drawing which shows the principal part which shows Example 10 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 10 of this invention. Sectional drawing which shows the principal part which shows Example 10 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 10 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 10 of this invention in order of a process. Sectional drawing which shows the principal part which shows Example 11 of this invention in order of a process. FIG. 6 is a cross-sectional view of a main part showing a conventional N-channel MOS transistor. Sectional drawing which shows the principal part which shows the other conventional N channel type MOS transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 4 and 5 source / drain area | region, 6 channel area | region, 7 gate insulating film, 8 gate electrode, 9 side wall, 9a oxide film, 9b polysilicon, 14 polysilicon layer, 24 and 25 source / drain area | region, 26 channel region, 27 gate insulating film, 28 gate electrode, 29 sidewall, 31-36 refractory metal silicide layer, 109 oxide film layer, 109a oxide film layer, 109b polysilicon layer.

Claims (2)

Forming a gate insulating film and a gate electrode on one main surface of the semiconductor substrate ;
Forming an oxide film on the surface of the gate electrode and on the exposed surface of the semiconductor substrate by chemical vapor deposition;
Implanting nitrogen ions into the oxide film through the surface of the oxide film;
Etching the oxide film implanted with nitrogen to form side walls of the gate electrode, side surfaces of the gate insulating film, and sidewalls in contact with the surface of the semiconductor substrate . A method for manufacturing a MOS transistor. 2. The method of manufacturing a MOS transistor according to claim 1 , wherein the nitrogen ions are implanted into the oxide film by an oblique rotation ion implantation method .