KR100326812B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100326812B1 KR100326812B1 KR1019990064096A KR19990064096A KR100326812B1 KR 100326812 B1 KR100326812 B1 KR 100326812B1 KR 1019990064096 A KR1019990064096 A KR 1019990064096A KR 19990064096 A KR19990064096 A KR 19990064096A KR 100326812 B1 KR100326812 B1 KR 100326812B1
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- plug
- ion implantation
- contact hole
- semiconductor device
- implantation process
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 150000002500 ions Chemical class 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 19
- 230000002093 peripheral effect Effects 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- -1 phosphorus ions Chemical class 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 17
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 210000004027 cell Anatomy 0.000 description 16
- 150000004767 nitrides Chemical class 0.000 description 8
- 238000002955 isolation Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 210000004692 intercellular junction Anatomy 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 셀(Cell) 영역의 측벽 형성 공정시 사용한 감광막을 마스크로 플러그(Plug) 이온주입 공정을 실시한 후 플러그 콘택홀을 형성하므로 플러그 저항 및 누설 전류를 감소시키기 위한 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device for reducing plug resistance and leakage current since a plug contact hole is formed after a plug ion implantation process is performed using a photoresist film used in the sidewall formation process of a cell region as a mask. will be.
본 발명의 반도체 소자의 제조 방법은 셀 영역의 측벽 형성 공정시 사용한 감광막을 마스크로 사용하여 추가적인 공정 없이 플러그 이온주입 공정을 셀 영역에만 실시한 후 플러그 콘택홀을 형성하므로, 종래 기술보다 이온주입 면적이 넓으며 상기 플러그 이온주입 공정 후 층간 절연막을 형성하기 때문에 플러그 콘택홀 측면의 층간 절연막이 스퍼터링(Sputtering)되지 않아 콘택홀 계면의 특성 저하를 방지하고 상기 플러그 이온주입 공정 후 트랜지스터의 소오스/드레인 불순물 영역 형성 공정 및 층간 산화막의 플로우(Flow) 공정 시 사용한 열처리 공정에 의해 상기 플러그 이온이 종래 기술보다 더 활성화되어 누설 전류 감소로 디램(Dynamic Random Access Memory:DRAM)의 리프레쉬(Refresh) 특성을 향상시키고 또는 플러그 저항의 저하로 셀 전류가 증가되기 때문에 소자의 집적화에 따른 협소 폭 효과에 의한 셀 트랜지스터의 전류 감소를 보상하여 DRAM의 읽기/쓰기 특성을 향상시키므로 소자의 특성, 신뢰성 및 수율을 향상시키는 특징이 있다.In the method of manufacturing a semiconductor device of the present invention, the plug contact hole is formed after the plug ion implantation process is performed only in the cell region without the additional process by using the photoresist film used in the sidewall formation process of the cell region as a mask. Since the interlayer insulating film is formed after the plug ion implantation process, the interlayer insulation film on the side of the plug contact hole is not sputtered to prevent deterioration of the characteristics of the contact hole interface and the source / drain impurity region of the transistor after the plug ion implantation process. By the heat treatment process used in the formation process and the flow process of the interlayer oxide film, the plug ions are more activated than the prior art, thereby improving the refresh characteristics of the dynamic random access memory (DRAM) by reducing leakage current. Because the decrease in the plug resistance increases the cell current Compensating for the current reduction of the cell transistor due to the narrow width effect of the integration of the device improves the read / write characteristics of the DRAM, thereby improving the characteristics, reliability, and yield of the device.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 플러그(Plug) 이온주입 공정을 한 후 플러그 콘택홀을 형성하여 소자의 특성, 신뢰성 및 수율을 향상시키는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which a plug contact hole is formed after a plug ion implantation process to improve characteristics, reliability and yield of the device.
고집적 디램(Dynamic Random Access Memory:DRAM) 형성 시 비트 라인(BitLine)과 활성 영역사이에 전기적으로 연결되도록 셀(Cell) 플러그 공정을 진행한다.The cell plug process is performed to electrically connect between the bit line and the active region when forming a dynamic random access memory (DRAM).
종래 기술에 따른 반도체 소자의 제조 방법은 도 1a에서와 같이, 소자 분리 영역에 형성된 소자 분리 산화막(32)을 포함하며 셀 영역과 주변 영역이 정의된 반도체 기판(31)상에 절연 막을 개재하며 캡(Cap) 절연 막을 구비한 다수개의 워드 라인(Word Line)(33)을 형성한다.The method of manufacturing a semiconductor device according to the related art includes a device isolation oxide film 32 formed in a device isolation region, as shown in FIG. 1A, with an insulating film on a semiconductor substrate 31 having a cell region and a peripheral region defined therebetween. (Cap) A plurality of word lines 33 having an insulating film are formed.
그리고, 상기 워드 라인(33)들을 포함한 반도체 기판(31)상에 질화막(34)과 산화막(35)을 형성한다.The nitride film 34 and the oxide film 35 are formed on the semiconductor substrate 31 including the word lines 33.
도 1b에서와 같이, 상기 산화막(35)상에 제 1 감광막(36)을 도포하고, 상기 제 1 감광막(36)을 상기 셀 영역에만 남도록 선택적으로 노광 및 현상한다.As shown in FIG. 1B, a first photosensitive film 36 is coated on the oxide film 35, and the first photosensitive film 36 is selectively exposed and developed to remain only in the cell region.
그리고, 상기 선택적으로 노광 및 현상된 상기 제 1 감광막(36)을 마스크로 상기 주변 영역의 산화막(35)과 질화막(34)을 에치 백(Etch Back)하여 상기 주변 영역의 각 워드 라인(33) 양측의 반도체 기판(31)상에 700 ∼ 900Å 두께의 제 1 측벽(S)을 형성한다.The word line 33 of the peripheral region is etched back by using the selectively exposed and developed first photosensitive layer 36 as a mask. The first sidewall S having a thickness of 700 to 900 의 is formed on the semiconductor substrate 31 on both sides.
도 1c에서와 같이, 상기 제 1 감광막을 제거한 후, 상기 제 1 측벽(S)을 포함한 전면에 제 2 감광막(37)을 도포한다.As shown in FIG. 1C, after removing the first photoresist layer, a second photoresist layer 37 is coated on the entire surface including the first sidewall S. Referring to FIG.
그리고, 상기 제 2 감광막(37)을 상기 주변 영역에만 남도록 선택적으로 노광 및 현상한다.Then, the second photosensitive film 37 is selectively exposed and developed so as to remain only in the peripheral region.
이어, 상기 선택적으로 노광 및 현상된 상기 제 2 감광막(37)을 마스크로 상기 셀 영역의 산화막(35)을 질화막과 산화막간의 식각 선택비를 갖는 등방성 건식식각 방법에 의해 제거한 후, 상기 셀 영역의 질화막(34)을 에치 백하여 상기 각 워드 라인(33) 양측의 반도체 기판(31)상에 300 ∼ 500Å 두께의 제 2 측벽(S2)을 형성한다.Subsequently, the oxide film 35 of the cell region is removed by the isotropic dry etching method having an etch selectivity between the nitride film and the oxide film using the selectively exposed and developed second photosensitive film 37 as a mask. The nitride film 34 is etched back to form a second sidewall S2 having a thickness of 300 to 500 상 에 on the semiconductor substrate 31 on each side of the word line 33.
도 1d에서와 같이, 상기 제 2 감광막(37)을 제거한 다음, 상기 제 2 측벽(S2)을 포함한 전면에 층간 절연막(38)을 형성하고 플로우(Flow)한다.As shown in FIG. 1D, after removing the second photoresist layer 37, an interlayer insulating layer 38 is formed on the entire surface including the second sidewall S2 and flows therein.
도 1e에서와 같이, 상기 층간 절연막(38)상에 제 3 감광막을 도포한 후, 상기 제 3 감광막을 플러그 콘택이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 1E, after applying a third photoresist film on the interlayer insulating film 38, the third photoresist film is selectively exposed and developed to be removed only at a portion where a plug contact is to be formed.
그리고, 상기 선택적으로 노광 및 현상된 상기 제 3 감광막을 마스크로 상기 층간 절연막(38)을 선택적으로 식각하여 콘택홀을 형성한 후, 상기 제 3 감광막(39)을 제거한다.The interlayer insulating layer 38 is selectively etched using the selectively exposed and developed third photoresist layer to form a contact hole, and then the third photoresist layer 39 is removed.
그리고, 상기 콘택홀을 포함한 전면에 셀 특성 향상을 위한 플러그 이온주입 공정인 인(P) 이온을 이온주입 한다.Then, phosphorus (P) ions, which are plug ion implantation processes for improving cell characteristics, are implanted on the entire surface including the contact hole.
그러나 종래의 반도체 소자의 제조 방법은 플러그 콘택홀을 형성한 후 플러그 이온주입 공정을 실시하므로 플러그 에스에이시(Self-Aligned-Contact:SAC) 식각 시의 프로파일(Profile)에 의해 이온주입 면적이 결정되며 콘택홀 측면의 층간 절연막이 상기 이온주입시 스퍼터링(Sputtering)되어 콘택홀 계면의 특성을 저하시켜 플러그 저항 및 누설 전류가 증가되는 문제점이 있었다.However, in the conventional semiconductor device manufacturing method, since the plug contact hole is formed and the plug ion implantation process is performed, the ion implantation area is determined by the profile of the plug-etching (Self-Aligned-Contact: SAC) etching. In addition, the interlayer insulating layer on the side of the contact hole is sputtered during the ion implantation, thereby decreasing the characteristics of the contact hole interface, thereby increasing the plug resistance and the leakage current.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 셀 영역의 측벽 형성 공정시 사용한 감광막을 마스크로 플러그 이온주입 공정을 실시한 후 플러그 콘택홀을 형성하므로 플러그 저항 및 누설 전류를 감소시키는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and thus, a plug contact hole is formed after a plug ion implantation process is performed using a photosensitive film used in the sidewall formation process of a cell region as a mask, thereby manufacturing a semiconductor device which reduces plug resistance and leakage current. The purpose is to provide a method.
도 1a 내지 도 1e는 종래 기술에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art
도 2a 내지 도 2f는 본 발명의 실시 예에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
31: 반도체 기판 32: 소자 분리 산화막31: semiconductor substrate 32: device isolation oxide film
33: 워드 라인 34: 질화막33: word line 34: nitride film
35: 산화막 36: 제 1 감광막35: oxide film 36: first photosensitive film
37: 제 2 감광막 38: 층간 절연막37: second photosensitive film 38: interlayer insulating film
본 발명의 반도체 소자의 제조 방법은 셀 영역과 주변 영역이 정의된 기판을 마련하는 단계, 상기 기판 상에 절연 막을 개재한 다수개의 워드 라인들을 형성하는 단계, 상기 주변 영역의 각 워드 라인 양측의 기판 상에 제 1 측벽을 형성하는 단계, 상기 주변 영역만을 마스킹 한 후 상기 셀 영역의 각 워드 라인 양측의 기판 상에 상기 제 1 측벽보다 두께가 작은 제 2 측벽을 형성하고 플러그 이온주입 공정을 하는 단계, 상기 플러그 이온주입 공정을 한 전면에 층간 절연막을 형성하는 단계 및 상기 층간 절연막을 선택 식각하여 다수 개의 플러그 콘택홀들을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The method of manufacturing a semiconductor device of the present invention includes the steps of: providing a substrate having a cell region and a peripheral region defined therein, forming a plurality of word lines through an insulating film on the substrate; and substrates on both sides of each word line of the peripheral region. Forming a first sidewall on the substrate, and after masking only the peripheral region, forming a second sidewall having a smaller thickness than the first sidewall on a substrate on each side of each word line of the cell region and performing a plug ion implantation process And forming an interlayer insulating film on the entire surface of the plug ion implantation process, and forming a plurality of plug contact holes by selectively etching the interlayer insulating film.
상기와 같은 본 발명에 따른 반도체 소자의 제조 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention as follows.
도 2a 내지 도 2f는 본 발명의 실시 예에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도이다.2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
본 발명의 실시 예에 따른 반도체 소자의 제조 방법은 도 2a에서와 같이, 소자 분리 영역에 형성된 소자 분리 산화막(32)을 포함하며 셀 영역과 주변 영역이 정의된 반도체 기판(31)상에 절연 막을 개재하며 캡 절연 막을 구비한 다수개의 워드 라인(33)을 형성한다.A method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention includes an isolation layer 32 formed in an isolation region as shown in FIG. 2A, and an insulating layer is formed on a semiconductor substrate 31 in which a cell region and a peripheral region are defined. Interposed and forming a plurality of word lines 33 having a cap insulating film.
그리고, 상기 워드 라인(33)들을 포함한 반도체 기판(31)상에 질화막(34)과 산화막(35)을 형성한다.The nitride film 34 and the oxide film 35 are formed on the semiconductor substrate 31 including the word lines 33.
도 2b에서와 같이, 상기 산화막(35)상에 제 1 감광막(36)을 도포하고, 상기 제 1 감광막(36)을 상기 셀 영역에만 남도록 선택적으로 노광 및 현상한다.As shown in FIG. 2B, a first photosensitive film 36 is coated on the oxide film 35, and the first photosensitive film 36 is selectively exposed and developed to remain only in the cell region.
그리고, 상기 선택적으로 노광 및 현상된 상기 제 1 감광막(36)을 마스크로 상기 주변 영역의 산화막(35)과 질화막(34)을 에치 백하여 상기 주변 영역의 각 워드 라인(33) 양측의 반도체 기판(31)상에 700 ∼ 900Å 두께의 제 1 측벽(S)을 형성한다.The semiconductor substrate on both sides of each word line 33 of the peripheral area is etched back by etching the oxide film 35 and the nitride film 34 of the peripheral area using the selectively exposed and developed first photosensitive film 36 as a mask. A first sidewall S having a thickness of 700 to 900 mm is formed on the 31.
도 2c에서와 같이, 상기 제 1 감광막을 제거한 후, 상기 제 1 측벽(S)을 포함한 전면에 제 2 감광막(37)을 도포한다.As shown in FIG. 2C, after removing the first photoresist layer, the second photoresist layer 37 is coated on the entire surface including the first sidewall S. Referring to FIG.
그리고, 상기 제 2 감광막(37)을 상기 주변 영역에만 남도록 선택적으로 노광 및 현상한다.Then, the second photosensitive film 37 is selectively exposed and developed so as to remain only in the peripheral region.
이어, 상기 선택적으로 노광 및 현상된 상기 제 2 감광막(37)을 마스크로 상기 셀 영역의 산화막(35)을 질화막과 산화막간의 식각 선택비를 갖는 등방성 건식 식각 방법에 의해 제거한 후, 상기 셀 영역의 질화막(34)을 에치 백하여 상기 각 워드 라인(33) 양측의 반도체 기판(31)상에 300 ∼ 500Å 두께의 제 2 측벽(S2)을 형성한다.Subsequently, the oxide film 35 of the cell region is removed by the isotropic dry etching method having an etching selectivity between the nitride film and the oxide film using the selectively exposed and developed second photosensitive film 37 as a mask. The nitride film 34 is etched back to form a second sidewall S2 having a thickness of 300 to 500 상 에 on the semiconductor substrate 31 on each side of the word line 33.
도 2d에서와 같이, 상기 제 2 감광막(37)을 포함한 전면에 셀 특성 향상을 위한 플러그 이온주입 공정인 인 이온을 이온주입 한다.As shown in FIG. 2D, phosphorus ions, which are plug ion implantation processes for improving cell characteristics, are implanted onto the entire surface including the second photosensitive layer 37.
여기서, 상기 플러그 이온주입 공정 시 플러그 저항 및 누설 전류가 감소되도록 상기 인 이온의 농도 및 에너지를 조절한다.Here, the concentration and energy of the phosphorus ion are adjusted to reduce plug resistance and leakage current during the plug ion implantation process.
또는 상기 플러그 이온으로 인 이온, 인 이온 이외의 도너(Donor) 이온을 사용 또는 혼용한 멀티(Multi) 농도 및 멀티 에너지를 사용하여 상기 플러그 이온주입 공정을 하므로 상기 반도체 기판(31)에서의 n형 도핑(Doping) 농도를 높이고 셀 접합에서의 전기장을 완화시키도록 한다.Alternatively, the plug ion implantation process may be performed using phosphorus ions, donor ions other than phosphorus ions as the plug ions, or by using a multi-concentration and multi-energy mixed with the n-type in the semiconductor substrate 31. Increase the doping concentration and relax the electric field at the cell junction.
이때, 상기 이온주입 시 20 ∼ 30keV 또는 70 ∼ 80keV의 에너지 그리고 0.5 ∼ 3E13/㎠의 농도를 사용한다.At this time, the ion implantation uses energy of 20 to 30 keV or 70 to 80 keV and a concentration of 0.5 to 3E13 / cm 2.
도 2e에서와 같이, 상기 제 2 감광막(37)을 제거한 다음, 상기 제 2 측벽(S2)을 포함한 전면에 층간 절연막(38)을 형성하고 플로우한다.As shown in FIG. 2E, after removing the second photoresist layer 37, an interlayer insulating layer 38 is formed and flows on the entire surface including the second sidewall S2.
도 2f에서와 같이, 상기 층간 절연막(38)상에 제 3 감광막을 도포한 후, 상기 제 3 감광막을 플러그 콘택이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 2F, after applying a third photoresist film on the interlayer insulating film 38, the third photoresist film is selectively exposed and developed to be removed only at a portion where a plug contact is to be formed.
그리고, 상기 선택적으로 노광 및 현상된 상기 제 3 감광막을 마스크로 상기 층간 절연막(38)을 선택적으로 식각하여 콘택홀을 형성한 후, 상기 제 3 감광막(39)을 제거한다.The interlayer insulating layer 38 is selectively etched using the selectively exposed and developed third photoresist layer to form a contact hole, and then the third photoresist layer 39 is removed.
본 발명의 반도체 소자의 제조 방법은 셀 영역의 측벽 형성 공정시 사용한 감광막을 마스크로 사용하여 추가적인 공정 없이 플러그 이온주입 공정을 셀 영역에만 실시한 후 플러그 콘택홀을 형성하므로, 종래 기술보다 이온주입 면적이 넓으며 상기 플러그 이온주입 공정 후 층간 절연막을 형성하기 때문에 플러그 콘택홀측면의 층간 절연막이 스퍼터링되지 않아 콘택홀 계면의 특성 저하를 방지하고 상기 플러그 이온주입 공정 후 트랜지스터의 소오스/드레인 불순물 영역 형성 공정 및 층간 산화막의 플로우 공정 시 사용한 열처리 공정에 의해 상기 플러그 이온이 종래 기술보다 더 활성화되는 등에 의해 누설 전류 감소로 디램의 리프레쉬(Refresh) 특성을 향상시키고 또는 플러그 저항의 저하로 셀 전류가 증가되기 때문에 소자의 집적화에 따른 협소 폭 효과에 의한 셀 트랜지스터의 전류 감소를 보상하여 디램의 읽기/쓰기 특성을 향상시키므로 소자의 특성, 신뢰성 및 수율을 향상시키는 효과가 있다.In the method of manufacturing a semiconductor device of the present invention, the plug contact hole is formed after the plug ion implantation process is performed only in the cell region without the additional process by using the photoresist film used in the sidewall formation process of the cell region as a mask. Since the interlayer insulating film is formed after the plug ion implantation process, the interlayer insulating film on the side of the plug contact hole is not sputtered to prevent deterioration of the characteristics of the contact hole interface, and the source / drain impurity region forming process of the transistor after the plug ion implantation process; and Since the plug ion is more activated than the prior art by the heat treatment process used in the flow process of the interlayer oxide film, the refresh current of the DRAM is improved by reducing the leakage current, or the cell current is increased by the decrease of the plug resistance. Narrow due to integration Improving the read / write characteristics of the dynamic random access memory by compensating for the reduced electric current of the cell transistor due to the effect because the effect of improving the characteristics of the element, reliability and yield.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06151580A (en) * | 1992-11-12 | 1994-05-31 | Sony Corp | Manufacture of semiconductor device |
| JPH07106432A (en) * | 1993-10-05 | 1995-04-21 | Matsushita Electric Ind Co Ltd | Semiconductor device and fabrication thereof |
| JPH07169849A (en) * | 1993-12-16 | 1995-07-04 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH10326838A (en) * | 1997-03-28 | 1998-12-08 | Matsushita Electron Corp | Semiconductor device and its production |
| JPH11186520A (en) * | 1997-12-22 | 1999-07-09 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06151580A (en) * | 1992-11-12 | 1994-05-31 | Sony Corp | Manufacture of semiconductor device |
| JPH07106432A (en) * | 1993-10-05 | 1995-04-21 | Matsushita Electric Ind Co Ltd | Semiconductor device and fabrication thereof |
| JPH07169849A (en) * | 1993-12-16 | 1995-07-04 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH10326838A (en) * | 1997-03-28 | 1998-12-08 | Matsushita Electron Corp | Semiconductor device and its production |
| JPH11186520A (en) * | 1997-12-22 | 1999-07-09 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
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