KR100325286B1 - Method for fabricating semiconductor memory device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor memory device is provided to reduce a chip area by forming a bitline on the side surface of a silicon pillar, and to guarantee an overlay margin by forming a capacitor node electrode on the side surface of an impurity region and a node contact on the capacitor node electrode. CONSTITUTION: The first insulation layer and an impurity-containing layer are sequentially formed on a substrate and are patterned to be a line type. Epitaxial silicon grows on the exposed substrate. Impurity ions are diffused from the impurity-containing layer to the epitaxial silicon layer to form the impurity region(24). The epitaxial silicon layer is patterned to form the silicon pillar(23). The second insulation layer is formed and etched back to expose the silicon pillar. A predetermined thickness of the second insulation layer is etched. A conductive material is deposited and etched back to form the bitline(26) and the capacitor node electrode(27) on both side surfaces of the exposed silicon pillar. The third insulation layer(28) is formed and etched back to expose the silicon pillar. A gate insulation layer(29) and a conductive layer for a gate electrode(30) are sequentially formed on the silicon pillar and are patterned to form the gate electrode perpendicular to the bitline and the capacitor node electrode. The capacitor node electrode is selectively etched to form a node electrode separation region(32). The fourth insulation layer(31) is formed and selectively etched to form the node contact(33) exposing the capacitor node electrode.

Description

Semiconductor Memory Device Manufacturing Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a highly integrated DRAM cell.

In FIG. 1, a conventional DRAM cell manufacturing method is shown according to a process sequence.

As shown in FIG. 1A, an oxide film 1 and a cut film 2 are sequentially formed on the silicon substrate 4, and then patterned so as to remain only on the active region through a photolithography process.

Subsequently, as shown in FIG. 1 (b), an oxidation process is performed to form the field oxide film 13 on the device isolation region, and then the nitride film and the oxide film are removed, and then the gate oxide film 5 and the conductive layer for the gate electrode 6 are removed. Are formed in sequence and patterned into a gate electrode pattern through a photolithography process.

Next, as shown in FIG. 1C, an ion implantation process is performed to form an n-type impurity region 9, an oxide film 7 is formed on the entire surface, and the oxide film 7 is selectively etched to form a bit line. A bitline contact 10 for the connection is formed. Subsequently, a conductive material is deposited on the entire surface of the substrate, and then patterned by a photolithography process to form a bit line 8 connecting the n-type impurity region 9 through the bit line contact 10.

Subsequently, after forming the oxide layer 11 again on the front surface of the substrate as shown in FIG. 1 (d), the oxide layer 11 is selectively etched to form a node contact 13 for connecting a capacitor, and then a conductive material is deposited on the front surface, which is then etched. The capacitor node electrode 13 is formed by patterning by the process.

In the prior art, since the bit line and the capacitor node electrode are formed at the left and right sides of the gate electrode, there is a problem that the chip area is increased, which is disadvantageous for high integration.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a semiconductor memory device suitable for manufacturing a highly integrated DRAM cell.

The semiconductor memory device manufacturing method of the present invention for achieving the above object is a step of sequentially forming a film containing a first insulating film and an impurity on a semiconductor substrate, and the film containing the impurity and the first insulating film through a photolithography process Forming an impurity region by diffusing the impurity ions from the film containing the impurity into the epitaxial silicon layer by performing a patterning process in a line shape, growing epitaxial silicon on an exposed semiconductor substrate, and heat treatment. Forming a silicon pillar by patterning the epitaxial silicon layer by a photolithography process; forming a second insulating film on the entire surface of the substrate; and exposing the surface of the silicon pillar by etching back the second insulating film. Etching the second insulating film to a predetermined thickness and leaving a predetermined thickness; depositing a conductive material on the entire surface of the substrate The process includes: etching back the conductive material layer to form bit lines and capacitor node electrodes on both sides of the exposed impurity regions of the silicon pillar, forming a third insulating layer on the entire surface of the substrate, and etching back the third insulating layer. Exposing the surface of the silicon pillar to form a gate insulating film and a conductive layer for forming a gate electrode on the silicon pillar, and patterning the gate electrode forming conductive layer and the gate insulating film to form the bit line and the capacitor node electrode. Forming a gate electrode having a shape orthogonal to the gate electrode; forming a node electrode isolation region by selectively etching the capacitor node electrode; forming a fourth insulating layer on the entire surface of the substrate; and selectively etching the fourth insulating layer Thereby forming a node contact exposing the capacitor node electrode.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 shows a method of manufacturing a semiconductor memory device according to the present invention in cross section and in layout according to a process sequence.

First, as shown in FIG. 2 (a), the first oxide film 21 as the first insulating film 21 and the PSG (Phodphosilicate Glass) film 22, which is a film containing impurities, are sequentially deposited on the silicon substrate 20, followed by photolithography. Patterned in the form of lines through the process. Next, after the epitaxial silicon 23 is grown on the exposed silicon substrate, an annealing process is performed to diffuse the impurity ions from the PSG film 22 into the epitaxial silicon layer 23 so as to form the n-type impurity region 24. To form.

Next, as shown in FIG. 2 (b), the epitaxial silicon layer 23 is etched using a photomask in a line orthogonal to the line epitaxial silicon layer 23, and then the PSG film and The oxide film is removed to form the silicon pillars 23.

Subsequently, as shown in FIG. 2C, a second insulating layer 25 is formed on the entire surface of the substrate on which the silicon pillars 23 are formed, for example, and then edge-backed to expose the surface of the silicon pillars 23. After the planarization, the second oxide film 25 is etched by a predetermined thickness using a line-shaped photomask used for patterning the first oxide film 21 of FIG. Subsequently, polysilicon is deposited, and then etched back to form polysilicon sidewalls on both sides of the n-type impurity region 24 of the exposed silicon pillar 23 to simultaneously form the bit line 26 and the capacitor node electrode 27. do.

Next, as shown in FIG. 2 (d), a third oxide film 28 is formed on the entire surface of the substrate, for example, and then etched back to expose the surface of the silicon pillar 23, followed by a gate oxide film 29 and A conductive layer 30 for forming a gate electrode is formed and patterned through a photolithography process to form a gate electrode 30 having a shape perpendicular to the polysilicon sidewall.

Subsequently, the capacitor node electrode 27 formed of the polysilicon sidewall as shown in FIG. 2E is selectively etched using a photomask pattern as shown in the layout of FIG. After forming 32, a fourth oxide film 31, for example, is formed on the entire surface, so that the node electrode isolation region 32 is filled with an oxide film.

Next, as shown in FIG. 2 (f), the fourth oxide film 32 is selectively etched to form a node contact 33 exposing the capacitor node electrode 27.

3 shows the final layout of the DRAM cell of the present invention.

As described above, according to the present invention, since the bit line is formed on the side of the silicon pillar, the chip area can be reduced, and the overlay margin is formed by forming the capacitor node electrode on the side of the impurity region and forming the node contact thereon. Can be secured. In addition, since the silicon pillar is used, the device isolation process can be omitted, and thus device characteristics are improved.

1 is a process flowchart showing a conventional DRAM cell manufacturing method.

2 is a process flowchart showing the DRAM cell manufacturing method of the present invention.

3 is a DRAM cell layout diagram of the present invention.

* Description of the symbols for the main parts of the drawings *

20. Semiconductor substrate 21. First insulating film

22. Membranes Containing Impurities 23. Silicon Columns

24. Impurity region 25. Second insulating film

26. Bit line 27. Capacitor node electrode

28. Third insulating film 29. Gate insulating film

30. Gate electrode 31. Fourth insulating film

32. Node electrode separation area 33. Node contact

Claims (1)

A step of sequentially forming a first insulating film and a film containing impurities on the semiconductor substrate; Patterning the impurity-containing film and the first insulating film in a line form through a photolithography process; Growing epitaxial silicon on the exposed semiconductor substrate, Performing an annealing process to diffuse the impurity ions from the film containing the impurity into the epitaxial silicon layer to form an impurity region; Forming a pillar of silicon by patterning the epitaxial silicon layer by a photolithography process; Forming a second insulating film over the entire substrate, Etching back the second insulating layer to expose the surface of the silicon pillar; Etching the second insulating film to a predetermined thickness and leaving a predetermined thickness; Depositing a conductive material on the entire surface of the substrate, Etching back the conductive material layer to form bit lines and capacitor node electrodes on both sides of the impurity regions of the exposed silicon pillars; Forming a third insulating film over the entire substrate, Etching back the third insulating film to expose a surface of a silicon pillar; Sequentially forming a gate insulating film and a conductive layer for forming a gate electrode on the silicon pillar, Patterning the gate electrode conductive layer and the gate insulating layer to form a gate electrode orthogonal to the bit line and the capacitor node electrode; Selectively etching the capacitor node electrode to form a node electrode isolation region; Forming a fourth insulating film over the entire substrate, and Selectively etching the fourth insulating layer to form a node contact exposing the capacitor node electrode.