KR100315454B1 - Inter-metal dielectric layer planarization method of semiconductor devices - Google Patents
Inter-metal dielectric layer planarization method of semiconductor devices Download PDFInfo
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- KR100315454B1 KR100315454B1 KR1019990052170A KR19990052170A KR100315454B1 KR 100315454 B1 KR100315454 B1 KR 100315454B1 KR 1019990052170 A KR1019990052170 A KR 1019990052170A KR 19990052170 A KR19990052170 A KR 19990052170A KR 100315454 B1 KR100315454 B1 KR 100315454B1
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- insulating film
- interlayer insulating
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 71
- 239000002184 metal Substances 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000010408 film Substances 0.000 claims abstract description 87
- 239000010410 layer Substances 0.000 claims abstract description 58
- 239000011229 interlayer Substances 0.000 claims abstract description 45
- 239000010409 thin film Substances 0.000 claims abstract description 44
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 38
- 239000010703 silicon Substances 0.000 claims abstract description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000013078 crystal Substances 0.000 claims abstract description 30
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 238000000137 annealing Methods 0.000 claims abstract description 8
- -1 silicon ions Chemical class 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000005468 ion implantation Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 abstract description 15
- 238000007517 polishing process Methods 0.000 abstract description 14
- 230000004888 barrier function Effects 0.000 abstract description 9
- 238000005530 etching Methods 0.000 abstract description 4
- 238000001465 metallisation Methods 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000007872 degassing Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
지역적 평탄화를 위한 SOG, USG 등의 매입 공정 및 화학 기계적 연마 공정을 생략할 수 있는 반도체 소자의 층간 절연막 평탄화 방법에 관한 것으로, 평탄화된 하부 층간 절연막 상부에 실리콘 이온을 주입하고 어닐링하여 씨 결정층을 형성하고, 씨 결정층이 형성된 하부 층간 절연막의 선택적 영역에 비아를 형성하며, 비아를 포함한 씨 결정층 상부 전면에 금속 박막을 증착하고 패터닝하여 금속 박막 패턴을 형성한다. 이후, 금속 박막 패턴 사이의 갭에 드러난 씨 결정층 상부에 에피택셜 실리콘을 성장시켜 갭을 매입하고, 에피택셜 실리콘을 포함한 금속 박막 상부 전면에 상부 층간 절연막을 증착한다. 이렇게 함으로써 갭 매입을 위해 사용했던 수분 함량이 많은 SOG, USG 등의 사용을 생략하여 비아 식각 후 베리어 메탈 증착에서 디가싱시 지역적 평탄화를 위해 사용되는 SOG, USG 등에서 발생하는 수분 등에 의해 베리어 메탈 증착이 제대로 되지않아 비아 저항이 높아지는 문제를 원천적으로 방지할 수 있으며, 화학 기계적 연마 공정을 생략할 수 있어 화학 기계적 연마 공정에 의해 증착된 산화막이 찢겨 나가거나, 공정의 균일도 문제에 따른 비아의 선폭 변화 및 비아 저항의 증가 문제를 원천적으로 방지할 수 있다.The present invention relates to a method of planarizing an interlayer insulating film of a semiconductor device capable of omitting a buried process such as SOG and USG for local planarization, and a chemical mechanical polishing process. The seed crystal layer is formed by implanting and annealing silicon ions on the planarized lower interlayer insulating film. A via is formed in a selective region of the lower interlayer insulating layer on which the seed crystal layer is formed, and a metal thin film pattern is formed by depositing and patterning a metal thin film on the entire top surface of the seed crystal layer including the via. Thereafter, epitaxial silicon is grown on the seed crystal layer exposed in the gap between the metal thin film patterns to fill the gap, and an upper interlayer insulating film is deposited on the entire upper surface of the metal thin film including the epitaxial silicon. This eliminates the use of SOG, USG, etc., which has a lot of moisture content used for gap filling, and deposits barrier metal by moisture generated in SOG, USG, etc., used for local planarization during barrier metal deposition after via etching. This prevents the problem of high via resistance due to the inadequate, and omits the chemical mechanical polishing process, so that the oxide film deposited by the chemical mechanical polishing process is torn off or the line width change due to the uniformity of the process. And the problem of increasing the via resistance can be prevented at the source.
Description
본 발명은 반도체 소자를 제조하는 공정에 관한 것으로, 더욱 상세하게는 반도체 집적 회로에서의 배선을 다층화하여 기판 내에 배치된 각 소자간의 조합에 자유도를 주어 고밀도의 반도체 소자를 제조할 경우 각 배선 사이의 전기적 절연을 위한 층간 절연막을 평탄화하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing a semiconductor device, and more particularly, to fabricate a semiconductor device having a high degree of freedom by fabricating a multilayered wiring in a semiconductor integrated circuit and giving a degree of freedom to the combination between the devices disposed in the substrate. A method of planarizing an interlayer insulating film for electrical insulation.
일반적으로 반도체 소자의 제조 공정에서 실리콘웨이퍼 상에 1층만의 배선을 형성하는 경우에는 배선 패턴 설계상의 자유도가 작아 실질적인 배선이 길어짐으로써 웨이퍼 내 반도체 소자의 레이아웃에도 큰 제약이 가해진다.In general, when only one layer of wiring is formed on a silicon wafer in the manufacturing process of a semiconductor device, the degree of freedom in design of the wiring pattern is small, so that the actual wiring is lengthened, thereby greatly limiting the layout of the semiconductor device in the wafer.
이것에 반해서 금속 배선을 다층화하면 아주 효율이 높은 설계가 가능하다. 즉, 반도체 칩 위에 배선을 통과시키는 스페이스를 고려하지 않고 각 반도체 소자가 레이아웃되기 때문에 집적도 및 밀도가 향상되어 반도체 칩 사이즈를 축소할 수있다. 그리고, 배선의 자유도가 증가하고, 패턴 설계가 용이해짐과 함께 배선 저항이나 전류 용량 등의 설정을 여유를 가지고 할 수 있게 된다.On the other hand, multi-layered metal wiring enables a highly efficient design. That is, since each semiconductor element is laid out without considering the space for allowing wiring to pass on the semiconductor chip, the degree of integration and density can be improved and the size of the semiconductor chip can be reduced. This increases the degree of freedom in wiring, facilitates pattern design, and allows setting of wiring resistance, current capacity, and the like with a margin.
이러한 금속 배선의 다층화에서는 금속 배선층과 금속 배선층 사이의 전기적 절연을 위한 층간 절연막 표면의 요곡이 심해짐에 따라 표면에서의 배선의 오픈이나 쇼트 등이 발생하게 되는 데, 이를 방지하기 위하여 층간 절연막을 평탄화하고 있다.In the multilayering of the metal wiring, as the curvature of the interlayer insulating film surface for electrical insulation between the metal wiring layer and the metal wiring layer becomes deep, opening or shorting of the wiring on the surface occurs, and the interlayer insulating film is planarized to prevent this. Doing.
그리고, 층간 절연막의 평탄화를 위하여 금속 배선층 형성을 위한 금속 박막 패턴이 형성된 하부 박막 상부에 PE-TEOS(plasma enhanced tetraethylorthosilicate) 또는 HDP(high density plasma) 방법으로 평탄화 정도가 양호한 산화막을 형성하여 층간 절연막을 형성하고 있다.In order to planarize the interlayer insulating film, an oxide film having a good leveling degree is formed by using plasma enhanced tetraethylorthosilicate (PE-TEOS) or high density plasma (HDP) method on the lower thin film on which the metal thin film pattern for forming the metal wiring layer is formed. Forming.
이중, 층간 절연막을 PE-TEOS 방법에 의한 산화막으로 형성하는 경우에는 콘택(contact) 또는 비아(via)가 형성된 하부 절연막 상부에 금속 박막을 증착하고 패터닝(patterning)하여 금속 배선층을 형성한 후, 금속 박막 패턴을 포함한 하부 절연막 상부에 PE-TEOS 방법에 의해 산화막을 증착한다. 그리고, 금속 박막 패턴에 의한 지역적인 단차를 최소화하기 위하여 각 금속 박막 패턴 사이의 갭(gap)에 SOG(spin on glass), USG(un-doped silicate glass) 등을 매입한다. 그 다음 하부 절연막 상부 전면에 재차 PE-TEOS 방법에 의해 산화막을 증착하고 화학 기계적 연마 공정(chemical mechanical polishing)에 의해 평탄화함으로써 층간 절연막을 완성한다. 그러나, PE-TEOS 방법에 의한 산화막을 이용하여 층간 절연막을 형성하는 경우에는 지역적인 평탄화를 위하여 수분 함량이 높은 SOG, USG 등을 각 금속 박막패턴 사이 갭에 매입하는 공정이 추가되어지며, 후속 비아 홀 식각 후 베리어 메탈(barrier metal) 증착에서 디가싱(de-gashing) 공정 진행시 SOG, USG 등에서 발생하는 수분 등에 의해 베리어 메탈이 제대로 증착되지 않아 비아 저항이 높게 되는 단점이 있다.In the case where the interlayer insulating film is formed of an oxide film by the PE-TEOS method, a metal thin film is deposited and patterned on the lower insulating film on which the contact or via is formed to form a metal wiring layer, and then the metal An oxide film is deposited on the lower insulating film including the thin film pattern by PE-TEOS method. In addition, in order to minimize local steps due to the metal thin film pattern, a spin on glass (SOG), an un-doped silicate glass (USG), or the like is embedded in a gap between the metal thin film patterns. Then, an oxide film is deposited on the entire upper surface of the lower insulating film by PE-TEOS method and planarized by chemical mechanical polishing to complete the interlayer insulating film. However, in the case of forming an interlayer insulating film using an oxide film by PE-TEOS method, a step of embedding SOG, USG, etc., which has a high moisture content, into the gap between the metal thin film patterns for local planarization is added. After the hole etching, the barrier metal is not properly deposited by moisture generated in SOG, USG, etc. during the de-gashing process in the deposition of barrier metal, resulting in a high via resistance.
또한, 층간 절연막을 HDP 방법을 이용한 산화막으로 형성하는 경우에는 콘택 또는 비아가 형성된 하부 절연막 상부에 금속 박막을 증착하고 패터닝하여 금속 배선층을 형성한 후, 금속 박막 패턴을 포함한 하부 절연막 상부 전면에 HDP 방법에 의해 갭 매입 능력이 우수한 산화막을 증착하고 화학 기계적 연마 공정에 의해 평탄화함으로써 층간 절연막을 완성한다. 따라서, HDP 방법에 의한 산화막을 이용하여 층간 절연막을 형성하는 경우에는 HDP 방법에 의한 산화막이 갭 매입 능력이 우수하므로 PE-TEOS 방법에 의한 산화막을 이용하는 데 있어서 지역적 평탄화를 위한 SOG, USG 등의 매입 공정을 생략할 수 있으며, 후속 비아 홀 식각 후 베리어 메탈 증착시 디가싱 공정에 의해 SOG, USG 등에서 발생되는 수분에 의한 제반 문제점을 방지할 수 있는 이점이 있다.In addition, when the interlayer insulating film is formed of an oxide film using the HDP method, a metal thin film is formed by depositing and patterning a metal thin film on the lower insulating film on which the contact or via is formed, and then forming the metal wiring layer on the entire upper surface of the lower insulating film including the metal thin film pattern. Thereby depositing an oxide film having excellent gap embedding capability and planarization by a chemical mechanical polishing process to complete the interlayer insulating film. Therefore, when the interlayer insulating film is formed by using the oxide film by the HDP method, the oxide film by the HDP method has a good gap embedding ability, so that SOG, USG, etc. for local planarization are used for the oxide film by the PE-TEOS method. The process can be omitted, there is an advantage that can prevent all problems caused by moisture generated in SOG, USG, etc. by the degassing process during the deposition of the barrier metal after the subsequent via hole etching.
그러나, 이와 같은 PE-TEOS, HDP 방법에 의한 산화막을 이용하여 층간 절연막을 형성할 경우에는 산화막의 증착 후 평탄화를 위해 화학 기계적 연마 공정을 수행하게 된다. 따라서 화학 기계적 연마 공정 중 증착된 PE-TEOS, HDP 방법에 의해 증착된 산화막이 찢겨 나가거나, 화학 기계적 연마 공정의 균일성 문제에 따른 후속 비아의 선폭(critical dimension, CD) 문제 및 비아 저항의 증가 문제 등이 발생하게 되는 단점이 있다.However, when the interlayer insulating film is formed using the oxide film by PE-TEOS, HDP method, a chemical mechanical polishing process is performed to planarize after deposition of the oxide film. Therefore, the oxide film deposited by the PE-TEOS and HDP method deposited during the chemical mechanical polishing process is torn off, or the subsequent via's critical dimension (CD) problem and the via resistance increase due to the uniformity problem of the chemical mechanical polishing process. There is a disadvantage that problems occur.
본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 그 목적은 지역적 평탄화를 위한 SOG, USG 등의 매입 공정 및 화학 기계적 연마 공정을 생략할 수 있는 반도체 소자의 층간 절연막 평탄화 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to provide a method for planarizing an interlayer insulating film of a semiconductor device capable of omitting an embedding process such as SOG and USG, and a chemical mechanical polishing process for local planarization.
도 1a 내지 도 1e는 본 발명의 일 실시예에 따라 반도체 소자의 층간 절연막을 평탄화하는 방법을 개략적으로 도시한 공정도이다.1A to 1E are process diagrams schematically illustrating a method of planarizing an interlayer insulating film of a semiconductor device according to an exemplary embodiment of the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 절연막 상에 실리콘 이온 주입과 어닐링을 통해 에피택셜 실리콘 성장을 위한 씨 결정층(seed layer)을 형성한 후, 그 상부에 금속 박막 패턴을 형성하고, 선택적 에피택셜 성장에 의해 씨 결정층이 드러난 금속 박막 패턴 사이의 갭에 에피택셜 실리콘을 금속 박막 패턴의 높이만큼 성장시킨 다음, 층간 절연막을 평탄화는 것을 특징으로 한다.In order to achieve the above object, the present invention after forming a seed layer for epitaxial silicon growth through silicon ion implantation and annealing on the insulating film, to form a metal thin film pattern thereon, The epitaxial silicon is grown by the height of the metal thin film pattern in the gap between the metal thin film patterns where the seed crystal layer is exposed by selective epitaxial growth, and then the interlayer insulating film is planarized.
그리고, 이와 같이 에피택셜 실리콘에 의해 금속 박막 패턴 사이의 갭을 매입하여 평탄화함으로써 증착되는 층간 절연막이 별도의 공정없이 평탄화되어 종래와 같은 화학 기계적 연마 공정을 생략하여 그에 따라 발생되는 각종 문제점을 방지할 수 있게 되며, 종래와 같이 갭 매입을 위한 수분 함량이 많은 SOG, USG 등의 사용을 생략하여 수분 발생에 따른 각종 문제점을 방지할 수 있게 된다.As such, the interlayer insulating film deposited by filling and planarizing the gap between the metal thin film patterns by the epitaxial silicon is flattened without a separate process, thereby avoiding various problems caused by omitting the conventional chemical mechanical polishing process. It will be possible to avoid various problems caused by the generation of moisture by omitting the use of SOG, USG, etc., which have a high moisture content for gap filling as in the prior art.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 일 실시예에 따라 반도체 소자의 층간 절연막을 평탄화하는 방법을 개략적으로 도시한 공정도이다.1A to 1D are process diagrams schematically illustrating a method of planarizing an interlayer insulating layer of a semiconductor device according to an exemplary embodiment of the present invention.
먼저 도 1a에 도시한 바와같이, 반도체 소자가 형성된 반도체 기판과 금속배선층을 전기적으로 절연하기 위한 BPSG(borophosphosilicate glass) 등으로 이루어진 절연막(2)을 평탄화하고, 반도체 기판(1)의 소자 전극과 금속 배선층을 전기적으로 접속하기 위한 콘택(3)을 선택적 영역에 형성한 다음, 콘택(3)을 포함한 절연막(2) 상부 전면에 PE-TEOS, HDP 등의 방법에 의해 산화막을 일정한 두께로 증착한다. 그리고, 이온 주입 공정에 의해 산화막에 실리콘(Si) 이온을 주입하고 어닐링(annealing)하여 에피택셜(epitaxial) 성장을 위한 씨 결정층(seed layer)(4)을 형성한다. 이때, 이와는 달리 절연막(2) 상부에 산화막을 증착하고 실리콘 이온 주입 및 어닐링을 통해 씨 결정층(4)을 형성한 후 콘택(3)을 형성할 수 있으며, 절연막(2) 상부에 산화막을 증착하고 콘택(3)을 형성한 후 실리콘 이온 주입 및 어닐링을 통해 씨 결정층(4)을 형성할 수도 있다. 또한, 씨 결정층(4) 형성을 위한 별도의 산화막 증착없이 BPSG 등의 절연막 상부에 직접적으로 실리콘 이온을 주입하고 어닐링함으로써 씨 결정층(4)을 형성할 수도 있다.First, as shown in FIG. 1A, the insulating film 2 made of borophosphosilicate glass (BPSG) or the like for electrically insulating the semiconductor substrate on which the semiconductor element is formed and the metal wiring layer is planarized, and the element electrode and the metal of the semiconductor substrate 1 are planarized. A contact 3 for electrically connecting the wiring layer is formed in an optional region, and then an oxide film is deposited on the entire upper surface of the insulating film 2 including the contact 3 by a method such as PE-TEOS, HDP, etc. to a constant thickness. Then, silicon (Si) ions are implanted and annealed into the oxide film by an ion implantation process to form a seed layer 4 for epitaxial growth. At this time, an oxide film is deposited on the insulating film 2, the seed crystal layer 4 is formed through silicon ion implantation and annealing, and then a contact 3 is formed, and an oxide film is deposited on the insulating film 2. After the contact 3 is formed, the seed crystal layer 4 may be formed through silicon ion implantation and annealing. In addition, the seed crystal layer 4 may be formed by directly injecting and annealing silicon ions onto an insulating film such as BPSG without separate oxide film deposition for forming the seed crystal layer 4.
그 다음 도 1b에 도시한 바와 같이, 씨 결정층(4)이 형성된 반도체 기판(1) 상부 전면에 금속 배선층 형성을 위한 금속 박막을 형성하고, 패터닝하여 회로 형성을 위한 금속 박막 패턴(5)을 형성한다. 그리고, 선택적 에피택셜 성장법에 의해 금속 박막 패턴(5) 사이의 갭에 에피택셜 실리콘(6)을 성장시킨다. 이때 선택적 에피택셜 성장시 씨 결정층(4)이 드러나지 않은 금속 박막 패턴(5)에서는 에피택셜 실리콘이 성장하지 않으며 씨 결정층(4)이 드러난 금속 박막 패턴(5) 사이의 갭 영역에서만 에피택셜 실리콘(6)이 성장된다. 그리고, 선택적 에피택셜 성장법에 의해 성장되는 에피택셜 실리콘(6)의 성장 높이는 금속 박막 패턴(5)의 높이 만큼 되도록 하며, 에피택셜 실리콘(6) 성장을 위한 선택적 에피택셜 성장은 금속 박막 패턴(5)의 녹는점 이하의 온도로 진행되도록 하는 것이 바람직하다.1B, a metal thin film for forming a metal wiring layer is formed on the entire upper surface of the semiconductor substrate 1 on which the seed crystal layer 4 is formed, and patterned to form a metal thin film pattern 5 for circuit formation. Form. Then, the epitaxial silicon 6 is grown in the gap between the metal thin film patterns 5 by the selective epitaxial growth method. At this time, in the metal thin film pattern 5 in which the seed crystal layer 4 is not exposed during selective epitaxial growth, epitaxial silicon does not grow and epitaxial only in the gap region between the metal thin film pattern 5 in which the seed crystal layer 4 is exposed. Silicon 6 is grown. In addition, the growth height of the epitaxial silicon 6 grown by the selective epitaxial growth method is equal to the height of the metal thin film pattern 5, and the selective epitaxial growth for the epitaxial silicon 6 growth is performed by the metal thin film pattern ( It is desirable to proceed to a temperature below the melting point of 5).
그 다음 도 1c에 도시한 바와 같이, 금속 박막 패턴(5)과 에피택셜 실리콘(6)에 의해 평탄화된 금속 배선층 상부 전면에 PE-TEOS, HDP 등의 방법에 의해 산화막(7)을 증착하여 금속 배선층과 금속 배선층 사이를 전기적으로 절연하기 위한 층간 절연막을 형성한다. 이때, 산화막(7)에 의해 형성되는 층간 절연막은 종래 PE-TEOS 방식에서 갭 매입을 위한 SOG, USG 등의 형성 공정 대신 에피택셜 실리콘(6)의 성장으로 갭을 매입하므로 수분 함량이 많은 SOG, USG의 이용에 따른 제반 문제점을 원천적으로 방지할 수 있으며, 에피택셜 실리콘(6)에 의한 갭의 매입으로 평탄화된 금속 배선층 상부에 PE-TEOS, HDP 등의 방법으로 산화막을 증착하므로 평탄화된 층간 절연막을 형성할 수 있을 뿐만 아니라 층간 절연막으로 증착되는 산화막이 단순히 증착만으로 평탄화되므로 종래와 같이 평탄화를 위한 화학 기계적 연마 공정을 생략할 수 있어 화학 기계적 연마 공정에 따른 제반 문제점을 원천적으로 방지할 수 있다. 이후, 층간 절연막인 산화막(7) 상부에 이온 주입 공정으로 실리콘 이온을 주입하고 어닐링하여 산화막(7) 상부 표면에 에피택셜 성장을 위한 씨 결정층(8)을 형성한다.Next, as shown in FIG. 1C, the oxide film 7 is deposited on the upper surface of the metal wiring layer planarized by the metal thin film pattern 5 and the epitaxial silicon 6 by PE-TEOS, HDP, or the like to form a metal. An interlayer insulating film for electrically insulating between the wiring layer and the metal wiring layer is formed. At this time, the interlayer insulating film formed by the oxide film 7 is filled with the gap by the growth of the epitaxial silicon 6 instead of the formation process of SOG, USG, etc. for gap filling in the conventional PE-TEOS method SOG, Various problems caused by the use of USG can be fundamentally prevented, and since the oxide film is deposited on the flattened metal wiring layer by PE-TEOS, HDP, etc. by the gap filling by the epitaxial silicon 6, the planarized interlayer insulating film In addition, since the oxide film deposited as the interlayer insulating film is simply flattened by deposition, the chemical mechanical polishing process for planarization may be omitted as in the prior art, and thus, problems inherent in the chemical mechanical polishing process may be prevented. Thereafter, silicon ions are implanted and annealed on the oxide film 7, which is an interlayer insulating film, to form a seed crystal layer 8 for epitaxial growth on the upper surface of the oxide film 7.
그 다음 도 1d에 도시한 바와 같이, 씨 결정층(8)이 형성된 산화막(7)을 선택적으로 식각하여 비아홀을 형성하고, 베리어 메탈(미도시)을 증착하고 텅스텐 플러그를 형성함으로써 금속 배선층과 금속 배선층을 전기적으로 접속하기 위한 비아(9)를 형성한다. 이때, 종래 PE-TEOS 방식에서와는 달리 갭 매입을 위하여 수분 함량이 많은 SOG, USG 등을 사용하지 않으므로 베리어 메탈 증착 공정에서의 디가싱시 수분에 의한 증착 불량 및 그에 따른 비아 저항 증대, 비아 선폭 변화 등의 문제가 발생하지 않는다.Next, as shown in FIG. 1D, the oxide film 7 having the seed crystal layer 8 is selectively etched to form via holes, depositing barrier metal (not shown), and forming a tungsten plug to form a metal wiring layer and a metal. The via 9 for electrically connecting the wiring layer is formed. At this time, unlike in the conventional PE-TEOS method, since SOG, USG, etc., which have a high moisture content, are not used for gap filling, deposition defects due to moisture during the degassing in the barrier metal deposition process, increase in the via resistance, and via line width change accordingly. There is no problem.
그 다음 도 1e에 도시한 바와 같이, 비아(9)가 형성된 층간 절연막인 산화막(7) 상부 전면에 금속 배선층 형성을 위한 금속 박막을 형성하고, 금속 박막 패턴을 패터닝하여 금속 배선층의 회로 형성을 위해 금속 박막 패턴(10)을 형성한다. 그리고, 도 1b에서 설명한 바와 같은 방법으로 선택적 에피택셜 성장법에 의해 금속 박막 패턴(10) 사이의 갭에 에피택셜 실리콘(11)을 성장시킨다. 이후, 금속 박막 패턴(10)과 에피택셜 실리콘(11)에 의해 평탄화된 금속 배선층 상부 전면에 PE-TEOS, HDP 등의 방법에 의해 산화막(12)을 증착하여 금속 배선층과 금속 배선층 사이를 전기적으로 절연하기 위한 층간 절연막을 형성한다Next, as shown in FIG. 1E, a metal thin film for forming a metal wiring layer is formed on the entire upper surface of the oxide film 7, which is an interlayer insulating film having vias 9 formed thereon, and the metal thin film pattern is patterned to form a circuit of the metal wiring layer. The metal thin film pattern 10 is formed. The epitaxial silicon 11 is grown in the gap between the metal thin film patterns 10 by the selective epitaxial growth method by the method described with reference to FIG. 1B. Thereafter, the oxide film 12 is deposited on the entire upper surface of the metal wiring layer planarized by the metal thin film pattern 10 and the epitaxial silicon 11 by PE-TEOS, HDP or the like to electrically connect the metal wiring layer to the metal wiring layer. Forming an interlayer insulating film for insulation
이후, 산화막(12) 상부의 실리콘 이온 주입 및 어닐링을 통한 씨 결정층 형성, 비아 형성, 금속 박막 패턴 형성, 선택적 에피택셜 성장, 층간 절연막 형성 등의 공정을 반복 실시함으로써 평탄화된 층간 절연막을 가진 반도체 소자의 다층 배선을 형성한다.Subsequently, a semiconductor having an interlayer insulating film planarized by repeating a process of forming a seed crystal layer, forming a via, forming a metal thin film pattern, selective epitaxial growth, and forming an interlayer insulating layer through silicon ion implantation and annealing on the oxide layer 12. The multilayer wiring of an element is formed.
그리고, 도 1a 내지 도 1e에 따른 실시예에서는 에피택셜 성장을 위한 씨 결정층을 형성한 후 층간 절연막에 비아를 형성하였지만, 이와는 달리 층간 절연막에 비아를 형성한 후 에피택셜 성장을 위한 씨 결정층을 형성할 수도 있다.In addition, in the embodiment of FIGS. 1A to 1E, after forming the seed crystal layer for epitaxial growth and forming a via in the interlayer insulating film, a via is formed in the interlayer insulating film, and then the seed crystal layer for epitaxial growth is formed. May be formed.
이와 같이 본 발명은 금속 박막 패턴 사이의 갭에 선택적 에피택셜 성장법으로 에피택셜 실리콘을 형성하여 평탄화된 금속 배선층을 형성하는 것으로, 종래 PE-TEOS 방법에서의 금속 박막 패턴 사이의 갭 매입을 위해 사용했던 수분 함량이 많은 SOG, USG 등의 형성 공정을 생략할 수 있어 층간 절연막에 비아 식각 후 베리어 메탈 증착에서 디가싱시 지역적 평탄화를 위해 사용되는 SOG, USG 등에서 발생하는 수분 등에 의해 베리어 메탈 증착이 제대로 되지않아 비아 저항이 높아지는 문제를 원천적으로 방지할 수 있으며, 종래 PE-TEOS, HDP 방법에서의 화학 기계적 연마 공정을 생략할 수 있어 화학 기계적 연마 공정에 의해 증착된 산화막이 찢겨 나가거나, 화학 기계적 연마 공정의 균일도 문제에 따른 비아의 선폭 변화 및 비아 저항의 증가 문제를 원천적으로 방지할 수 있을 뿐만 그에 따라 반도체 소자 제조 공정의 수율을 향상시킬 수 있다.As described above, the present invention forms a planarized metal interconnection layer by forming epitaxial silicon in the gap between the metal thin film patterns by the selective epitaxial growth method, and is used for embedding the gap between the metal thin film patterns in the conventional PE-TEOS method. The formation process of SOG, USG, etc., which has a high moisture content, can be omitted, and barrier metal deposition is caused by moisture generated in SOG, USG, etc., which is used for local planarization when degassing in the barrier metal deposition after via etching on the interlayer insulating film. It is possible to prevent the problem of high via resistance due to improper operation, and to skip the chemical mechanical polishing process in the conventional PE-TEOS and HDP methods, so that the oxide film deposited by the chemical mechanical polishing process is torn off or the chemical mechanical The change in via line width and increase in via resistance due to the uniformity problem of the polishing process Not only you can stop whereby it is possible to improve the yield of manufacturing the semiconductor device process.
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