KR101023073B1 - Method for manufacturing Semiconductor Device - Google Patents

Method for manufacturing Semiconductor Device Download PDF

Info

Publication number
KR101023073B1
KR101023073B1 KR1020080090716A KR20080090716A KR101023073B1 KR 101023073 B1 KR101023073 B1 KR 101023073B1 KR 1020080090716 A KR1020080090716 A KR 1020080090716A KR 20080090716 A KR20080090716 A KR 20080090716A KR 101023073 B1 KR101023073 B1 KR 101023073B1
Authority
KR
South Korea
Prior art keywords
insulating film
film
trench
metal
semiconductor device
Prior art date
Application number
KR1020080090716A
Other languages
Korean (ko)
Other versions
KR20100031872A (en
Inventor
이진규
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080090716A priority Critical patent/KR101023073B1/en
Publication of KR20100031872A publication Critical patent/KR20100031872A/en
Application granted granted Critical
Publication of KR101023073B1 publication Critical patent/KR101023073B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor

Abstract

반도체 소자의 제조 방법이 개시된다. 이 방법은, 반도체 기판상에 절연물질을 증착하여 절연막을 형성하는 단계와, 절연막을 식각하여 절연막 표면을 평탄화하는 단계와, 평탄화된 절연막에 포토리소그래피 공정을 수행하여 트렌치를 형성하는 단계와, 오버 식각된 상기 트렌치를 포함하는 상기 반도체 기판 전면에 금속물질을 증착하되, 상기 오버식각된 트렌치 두께 이상으로 상기 절연막 상에 상기 금속물질을 증착하는 단계와, 절연막이 표면에 드러날 때까지 금속물질을 식각하여 트렌치에 매립된 금속물질을 노출시켜 금속막을 형성하는 단계를 포함하는 것이 바람직하다. 그러므로, 금속막 형성시 오버 식각으로 인하여 발생되는 리세스 현상 및 레지듀의 발생을 방지할 수 있고, 금속막의 저항값을 균일하게 안정시킬 수 있다.Disclosed is a method of manufacturing a semiconductor device. The method includes depositing an insulating material on a semiconductor substrate to form an insulating film, etching the insulating film to planarize the insulating film surface, performing a photolithography process on the planarized insulating film, and forming a trench over Depositing a metal material on the entire surface of the semiconductor substrate including the etched trench, depositing the metal material on the insulating film to the thickness of the over-etched trench, and etching the metal material until the insulating film is exposed on the surface. Thereby exposing the metal material embedded in the trench to form a metal film. Therefore, it is possible to prevent the occurrence of the recess phenomenon and the residue caused by the over etching during the formation of the metal film, and to uniformly stabilize the resistance value of the metal film.

오버 식각, 리세스, 레지듀 Over Etch, Recess, Residue

Description

반도체 소자의 제조방법{Method for manufacturing Semiconductor Device} Method for manufacturing semiconductor device

본 발명은 반도체 소자에 관한 것으로서, 특히 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a method for manufacturing a semiconductor device.

일반적으로 반도체 소자는 미세화, 대용량화 및 고집적화를 위해서 반도체 소자의 트랜지스터, 비트라인 및 커패시터 등을 형성한 다음, 각각의 소자를 전기적으로 연결할 수 있는 금속배선 등과 같은 다층 배선을 형성하기 위한 후속 공정을 필수적으로 요구하고 있다. In general, semiconductor devices require a subsequent process of forming transistors, bit lines, capacitors, and the like of semiconductor devices for miniaturization, high capacity, and high integration, and then forming multi-layered wiring such as metal wirings to electrically connect the respective devices. Is asking.

도 1에 도시된 바와 같이, 반도체 기판(10) 상에 트랜지스터(20), 콘택(40)을 포함한 하부 구조물(5)을 형성하고, 층간절연막(30)을 형성한다. As shown in FIG. 1, a lower structure 5 including a transistor 20 and a contact 40 is formed on a semiconductor substrate 10, and an interlayer insulating film 30 is formed.

층간절연막(30) 상에 절연막(50)을 증착하고, 콘택(40)을 노출시키기 위해 절연막(50)의 일부에 트렌치(trench)를 형성하여, 트렌치에 텅스텐과 같은 금속물질을 매립하고 이를 평탄화하여 금속막(60)을 형성한다. By depositing an insulating film 50 on the interlayer insulating film 30 and forming a trench in a portion of the insulating film 50 to expose the contact 40, a metal material such as tungsten is embedded in the trench and planarized The metal film 60 is formed.

트랜지스터(20), 콘택(40) 및 금속막(60)이 전기적으로 연결될 수 있고, 금속막(60)의 저항값은 절연막(50)의 트렌치에 증착되는 금속막(60)의 두께에 따라 결정되게 된다. The transistor 20, the contact 40, and the metal film 60 may be electrically connected, and the resistance of the metal film 60 is determined according to the thickness of the metal film 60 deposited in the trench of the insulating film 50. Will be.

도 2a 내지 도 2c는 종래 기술에 의해 형성된 반도체 소자의 공정단면도이다. 2A to 2C are process cross-sectional views of a semiconductor device formed by the prior art.

콘택(50)을 포함한 하부구조물(5) 상에 형성된 절연막(50)에 트렌치를 형성하기 위해 절연막(50)의 일부 영역을 식각하는 과정에서 발생된 오버 식각(over etching)으로 인하여 도 2a에 도시된 바와 같은 리세스(recess)를 동반한 토폴로지(topology)가 발생된다. As shown in FIG. 2A due to over etching generated in etching a portion of the insulating film 50 to form a trench in the insulating film 50 formed on the lower structure 5 including the contact 50. A topology with recesses as shown is generated.

따라서, 절연막(50)이 식각됨과 동시에 하부구조물(5)의 일부까지 식각됨으로 인하여 식각된 절연막(50) 상에 금속막(60)을 형성하기 위한 금속 성분(62)을 적층하면, 도 2b에 도시된 바와 같이 금속 성분(62)이 절연막(50)의 높이까지 적층되지 못하고 함몰되게 된다. Therefore, when the insulating film 50 is etched and part of the lower structure 5 is etched, the metal component 62 for forming the metal film 60 is formed on the etched insulating film 50. As shown, the metal component 62 is not stacked to the height of the insulating film 50 and is recessed.

도 2c에 도시된 바와 같은 금속 플러그(70)를 형성하는 경우, 리세스를 동반한 토폴로지가 그대로 남아있기 때문에, 하부구조물(5)이 오버 식각된 트렌치의 상부에 형성된 금속 플러그(72)는 절연막(50) 상에 형성된 금속 플러그(70)의 높이보다 낮게 형성된다. In the case of forming the metal plug 70 as shown in FIG. 2C, since the topology with the recess remains, the metal plug 72 formed on the trench where the substructure 5 is over-etched is insulated. It is formed lower than the height of the metal plug 70 formed on 50.

이로 인하여, 금속 플러그(72) 사이에 형성된 절연막(80)의 상부에는 금속 레지듀(residue,90)가 적층되는 문제가 발생되고, 트렌치에 형성된 금속 플러그(72)가 균일하지 못함으로 인하여 금속 저항값이 안정화되지 못하는 단점이 있다. As a result, a problem arises in that a metal resistor 90 is stacked on the insulating layer 80 formed between the metal plugs 72, and the metal resistors 72 formed in the trenches are not uniform. There is a disadvantage that the value is not stabilized.

본 발명이 이루고자하는 기술적 과제는, 금속막 형성시 리세스 현상 및 레지듀 형성을 방지하고, 금속막의 저항값을 안정화시키는 반도체 소자의 제조 방법을 제공하는데 있다. SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a semiconductor device in which a recess phenomenon and resist formation are prevented during metal film formation, and a resistance value of the metal film is stabilized.

상기 과제를 이루기 위한 본 발명의 일 실시예에 의한 반도체 소자의 제조방법은 반도체 기판상에 절연물질을 증착하여 절연막을 형성하는 단계와, 절연막을 식각하여 절연막 표면을 평탄화하는 단계와, 평탄화된 절연막에 포토리소그래피 공정을 수행하여 트렌치를 형성하는 단계와, 오버 식각된 상기 트렌치를 포함하는 상기 반도체 기판 전면에 금속물질을 증착하되, 상기 오버식각된 트렌치 두께 이상으로 상기 절연막 상에 상기 금속물질을 증착하는 단계와, 절연막이 표면에 드러날 때까지 상기 금속물질을 식각하여 상기 트렌치에 매립된 금속물질을 노출시켜 금속막을 형성하는 단계를 포함하는 것이 바람직하다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming an insulating film by depositing an insulating material on a semiconductor substrate; and etching the insulating film to planarize the insulating film surface; Forming a trench by performing a photolithography process, depositing a metal material on the entire surface of the semiconductor substrate including the over-etched trench, and depositing the metal material on the insulating layer to the thickness of the over-etched trench. And etching the metal material until the insulating film is exposed on the surface to expose the metal material embedded in the trench to form a metal film.

상기 과제를 이루기 위한 본 발명의 다른 실시예에 의한 반도체 소자의 제조방법은 반도체 기판상에 절연물질을 증착하여 절연막을 형성하는 단계와, 절연막을 식각하여 절연막 표면을 평탄화하는 단계와, 평탄화된 절연막에 포토리소그래피 공정을 수행하여 트렌치를 형성하는 단계와, 반도체 기판 전면에 금속 물질을 증착하여 트렌치를 매립하는 금속막을 형성하는 단계 및 금속막 상부 및 절연막의 상부가 평탄할 때까지 금속막 및 절연막을 식각하되, 상기 절연막은 오버식각된 상기 트렌치 두께 이상으로 식각하는 단계를 포함하는 것이 바람직하다.According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming an insulating film by depositing an insulating material on a semiconductor substrate; Forming a trench by performing a photolithography process; forming a metal film filling a trench by depositing a metal material on the entire surface of the semiconductor substrate; and forming a metal film and an insulating film until the top of the metal film and the top of the insulating film are flat. Etching, the insulating film preferably comprises etching the over-etched thickness of the trench.

본 발명에 의한 반도체 소자의 제조 방법은 금속막을 균일하게 형성함으로써, 리세스 현상 및 레지듀의 발생을 방지할 수 있고, 금속막의 저항값을 안정화시킬 수 있다. In the method for manufacturing a semiconductor device according to the present invention, by forming the metal film uniformly, it is possible to prevent the recess phenomenon and the occurrence of residue, and to stabilize the resistance value of the metal film.

이하, 본 발명에 의한 반도체 소자의 제조 방법의 실시예들을 첨부한 도면들을 참조하여 다음과 같이 설명한다.Hereinafter, embodiments of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

도 3a 내지 도 3g는 본 발명의 일 실시예에 따른 반도체 소자의 제조 방법을 나타낸 공정단면도이다.3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3a에 도시된 바와 같이, 본 발명에 따른 반도체 소자 제조를 위한 방법은, 먼저 트랜지스터 제조공정 등의 일련의 반도체 제조 공정이 수행된 반도체 기판(300) 상에 절연막을 형성한다.As shown in FIG. 3A, the method for manufacturing a semiconductor device according to the present invention first forms an insulating film on a semiconductor substrate 300 on which a series of semiconductor manufacturing processes such as a transistor manufacturing process are performed.

여기서, 절연막은 BSG(Boro Silicate Glass)막, BPSG(Boro Phospho Silicate Glass)막, PSG(Phospho Silicate Glass)막, TEOS(Tetra Ethyl Ortho Silicate)막, HDP(High Density Plasma) 산화막, SOG(Spin On Glass)막 또는 APL(Advanced Planarization Layer)막 등을 이용하며, 산화막 계열 이외에 무기 또는 유기 계열의 저유전율막을 이용할 수 있다.The insulating film may include a BSG (Boro Silicate Glass) film, a BPSG (Boro Phospho Silicate Glass) film, a PSG (Phospho Silicate Glass) film, a TEOS (Tetra Ethyl Ortho Silicate) film, an HDP (High Density Plasma) oxide film, and a SOG (Spin On) film. A glass film or an advanced planarization layer (APL) film may be used, and an inorganic or organic low dielectric constant film may be used in addition to the oxide film series.

본 발명에서는 TEOS막을 사용하며, 3300Å 두께로 적층한다.In the present invention, a TEOS film is used and laminated to a thickness of 3300 mm 3.

다음, 절연막을 화학 기계적 연마 공정(Chemical Mechanical Polishing,CMP)으로 평탄화한다. Next, the insulating film is planarized by Chemical Mechanical Polishing (CMP).

그리고, 반도체 기판(300) 내에 형성된 콘택(미도시)을 노출시키기 위한 트 렌치(trench)를 형성하기 위하여 평탄화된 절연막(310) 상에 포토레지스트 패턴(미도시)을 형성한다. In addition, a photoresist pattern (not shown) is formed on the planarized insulating layer 310 to form a trench for exposing a contact (not shown) formed in the semiconductor substrate 300.

포토레지스트 패턴을 식각 마스크로 사용하여 평탄화된 절연막(310)을 식각하여 반도체 기판(300) 내에 형성된 콘택(미도시)을 노출시키는 트렌치(320)를 형성한다.The planarized insulating layer 310 is etched using the photoresist pattern as an etch mask to form a trench 320 that exposes a contact (not shown) formed in the semiconductor substrate 300.

그리고, 애싱(Ashing) 공정 등의 수행으로 포토 레지스트 패턴을 제거한다.Then, the photoresist pattern is removed by an ashing process or the like.

한편, 트렌치(320)를 형성할 때 절연막(310)을 오버 식각(over etching)하여 반도체 기판(300)까지 일부 식각된다고 가정한다. Meanwhile, when forming the trench 320, it is assumed that the insulating layer 310 is over-etched to partially etch the semiconductor substrate 300.

즉, 절연막(310)을 3300Å 이상으로 식각하여 반도체 기판(300)의 일부 영역(A)만큼 식각되었다고 하자.In other words, it is assumed that the insulating layer 310 is etched at 3300 Å or more to etch the partial region A of the semiconductor substrate 300.

도 3b에 도시된 바와 같이, 평탄화된 절연막(310)에 금속막을 형성하기 위하여 화학기상증착공정(Chemical Vapor Deposition:CVD)에 의해 트렌치(320)를 완전히 매몰시켜 텅스텐막(330)을 형성한다. As shown in FIG. 3B, the tungsten layer 330 is formed by completely buried the trench 320 by chemical vapor deposition (CVD) in order to form a metal layer on the planarized insulating layer 310.

이때, 오버식각된 트렌치에 매립되는 텅스텐막(330)의 상부에 리세스(recess) 현상을 방지하기 위하여 텅스텐막(330)을 4000Å 두께로 매립한다.In this case, the tungsten film 330 is buried in a thickness of 4000 Å to prevent a recess phenomenon on the tungsten film 330 embedded in the over-etched trench.

즉, 텅스텐막(330)을 4000Å 두께로 형성하면, 트렌치가 오버식각됨으로 인하여 함몰되는 A영역으로 인한 텅스텐막(330) 표면의 리세스를 방지하고, 절연막(310a)과 평평한 텅스텐막(330)을 구현할 수 있다. That is, when the tungsten film 330 is formed to have a thickness of 4000 Å, the trench is over-etched to prevent recesses on the surface of the tungsten film 330 due to the recessed A region, and the insulating film 310a and the flat tungsten film 330 are prevented. Can be implemented.

도 3c에 도시된 바와 같이, 화학적 기계적 연마 공정(CMP)을 실시하여 절연막(310a)이 표면에 드러날 때까지 텅스텐막(330)을 연마하여 트렌치(320) 이외의 부분에 존재하는 텅스텐막을 제거한다.As shown in FIG. 3C, a tungsten film 330 is polished until the insulating film 310a is exposed to the surface by performing a chemical mechanical polishing process (CMP) to remove the tungsten film present in portions other than the trench 320. .

이러한 방법으로 오버 식각된 트렌치상에 형성되는 텅스텐막(330a)의 상부면은 절연막(310a)의 상부 높이와 동일하게 된다.In this manner, the upper surface of the tungsten film 330a formed on the over-etched trench is the same as the upper height of the insulating film 310a.

즉, 본 발명은 종래에 트렌치 오버 식각으로 인해 텅스텐막(330)의 표면이 인접한 절연막(310a) 보다 함몰된 즉, 리세스(recess)를 동반한 토폴로지(topology) 현상을 방지함으로써, 절연막(310a)과 평탄한 텅스텐막(330a)을 구현할 수 있다.That is, according to the present invention, the surface of the tungsten film 330 is recessed than the adjacent insulating film 310a due to the trench over etching, that is, by preventing the topology phenomenon with the recess, the insulating film 310a ) And a flat tungsten film 330a may be implemented.

도 3d에 도시된 바와 같이, 평탄화된 절연막(310a) 및 텅스텐막(330a) 상에 층간 절연막(Inter Metal Dielectic, 이하 "IMD"라 한다,340)을 증착한다.As shown in FIG. 3D, an interlayer dielectric (Inter Metal Dielectic, hereinafter referred to as “IMD”) 340 is deposited on the planarized insulating layer 310a and the tungsten film 330a.

층간절연막(340)을 산화막 계열의 물질막으로 이용할 경우에는 BSG(Boro Silicate Glass)막, BPSG(Boro Phospho Silicate Glass)막, PSG(Phospho Silicate Glass)막, TEOS(Tetra Ethyl Ortho Silicate)막, HDP(High Density Plasma) 산화막, SOG(Spin On Glass)막 또는 APL(Advanced Planarization Layer)막 등을 이용하며, 산화막 계열 이외에 무기 또는 유기 계열의 저유전율막을 이용할 수 있다.When the interlayer insulating film 340 is used as an oxide-based material film, a BSG (Boro Silicate Glass) film, BPSG (Boro Phospho Silicate Glass) film, PSG (Phospho Silicate Glass) film, TEOS (Tetra Ethyl Ortho Silicate) film, HDP (High Density Plasma) oxide film, SOG (Spin On Glass) film or APL (Advanced Planarization Layer) film, and the like, in addition to the oxide film-based low dielectric constant film may be used.

본 발명에서는 층간 절연막(340)으로 TEOS막을 사용하며, 화학적 기상증착법(CVD)을 이용하여 7000Å 두께로 증착한다.In the present invention, a TEOS film is used as the interlayer insulating film 340, and is deposited to a thickness of 7000 Å by chemical vapor deposition (CVD).

도 3e에 도시된 바와 같이, 층간절연막(340)에 V1 패턴을 형성하기 위하여, 포토 레지스트 패턴(미도시)을 형성한 후, 이 포토 레지스트 패턴을 식각 마스크로 이용하여 층간절연막(340)을 식각하여 층간절연막 패턴(340a)을 형성한다.As shown in FIG. 3E, in order to form a V1 pattern on the interlayer insulating film 340, after forming a photoresist pattern (not shown), the interlayer insulating film 340 is etched using the photoresist pattern as an etching mask. The interlayer insulating film pattern 340a is formed.

V1 패턴은 텅스텐막(330a)을 플러그용 금속막으로 형성하기 위한 패턴이다.The V1 pattern is a pattern for forming the tungsten film 330a as a plug metal film.

도 3f에 도시된 바와 같이, 층간 절연막 패턴(340a) 상에 화학기상증착공정(Chemical Vapor Deposition:CVD)을 이용하여 텅스텐막(350)을 증착한다.As shown in FIG. 3F, a tungsten film 350 is deposited on the interlayer insulating film pattern 340a by using a chemical vapor deposition process (CVD).

층간 절연막 패턴(340a) 사이의 하부에 노출된 텅스텐막(330a)은 텅스텐막(350)과 전기적으로 연결된다. The tungsten film 330a exposed under the interlayer insulating film pattern 340a is electrically connected to the tungsten film 350.

도 3g에 도시된 바와 같이, 화학적 기계적 연마 공정(CMP)을 실시하여 층간 절연막 패턴(340a)이 표면에 드러날 때까지 텅스텐막(350)을 연마하여 절연막 패턴(340a) 이상의 부분에 존재하는 텅스텐막을 제거한다. As shown in FIG. 3G, the tungsten film 350 is polished until the interlayer insulating film pattern 340a is exposed on the surface by performing a chemical mechanical polishing process (CMP) to remove the tungsten film present in the portion of the insulating film pattern 340a or more. Remove

이로써 층간 절연막 패턴(340a) 사이에 매립된 텅스텐막(350a)을 노출시킨다.As a result, the tungsten film 350a buried between the interlayer insulating film patterns 340a is exposed.

이러한 방법으로 형성된 반도체 소자는 층간 절연막 패턴(340a) 상부에 레지듀(residue)의 적층을 방지시킬 수 있다. The semiconductor device formed in this manner may prevent stacking of resin on the interlayer insulating layer pattern 340a.

또한, 본 발명의 반도체 소자는 텅스텐막(350a)의 두께가 균일하기 때문에 금속막의 저항값이 안정되게 된다. Further, in the semiconductor element of the present invention, since the tungsten film 350a has a uniform thickness, the resistance value of the metal film becomes stable.

이하, 본 발명에 의한 반도체 소자의 제조방법의 다른 실시예를 설명한다.Hereinafter, another Example of the manufacturing method of the semiconductor element by this invention is described.

도 4a 및 도 4b는 본 발명의 다른 실시예에 따른 반도체 소자의 제조 방법을 나타낸 공정단면도이다.4A and 4B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

하부 구조물(미도시)이 포함된 반도체 기판(400) 상에 절연막을 형성하고, 절연막을 평탄화한 후, 절연막에 트렌치를 형성하는 방법은 도 3a를 참조하여 설명한 상기 실시예와 동일하므로, 자세한 설명은 생략하기로 한다. Since an insulating film is formed on the semiconductor substrate 400 including the lower structure (not shown), the insulating film is planarized, and a trench is formed in the insulating film, the same method as described above with reference to FIG. 3A is described. Will be omitted.

도 4a에 도시된 바와 같이, 트렌치를 포함한 반도체 기판 전면에 화학기상증 착공정(CVD)으로 텅스텐을 증착하여 트렌치를 매립한다.As shown in FIG. 4A, the trench is filled by depositing tungsten by chemical vapor deposition (CVD) on the entire surface of the semiconductor substrate including the trench.

이때, 트렌치를 형성하기 위해 절연막을 식각할 때 오버 식각된 트렌치 상에 증착된 텅스텐막(430a)의 상부는 절연막(410a)의 상부보다 낮게 형성된다. In this case, when the insulating layer is etched to form the trench, an upper portion of the tungsten layer 430a deposited on the over-etched trench is formed lower than an upper portion of the insulating layer 410a.

즉, 절연막을 식각하여 트렌치를 형성할 때, 반도체 기판(400)을 A만큼 오버식각했다면, 그 상부에 증착되는 텅스텐막(430a)의 상부는 절연막(410a)의 상부보다 A만큼 낮게 형성되어 리세스(recess)가 발생된다.That is, when the trench is formed by etching the insulating film, if the semiconductor substrate 400 is over-etched by A, the upper portion of the tungsten film 430a deposited on the upper portion is formed to be lower than the upper portion of the insulating film 410a. A recess is generated.

따라서, 도 4b에 도시된 바와 같이, 텅스텐막(430)의 전면을 화학적 기계적 연마 공정(CMP)을 실시하여 식각할 때 식각층(B-B')까지 식각함으로써, 리세스(recess)를 제거할 수 있다.Therefore, as shown in FIG. 4B, when the entire surface of the tungsten film 430 is etched by performing a chemical mechanical polishing process (CMP), the recess is removed by etching to the etching layer B-B '. can do.

즉, 식각층(B-B')까지 텅스텐막(430 및 430a) 및 절연막(410a)을 동시에 식각함으로써, 텅스텐막(430 및 430a) 및 절연막(410a)을 평탄화할 수 있다. That is, by simultaneously etching the tungsten films 430 and 430a and the insulating film 410a to the etching layer B-B ', the tungsten films 430 and 430a and the insulating film 410a can be planarized.

여기서, 식각층(B-B')은 오버식각된 반도체 기판(400) 상에 증착된 텅스텐막(430a)의 상부면 보다 낮게 임의로 정의된 식각층이라고 할 수 있다. Here, the etching layer B-B 'may be referred to as an etching layer arbitrarily defined lower than an upper surface of the tungsten film 430a deposited on the overetched semiconductor substrate 400.

이와 같은 방법으로, 본 발명은 반도체 소자의 제조에 있어서 금속막 표면의 리세스 현상 및 레지듀 발생을 방지할 수 있으며, 금속막을 균일하게 형성함으로써 금속막의 저항값을 안정화시킬 수 있다.In this manner, the present invention can prevent the recess phenomenon and the generation of residue on the surface of the metal film in the manufacture of the semiconductor element, and can stabilize the resistance value of the metal film by forming the metal film uniformly.

도 1은 일반적인 반도체 소자의 단면도.1 is a cross-sectional view of a general semiconductor device.

도 2a 내지 도 2c는 일반적인 반도체 소자의 제조과정을 나타낸 공정단면도.2A to 2C are cross-sectional views illustrating a manufacturing process of a general semiconductor device.

도 3a 내지 도 3g는 본 발명의 반도체 소자의 제조과정을 나타낸 공정단면도.3A to 3G are cross-sectional views illustrating a process of manufacturing a semiconductor device of the present invention.

도 4a 및 도 4b는 본 발명의 반도체 소자의 제조과정을 나타낸 공정단면도.Figures 4a and 4b is a cross-sectional view showing the manufacturing process of the semiconductor device of the present invention.

Claims (8)

반도체 기판상에 절연물질을 증착하여 절연막을 형성하는 단계;Forming an insulating film by depositing an insulating material on the semiconductor substrate; 상기 절연막을 식각하여 상기 절연막 표면을 평탄화하는 단계;Etching the insulating film to planarize the insulating film surface; 상기 평탄화된 절연막에 포토리소그래피 공정을 수행하여 트렌치를 형성하는 단계;Forming a trench by performing a photolithography process on the planarized insulating film; 오버 식각된 상기 트렌치를 포함하는 상기 반도체 기판 전면에 금속물질을 증착하되, 상기 오버식각된 트렌치 두께 이상으로 상기 절연막 상에 상기 금속물질을 증착하는 단계; Depositing a metal material on an entire surface of the semiconductor substrate including the over-etched trench, but depositing the metal material on the insulating layer to the thickness of the over-etched trench; 상기 절연막이 표면에 드러날 때까지 상기 금속물질을 식각하여 상기 트렌치에 매립된 금속물질을 노출시켜 금속막을 형성하는 단계;Etching the metal material until the insulating film is exposed on the surface to expose the metal material embedded in the trench to form a metal film; 를 포함하는 반도체 소자의 제조방법. Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, 상기 절연막은The method of claim 1, wherein the insulating film TEOS(Tetra Ethyl Ortho Silicate)막으로 형성됨을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, characterized in that it is formed of a TEOS (Tetra Ethyl Ortho Silicate) film. 제 1 항에 있어서, 상기 금속막은 The method of claim 1, wherein the metal film 텅스텐을 화학기상증착공정을 수행하여 형성됨을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, characterized in that formed by performing a chemical vapor deposition process tungsten. 제 1 항에 있어서, 상기 금속물질은 The method of claim 1, wherein the metal material 화학적 기계적 연마 공정을 이용하여 제거됨을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, characterized in that it is removed using a chemical mechanical polishing process. 반도체 기판상에 절연물질을 증착하여 절연막을 형성하는 단계;Forming an insulating film by depositing an insulating material on the semiconductor substrate; 상기 절연막을 식각하여 상기 절연막 표면을 평탄화하는 단계;Etching the insulating film to planarize the insulating film surface; 상기 평탄화된 절연막에 포토리소그래피 공정을 수행하여 트렌치를 형성하는 단계;Forming a trench by performing a photolithography process on the planarized insulating film; 상기 반도체 기판 전면에 금속 물질을 증착하여 상기 트렌치를 매립하여 금속막을 형성하는 단계; 및Depositing a metal material on the entire surface of the semiconductor substrate to fill the trench to form a metal film; And 상기 금속막 상부 및 상기 절연막의 상부가 평탄할 때까지 상기 금속막 및 상기 절연막을 식각하되, 상기 절연막은 오버식각된 상기 트렌치 두께 이상으로 식각하는 단계;Etching the metal film and the insulating film until the upper part of the metal film and the upper part of the insulating film are flat, wherein the insulating film is etched over the over-etched trench thickness; 를 포함하는 반도체 소자의 제조 방법.Wherein the semiconductor device is a semiconductor device. 제 5 항에 있어서, 상기 절연막은The method of claim 5, wherein the insulating film TEOS(Tetra Ethyl Ortho Silicate)막으로 형성됨을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, characterized in that it is formed of a TEOS (Tetra Ethyl Ortho Silicate) film. 제 5 항에 있어서, 상기 금속막은 The method of claim 5, wherein the metal film 텅스텐을 화학기상증착공정을 수행하여 형성됨을 특징으로 하는 반도체 소자 의 제조방법.A method of manufacturing a semiconductor device, characterized in that formed by performing a chemical vapor deposition process tungsten. 제 5 항에 있어서, 상기 금속물질 및 상기 절연막은 The method of claim 5, wherein the metal material and the insulating film 화학적 기계적 연마 공정을 이용하여 제거됨을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, characterized in that it is removed using a chemical mechanical polishing process.
KR1020080090716A 2008-09-16 2008-09-16 Method for manufacturing Semiconductor Device KR101023073B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080090716A KR101023073B1 (en) 2008-09-16 2008-09-16 Method for manufacturing Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080090716A KR101023073B1 (en) 2008-09-16 2008-09-16 Method for manufacturing Semiconductor Device

Publications (2)

Publication Number Publication Date
KR20100031872A KR20100031872A (en) 2010-03-25
KR101023073B1 true KR101023073B1 (en) 2011-03-24

Family

ID=42181244

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080090716A KR101023073B1 (en) 2008-09-16 2008-09-16 Method for manufacturing Semiconductor Device

Country Status (1)

Country Link
KR (1) KR101023073B1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000182992A (en) * 1998-12-17 2000-06-30 Sony Corp Manufacture of semiconductor device
JP2001060564A (en) * 1999-08-23 2001-03-06 Nec Corp Manufacture of semiconductor device
KR20030080311A (en) * 2002-04-08 2003-10-17 아남반도체 주식회사 Method for protecting scratch defect of semiconductor device
JP2007317682A (en) * 2006-05-23 2007-12-06 Renesas Technology Corp Process for fabricating semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000182992A (en) * 1998-12-17 2000-06-30 Sony Corp Manufacture of semiconductor device
JP2001060564A (en) * 1999-08-23 2001-03-06 Nec Corp Manufacture of semiconductor device
KR20030080311A (en) * 2002-04-08 2003-10-17 아남반도체 주식회사 Method for protecting scratch defect of semiconductor device
JP2007317682A (en) * 2006-05-23 2007-12-06 Renesas Technology Corp Process for fabricating semiconductor device

Also Published As

Publication number Publication date
KR20100031872A (en) 2010-03-25

Similar Documents

Publication Publication Date Title
US7348676B2 (en) Semiconductor device having a metal wiring structure
US7538023B2 (en) Method of manufacturing a semiconductor wafer device having separated conductive patterns in peripheral area
JP5635301B2 (en) Semiconductor device and manufacturing method thereof
KR100833201B1 (en) Semiconductor device having fine patterns of wiring line integrated with contact plug and method of manufacturing the same
KR100333382B1 (en) Method for forming multi-level metal interconnection of semiconductor device
KR100739252B1 (en) Method of manufacturing a semiconductor device
KR20110136473A (en) Semiconductor device and method of manufacturing a semiconductor device
KR20100112669A (en) Semiconductor device and method of manufacturing the same
US7932168B2 (en) Method for fabricating bitline in semiconductor device
KR101023073B1 (en) Method for manufacturing Semiconductor Device
JP2006294979A (en) Semiconductor device and its manufacturing method
KR100590205B1 (en) Interconnection Structure For Semiconductor Device And Method Of Forming The Same
JP2009130126A (en) Semiconductor device and method of manufacturing the same
TWI512894B (en) Metal interconnect structure and process thereof
US20230170293A1 (en) Beol top via wirings with dual damascene via and super via redundancy
KR100807026B1 (en) Method of fabricating semicondcucor device
KR100678008B1 (en) Method for fabricating metal line of semiconductor
KR100579858B1 (en) Method of fabricating mim(metal-insulator-metal) capacitor
KR20230085819A (en) Film deposition for patterning process
KR100922558B1 (en) Metal line of the semiconduct and method for manufacturing the same
KR100776141B1 (en) Fabricating method of metal line in semiconductor
KR100577309B1 (en) Method for forming semiconductor device
KR20020068417A (en) Semiconductor device with contacts having uniform contact resistance and method for manufacturing the same
KR20010056792A (en) Method of forming interconnection with dual damascene process
JP2005129816A (en) Semiconductor device having mim capacitor element, and manufacturing method thereof

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee