KR20020053542A - Method of forming a contact plug in a semiconductor device - Google Patents
Method of forming a contact plug in a semiconductor device Download PDFInfo
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- KR20020053542A KR20020053542A KR1020000083202A KR20000083202A KR20020053542A KR 20020053542 A KR20020053542 A KR 20020053542A KR 1020000083202 A KR1020000083202 A KR 1020000083202A KR 20000083202 A KR20000083202 A KR 20000083202A KR 20020053542 A KR20020053542 A KR 20020053542A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Abstract
Description
본 발명은 반도체 소자의 콘택 플러그 형성 방법에 관한 것으로, 특히 반도체 기판의 접합부를 선택적 에피 성장(Selective epitaxial growth; SEG)법으로 성장시켜 형성한 SEG 플러그를 콘택 플러그로 사용하는 반도체 소자의 콘택 플러그 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact plug of a semiconductor device, and in particular, to forming a contact plug of a semiconductor device using a SEG plug formed by growing a junction portion of a semiconductor substrate by a selective epitaxial growth (SEG) method as a contact plug. It is about a method.
최근 들어, 반도체 소자의 패턴이 미세화 됨에 따라 콘택의 종횡비(Aspect ratio)가 증가하기 때문에 반도체 기판 상에 일차적으로 콘택 플러그를 형성한 후 콘택 플러그 상에 금속 콘택을 이차적으로 형성하는 것이 일반적이 되었다. 이러한 일차적 콘택플러그 형성 시에도 디자인 룰이 0.1㎛ 이상인 소자의 경우에는, 층간 절연막 형성 후 콘택 마스크 노광 공정과 식각 공정을 실시하여 콘택홀을 형성하고, 폴리실리콘이나 전도성 물질을 매립하여 콘택 플러그를 형성할 수 있다. 그러나, 디자인 룰이 0.1㎛ 이하인 소자의 경우에는 마스크 노광 공정 및 식각 공정에 필요한 공정 마진이 부족하여 공정상의 문제가 발생한다.In recent years, as the aspect ratio of a contact increases as the pattern of a semiconductor device becomes finer, it is common to form a metal contact on a contact plug after forming a contact plug first on a semiconductor substrate. Even when the primary contact plug is formed, in the case of a device having a design rule of 0.1 µm or more, contact holes are formed by forming a contact insulating layer and an etching process after forming an interlayer insulating film, and forming a contact plug by embedding polysilicon or a conductive material. can do. However, in the case of a device having a design rule of 0.1 μm or less, process margins necessary for the mask exposure process and the etching process are insufficient, resulting in process problems.
이를 극복하기 위한 방법으로서, 반도체 기판의 접합부를 선택적 에피 성장법(Selective epitaxial growth)으로 성장시켜 콘택 플러그를 형성하는 방법이 있다.As a method for overcoming this, there is a method of forming a contact plug by growing a junction portion of a semiconductor substrate by selective epitaxial growth.
이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 콘택 플러그 형성 방법을 설명하기로 한다.Hereinafter, a method for forming a contact plug of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a를 참조하면, 필드 산화막(2)이 형성된 반도체 기판(1) 상에 게이트 산화막(3), 게이트 전극(4), 질화막 하드 마스크(5), 게이트 스페이서(6) 및 LDD 구조의 소오스/드레인(7)으로 이루어진 트랜지스터를 형성한다. 이후, 실리콘이 노출된 소오스/드레인(7) 영역에만 선택적 에피 성장법으로 단결정 실리콘을 성장시켜 SEG 플러그(8)를 형성한다.Referring to FIG. 1A, a source / gate of a gate oxide film 3, a gate electrode 4, a nitride film hard mask 5, a gate spacer 6, and an LDD structure is formed on a semiconductor substrate 1 on which a field oxide film 2 is formed. A transistor consisting of the drain 7 is formed. Thereafter, single crystal silicon is grown only on the source / drain 7 region where silicon is exposed to form an SEG plug 8.
도 1b를 참조하면, 선택적 에피 성장법으로 소오스/드레인(7) 영역에만 SEG 플러그(8)를 형성하는 과정에서 측면 성장(Lateral growth)이 동시에 발생하기 때문에, SEG 플러그(8)가 일정 높이로 성장하다 보면 근접해 있는 서로 다른 SEG 플러그가 서로 접촉하는 경우가 발생한다.Referring to FIG. 1B, since the SEG plug 8 is formed at a predetermined height in the process of forming the SEG plug 8 only in the source / drain 7 region by the selective epitaxial growth method, the SEG plug 8 is fixed at a predetermined height. As it grows, different SEG plugs in close proximity can come into contact with each other.
상술한 바와 같이, 일반적으로 미세 구조의 소자를 형성할 경우 콘택 면적이 매우 작고, 자기 정렬 콘택 식각의 필요성이 크기 때문에, 게이트 전극 상부나 비트 라인 상에 매우 두꺼운 실리콘 질화막 하드 마스크(Hard mask)를 형성하게 됨으로, 이에 따라 요구되는 SEG 플러그의 높이는 200nm이상으로 높아진다. 그러므로, 콘택마스크 없이 선택적 에피 성장을 통해 200nm이상의 플러그를 형성하게 되면, 도 1b에서 도시한 바와 같이, SEG 플러그(8)가 소오스/드레인(7) 영역으로부터 필드 산화막(2) 쪽으로 성장하는 측면 성장(Lateral growth)으로 인하여 양쪽 SEG 플러그가 단락되어 불량이 발생하기 쉽다.As described above, in general, when forming a microstructured device, since the contact area is very small and the need for self-aligned contact etching is large, a very thick silicon nitride hard mask is applied on the gate electrode or the bit line. As a result, the required height of the SEG plug is increased to 200 nm or more. Therefore, when a plug of 200 nm or more is formed through selective epitaxial growth without a contact mask, as shown in FIG. 1B, the side growth in which the SEG plug 8 grows from the source / drain 7 region toward the field oxide film 2 is performed. Due to (Lateral growth), both SEG plugs are short-circuited and defects are likely to occur.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 일차적으로 측면 성장(Lateral growth)의 정도가 허용 가능한 두께까지 1차 선택적 에피 박막을 성장시킨 후 에피 박막 사이에 절연물질을 매립하여 절연시킨 후 2차 선택적 에피 박막을 성장시킴으로써 목표 높이의 SEG 플러그를 형성하면서 SEG 플러그간의 단락이 발생하는 것을 방지하여 공정의 신뢰성을 향상시킬 수 있는 반도체 소자의 콘택 플러그 형성 방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the above problems, the present invention primarily grows a first selective epitaxial film to a thickness that allows a degree of lateral growth, and then insulates an insulating material between the epitaxial thin films and insulates the secondary. It is an object of the present invention to provide a method for forming a contact plug of a semiconductor device capable of improving process reliability by preventing a short circuit between SEG plugs while forming a SEG plug having a target height by growing a selective epi thin film.
도 1a 및 도 1b는 종래의 반도체 소자의 콘택 플러그 형성 방법을 설명하기 위하여 도시한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a method of forming a contact plug of a conventional semiconductor device.
도 2a 및 도 2d는 본 발명에 따른 반도체 소자의 콘택 플러그 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도.2A and 2D are cross-sectional views of devices sequentially shown to illustrate a method for forming a contact plug of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
1, 11 : 반도체 기판2, 12 : 필드 산화막1, 11: semiconductor substrate 2, 12: field oxide film
3, 13 : 게이트 산화막4, 14 : 게이트 전극3, 13 gate oxide film 4, 14 gate electrode
5, 15 : 하드 마스크6, 16 : 게이트 스페이서5, 15: hard mask 6, 16: gate spacer
7, 17 : 소오스/드레인8, 18 : SEG 플러그7, 17: source / drain 8, 18: SEG plug
18a : 제 1 선택적 에피 박막18b : 제 2 선택적 에피 박막18a: First Selective Epi Thin Film 18b: Second Selective Epi Thin Film
19 : 제 1 절연막20 : 제 2 절연막19: first insulating film 20: second insulating film
21 : 금속 물질21: metal material
본 발명에 따른 반도체 소자의 콘택 플러그 형성 방법은 소정의 공정을 실시하여 접합부가 노출된 반도체 기판이 제공되는 제 1 단계, 선택적 에피 성장법으로 접합부 상에 제 1 선택적 에피 박막을 형성하는 제 2 단계, 전체 상부에 제 1 절연막을 증착한 후 제 1 선택적 에피 박막 사이에 매립된 제 1 절연막을 제외한 나머지 영역의 제 1 절연막을 완전히 제거하고 상부를 노출시켜 제 1 선택적 에피 박막 사이를 보이드 없이 절연시키는 제 3 단계, 제 2 단계 및 제 3 단계를 반복 실시하여 콘택 플러그 사이가 절연된 상태로 목표 높이의 선택적 에피 박막을 형성하는 제 4 단계 및 전체 상부에 제 2 절연막을 형성하고 평탄화 한 후 소정 영역을 식각하여 선택적 에피 박막의 상부를 노출시키는 제 5 단계로 이루어진다.The method for forming a contact plug of a semiconductor device according to the present invention includes a first step of providing a semiconductor substrate having a junction portion exposed by performing a predetermined process, and a second step of forming a first selective epitaxial film on the junction portion by a selective epitaxial growth method. After depositing the first insulating film over the entire surface, completely removing the first insulating film in the remaining regions except for the first insulating film buried between the first selective epitaxial thin films and exposing the upper portions to insulate the first selective epitaxial films without voids. Repeating the third step, the second step and the third step to form a selective epi thin film having a target height with the contact plugs insulated and the second insulating film formed on the entire upper part and planarized Etching to form a fifth step of exposing the top of the selective epi thin film.
제 1 선택적 에피 박막은 측면 성장에 의한 단락을 방지하기 위하여 소자의 패턴 밀도에 따라 성장 높이를 결정한다. 이때, 제 1 선택적 에피 박막은 Si2H2Cl2또는 SiH4에 HCI을 첨가하고 H2로 희석시킨 가스를 이용하여 700 내지 950℃의 온도에서 저압 화학 기상 증착법으로 형성하거나, Si2H6및 Cl2를 H2로 희석시킨 가스를 이용하여 600 내지 750℃의 온도에서 초저압 화학 기상 증착법으로 성장시켜 형성한다. 제 1 절연막은 실리콘 산화막으로 형성한다.The first selective epitaxial film determines the growth height according to the pattern density of the device in order to prevent short circuit due to lateral growth. In this case, the first selective epitaxial thin film is formed by low pressure chemical vapor deposition at a temperature of 700 to 950 ° C. by adding HCI to Si 2 H 2 Cl 2 or SiH 4 and diluting with H 2 , or Si 2 H 6 And Cl 2 is grown by ultra low pressure chemical vapor deposition at a temperature of 600 to 750 ° C. using a gas diluted with H 2 . The first insulating film is formed of a silicon oxide film.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 2a 및 도 2d는 본 발명에 따른 반도체 소자의 콘택 플러그 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도이다.2A and 2D are cross-sectional views sequentially illustrating devices for sequentially forming a contact plug of a semiconductor device according to the present invention.
도 2a를 참조하면, 필드 산화막(12)이 형성된 반도체 기판(11)상에 게이트 산화막(13), 게이트 전극(14), 게이트 전극(14)을 패터닝하기 위하여 형성한 하드 마스크(15), 게이트 전극 스페이서(16) 및 소오스/드레인(17)으로 이루어진 트랜지스터를 형성한다. 이후, 소오스/드레인(17) 상에 일정 높이까지 선택적 에피 박막을 성장시켜 제 1 선택적 에피 박막(18a)을 형성한다.Referring to FIG. 2A, a hard mask 15 and a gate formed to pattern the gate oxide film 13, the gate electrode 14, and the gate electrode 14 on the semiconductor substrate 11 on which the field oxide film 12 is formed. A transistor consisting of an electrode spacer 16 and a source / drain 17 is formed. Thereafter, the selective epitaxial thin film is grown on the source / drain 17 to a predetermined height to form the first selective epitaxial film 18a.
제 1 선택적 에피 박막(18a)은 Si2H2Cl2또는 SiH4에 HCI을 첨가하고 H2로 희석시킨 가스를 이용하여 700 내지 950℃의 온도에서 저압 화학 기상 증착법으로 형성하거나 Si2H6및 Cl2를 H2로 희석시킨 가스를 이용하여 600 내지 750℃의 온도에서 초저압 화학 기상 증착법으로 성장시켜 형성한다. 이때, 제 1 선택적 에피 박막(18a)은 일정 높이 이상으로 성장을 진행시키게 되면 측면 성장이 발생하게 되고 이로 인해 플러그간 단락이 발생하게 되므로, 제 1 선택적 에피 박막(18a)의 성장 높이는 제 1 선택적 에피 박막(18a)간에 측면 성장에 의한 단락이 발생하지 않을 정도로 설정한다.The first selective epitaxial film 18a may be formed by low pressure chemical vapor deposition at a temperature of 700 to 950 ° C. using a gas diluted with H 2 and H 2 added to Si 2 H 2 Cl 2 or SiH 4 , or Si 2 H 6. And Cl 2 is grown by ultra low pressure chemical vapor deposition at a temperature of 600 to 750 ° C. using a gas diluted with H 2 . In this case, when the first selective epitaxial film 18a is grown at a predetermined height or more, lateral growth occurs and a short circuit occurs between the plugs. Thus, the growth height of the first selective epitaxial film 18a is first selected. It is set to such an extent that a short circuit due to lateral growth does not occur between the epi thin films 18a.
도 2b를 참조하면, 제 1 선택적 에피 박막(18a)간의 절연을 위하여 제 1 선택적 에피 박막(18a) 사이의 공간이 보이드 없이 충분히 매립될 수 있도록 전체 상부에 제 1 절연막(19)을 증착한다. 이후 건식 식각법으로 블랭킷 에치 백(Blanket etch-back)을 실시하거나, 불산 계열의 식각제를 사용한 습식 식각을 실시하거나 또는 블랭킷 에치 백과 습식 식각을 병행으로 실시하여 제 1 선택적 에피 박막(18a) 사이의 제 1 절연막(19)만을 잔류시키고, 나머지 영역의 제 1 절연막(19)은 완전히 제거한다. 이로써, 제 1 절연막(19)은 제 1 선택적 에피 박막(18a) 사이에만 잔류하며, 제 1 선택적 에피 박막(18a)의 상부 표면은 노출된다. 이때, 제 1 절연막(19)은 기타 영역의 막들(실리콘 질화막 및 콘택 플러그 실리콘)에 대해 선택적으로 제거가 가능하며 전기적 절연성을 갖는 물질을 사용한다. 실리콘 산화막(SiO2)이 대표적인 물질이다.Referring to FIG. 2B, the first insulating layer 19 is deposited over the entire surface of the first selective epitaxial film 18a so that the space between the first selective epitaxial film 18a can be sufficiently filled without voids. Thereafter, a blanket etch-back is performed by dry etching, a wet etching using a hydrofluoric acid-based etching agent, or a blanket etch bag and a wet etching are performed in parallel to form the first selective epitaxial film 18a. Only the first insulating film 19 is left, and the first insulating film 19 in the remaining area is completely removed. Thus, the first insulating film 19 remains only between the first selective epitaxial films 18a, and the upper surface of the first selective epitaxial films 18a is exposed. In this case, the first insulating film 19 may be selectively removed with respect to the films (silicon nitride film and contact plug silicon) in other regions, and may be made of a material having electrical insulation. Silicon oxide film (SiO 2 ) is a representative material.
도 2c를 참조하면, 목표 높이의 에피 박막을 형성하기 위하여 도 2a에서 실시한 저압 화학 기상 증착법이나 초저압 화학 기상 증착법으로 형성된 제 1 선택적 에피 박막(18a) 상에 제 2 선택적 에피 박막(18b)을 형성한다.Referring to FIG. 2C, a second selective epitaxial film 18b is formed on the first selective epitaxial film 18a formed by the low pressure chemical vapor deposition method or the ultra low pressure chemical vapor deposition method described in FIG. 2A to form an epitaxial film having a target height. Form.
상기와 같은 2단계 공정으로 목표 두께를 달성할 수 없을 경우, 목표 두께의 에피 박막을 성장시키기 위해서는 도 2a에서 실시한 선택적 에피 성장과 도 2b에서실시한 에피 박막간의 절연 공정을 반복 실시한다.When the target thickness cannot be achieved by the two-step process as described above, in order to grow the epitaxial film having the target thickness, the insulating process between the selective epitaxial growth of FIG. 2A and the epitaxial film of FIG. 2B is repeatedly performed.
도 2d를 참조하면, 제 1 및 제 2 선택적 에피 박막(18a 및 18b)을 형성하여 목표 높이의 선택적 에피 박막(18)이 형성되면, 후속 공정에서 형성될 상부 요소와의 절연을 위하여 전체 상부에 제 2 절연막(20)을 형성한 후 평탄화 공정을 실시한다. 이후, 수직 배선을 위하여 하부 요소의 접합 영역인 선택적 에피 박막(18) 또는 게이트 전극(14)의 표면이 노출되는 소정의 콘택홀을 형성하고, 금속 물질(21)을 매립한다. 이때, 금속 물질(21)을 매립하기 전에 접촉 저항을 낮추기 위하여 오믹 콘택층을 형성하거나, 선택적 에피 박막(18)으로의 산소 확산을 방지하기 위하여 확산 방지막을 형성하기도 한다. 상기의 공정에서 선택적 에피 박막(18)을 콘택 플러그로 사용함으로써 종횡비가 낮아진 상태에서 금속 물질(21)을 매립하게 되므로 매립 특성을 향상시키게 된다.Referring to FIG. 2D, when the first and second selective epitaxial films 18a and 18b are formed to form the selective epitaxial film 18 of the target height, the entire upper portion is insulated for isolation from the upper element to be formed in a subsequent process. After the second insulating film 20 is formed, a planarization process is performed. Thereafter, a predetermined contact hole is formed to expose the surface of the selective epitaxial film 18 or the gate electrode 14, which is a junction region of the lower element, for the vertical wiring, and the metal material 21 is buried. In this case, an ohmic contact layer may be formed to lower contact resistance before the metal material 21 is embedded, or a diffusion barrier may be formed to prevent oxygen diffusion into the selective epitaxial film 18. In the above process, by using the selective epitaxial film 18 as the contact plug, the metal material 21 is buried in the state where the aspect ratio is lowered, thereby improving the embedding characteristics.
상기의 공정으로, 본 발명에서는 일차적으로 측면 성장(Lateral growth)의 정도가 허용 가능한 두께까지 선택적 에피 박막을 성장시킨 후 절연막을 증착하고 에치 백(Etch-back)하여 필드 산화막 양쪽의 선택적 에피 박막 사이를 절연막으로 채워 단락을 방지한 뒤 2차 선택적 에피 박막을 성장시킴으로써 측면 성장으로 인한 성장의 높이 제한을 개선할 수 있다.In the above process, in the present invention, the selective epitaxial film is first grown to a thickness that allows the degree of lateral growth, and then an insulating film is deposited and etched back to select between the selective epitaxial films on both sides of the field oxide film. It is possible to improve the height limit of growth due to lateral growth by filling a with an insulating layer to prevent a short circuit and then grow a second selective epi thin film.
상술한 바와 같이, 본 발명은 선택적 에피 박막 사이에 절연막을 매립하여측면 성장에 의한 단락을 방지함으로써 초미세 구조의 패턴에서도 불량 없이 목표 높이의 에피 박막을 성장시킬 수 있어, 공정의 신뢰성을 향상시키는 효과가 있다.As described above, according to the present invention, an insulating film is interposed between the selective epi thin films to prevent short-circuits due to side growth, so that the epi thin film having a target height can be grown without a defect even in an ultra fine structure pattern, thereby improving process reliability. It works.
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| KR100611112B1 (en) * | 2005-01-20 | 2006-08-09 | 삼성전자주식회사 | Single crystal structure and method for forming the same, emiconductor device having the Single crystal structure and method for manufacturing the same |
| KR100728968B1 (en) * | 2005-12-28 | 2007-06-15 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| US7338867B2 (en) | 2003-02-17 | 2008-03-04 | Samsung Electronics Co., Ltd. | Semiconductor device having contact pads and method for manufacturing the same |
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| US5753555A (en) * | 1995-11-22 | 1998-05-19 | Nec Corporation | Method for forming semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7338867B2 (en) | 2003-02-17 | 2008-03-04 | Samsung Electronics Co., Ltd. | Semiconductor device having contact pads and method for manufacturing the same |
| US7511340B2 (en) | 2003-02-17 | 2009-03-31 | Samsung Electronics Co., Ltd. | Semiconductor devices having gate structures and contact pads that are lower than the gate structures |
| KR100611112B1 (en) * | 2005-01-20 | 2006-08-09 | 삼성전자주식회사 | Single crystal structure and method for forming the same, emiconductor device having the Single crystal structure and method for manufacturing the same |
| KR100728968B1 (en) * | 2005-12-28 | 2007-06-15 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
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