KR20020002733A - Method of filling a contact hole in a semiconductor device - Google Patents
Method of filling a contact hole in a semiconductor device Download PDFInfo
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- KR20020002733A KR20020002733A KR1020000037019A KR20000037019A KR20020002733A KR 20020002733 A KR20020002733 A KR 20020002733A KR 1020000037019 A KR1020000037019 A KR 1020000037019A KR 20000037019 A KR20000037019 A KR 20000037019A KR 20020002733 A KR20020002733 A KR 20020002733A
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- contact hole
- interlayer insulating
- etching
- insulating film
- insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
Description
본 발명은 반도체 소자의 콘택홀 매립 방법에 관한 것으로, 특히 화학기상증착법으로 금속을 증착하여 콘택홀을 매립할 때, 반도체 소자의 고집적화로 크기가 작아 진 콘택홀을 양호하게 매립시킬 수 있는 반도체 소자의 콘택홀 매립 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for filling contact holes in a semiconductor device. In particular, when a contact hole is filled by depositing a metal by chemical vapor deposition, a semiconductor device capable of satisfactorily filling a small contact hole due to high integration of the semiconductor device is well formed. It relates to a method of filling a contact hole.
일반적으로, 반도체 소자의 제조 공정중 하부 도전층과 상부 도전층을 전기적으로 상호 연결시키기 위하여 콘택홀을 형성한다. 반도체 소자가 고집적화 되어 감에 따라 콘택홀의 크기가 줄어들 뿐만 아니라, 배선간의 간격 또한 줄어들어 콘택 공정 마진을 확보하기가 점점 어려워 지고 있다. 콘택홀의 크기가 줄어듦에 따라 콘택홀 매립과 금속 배선 증착을 한번의 증착 공정으로 하기가 어려워 금속배선을 형성하기 전에 먼저 콘택홀 내부를 도전성 물질로 채우는 콘택홀 매립 공정이 도입되었다. 최근에는 소자의 동작 속도를 증대시키기 위하여 콘택 매립에 사용하는 물질을 전도성이 우수한 금속을 화학기상증착법(CVD)으로 증착하여 콘택홀을 매립시키고 있다.In general, contact holes are formed to electrically interconnect the lower conductive layer and the upper conductive layer during the manufacturing process of the semiconductor device. As semiconductor devices are highly integrated, not only the contact hole size is reduced, but also the gap between wirings is reduced, making it difficult to secure a contact process margin. As contact hole size decreases, contact hole filling and metal wire deposition are difficult to be deposited in one deposition process. Therefore, a contact hole filling process for filling a contact hole with a conductive material is introduced before forming a metal wiring. Recently, in order to increase the operation speed of a device, a contact hole is buried by depositing a metal having excellent conductivity by chemical vapor deposition (CVD).
도 1a 내지 도 1d는 종래 반도체 소자의 콘택홀 매립 방법을 설명하기 위한 소자의 단면도이다.1A to 1D are cross-sectional views of devices for describing a method for filling contact holes in a conventional semiconductor device.
도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(11) 상에 층간 절연막(12)을 형성하고, 층간 절연막(12) 상에 콘택홀 형성을 위한 포토레지스트 패턴(13)을 형성한다. 포토레지스트 패턴(13)을 식각 마스크로 한 식각 공정으로 층간 절연막(12)을 식각하여 콘택홀(14)을 형성한다.Referring to FIG. 1A, an interlayer insulating layer 12 is formed on a substrate 11 on which various elements for forming a semiconductor device are formed, and a photoresist pattern 13 for forming a contact hole is formed on the interlayer insulating layer 12. Form. The contact hole 14 is formed by etching the interlayer insulating layer 12 by an etching process using the photoresist pattern 13 as an etching mask.
상기에서, 콘택홀(14)에 의해 노출되는 기판(11) 부분은 반도체 기판에 형성된 접합부이거나 또는 워드 라인, 비트 라인 및 금속 배선등의 전도성 패턴이다.In the above, the portion of the substrate 11 exposed by the contact hole 14 is a junction formed in the semiconductor substrate or a conductive pattern such as a word line, a bit line, and a metal wiring.
도 1b를 참조하면, 포토레지스트 패턴(13)을 제거한 후, 화학기상증착법에 의한 금속 증착 공정중 핵 생성 공정을 진행하여 콘택홀(14)을 포함한 층간 절연막(12) 표면을 따라 금속 핵(15A)을 형성한다.Referring to FIG. 1B, after the photoresist pattern 13 is removed, a nucleation process is performed during the metal deposition process by chemical vapor deposition, and the metal nucleus 15A is formed along the surface of the interlayer insulating layer 12 including the contact hole 14. ).
상기에서, 금속 핵(15A)은 콘택홀(14) 내부에 생성되는 속도 보다 입구 부분에 생성되는 속도가 빨라 콘택홀(14)의 입구가 좁을 경우 입구가 막히는 현상이 발생된다.In the above, the metal nucleus 15A is formed at the inlet portion faster than the speed generated in the contact hole 14 so that the inlet is blocked when the inlet of the contact hole 14 is narrow.
도 1c를 참조하면, 콘택홀(14) 내부를 완전히 매립시키기 위하여 금속 증착 공정중 성장 공정을 진행하여 금속층(15)을 형성한다.Referring to FIG. 1C, in order to completely fill the inside of the contact hole 14, a growth process is performed in the metal deposition process to form the metal layer 15.
상기에서, 성장 공정을 진행하여 콘택홀(14) 내부를 완전히 매립시키고자 하여도 이전 공정인 핵 생성 공정시에 금속 핵(15A)이 콘택홀(14) 입구를 막고 있기 때문에 내부에 보이드(19)가 생기게 된다.In the above-described process, although the metal nucleus 15A blocks the entrance of the contact hole 14 during the nucleation process, which is a previous step, even when the growth process is performed to completely fill the inside of the contact hole 14, the void 19 ).
도 1d를 참조하면, 전면 식각 공정을 층간 절연막(12)의 표면이 노출되는 시점까지 실시하여 콘택홀(14) 내부가 금속층(15)으로 매립된 콘택 플러그(150)가 형성된다. 콘택 플러그(150)에 보이드(19)가 존재하므로 인하여 전기적 저항의 증가를 초래하게 된다.Referring to FIG. 1D, the entire surface etching process is performed until the surface of the interlayer insulating layer 12 is exposed to form the contact plug 150 having the inside of the contact hole 14 filled with the metal layer 15. Since the void 19 is present in the contact plug 150, an increase in electrical resistance is caused.
상기한 바와 같이, 화학기상증착법에 의한 금속 증착은 크게 핵 생성 단계와 성장 단계로 구분하여 진행하고 있다. 콘택홀(14)을 매립하는 성장 단계는 콘택홀(14) 내에서 금속의 층덮힘 특성을 좋게하기 위하여 표면에서 반응하는 속도가 전체 박막 증착 속도를 결정하도록 공정 조건을 설정할 수 있지만, 핵 생성 단계는 핵(15A)이 웨이퍼 전체면에 균일하게 형성되어야 하므로 반응 속도 결정 조건으로 증착하기 어렵다. 따라서, 핵 생성 단계에서 증착된 금속 핵(15A)은 층덮힘 특성이 좋지 않아 콘택홀(14)의 입구가 좁을 경우 콘택홀(14)의 입구가 막히고 콘택홀(14) 내부가 비어있는 보이드 구조를 갖게된다. 이 상태에서 콘택홀(14) 매립을 위한 성장 단계를 진행하여도 입구가 먼저 막혀있기 때문에 콘태홀(14) 내부에는 증착이 어렵게 된다.As described above, metal deposition by chemical vapor deposition is largely divided into a nucleation step and a growth step. The growth step of embedding the contact hole 14 may set the process conditions such that the rate of reaction at the surface determines the overall thin film deposition rate in order to improve the layer covering properties of the metal in the contact hole 14, but the nucleation step Since the nucleus 15A must be uniformly formed on the entire surface of the wafer, it is difficult to deposit the reaction rate determining conditions. Therefore, the metal nucleus 15A deposited in the nucleation step has poor layer covering characteristics, so that when the inlet of the contact hole 14 is narrow, the inlet of the contact hole 14 is blocked and the inside of the contact hole 14 is empty. Will have In this state, even when the growth step for filling the contact hole 14 is progressed, since the inlet is blocked first, it is difficult to deposit the inside of the contact hole 14.
따라서, 본 발명은 화학기상증착법으로 금속을 증착하여 콘택홀을 매립할 때, 반도체 소자의 고집적화로 콘택홀의 크기가 작아 질 경우 금속 핵 생성 단계에서 콘택홀 입구가 막히는 것을 방지하여 입구가 좁은 콘택홀 내부를 금속으로 양호하게 매립시킬 수 있는 반도체 소자의 콘택홀 매립 방법을 제공함에 그 목적이 있다.Therefore, in the present invention, when the contact hole is filled by depositing metal by chemical vapor deposition, when the contact hole becomes small due to high integration of the semiconductor device, the contact hole inlet is prevented from being blocked in the nucleation process, so that the contact hole is narrow. It is an object of the present invention to provide a method for filling a contact hole in a semiconductor device capable of satisfactorily filling an inside with a metal.
도 1a 내지 도 1d는 종래 반도체 소자의 콘택홀 매립 방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a method of filling a contact hole in a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 매립 방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of devices for explaining a method of filling contact holes in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11, 21: 기판 12, 22: 층간 절연막11, 21: substrate 12, 22: interlayer insulating film
13, 23: 포토레지스트 패턴 14, 24: 콘택홀13 and 23 photoresist patterns 14 and 24 contact holes
15A, 25A: 금속 핵 15, 25: 금속층15A, 25A: metal nucleus 15, 25: metal layer
19: 보이드 150, 250; 콘택 플러그19: voids 150, 250; Contact plug
220: 희생 절연막220: sacrificial insulating film
본 발명의 실시예에 따른 반도체 소자의 콘택홀 매립 방법은 기판 상에 층간 절연막을 형성하는 단계; 층간 절연막 상에 식각 선택비가 다른 희생 절연막을 형성하는 단계; 콘택 마스크 공정 및 식각 공정으로 희생 절연막 및 층간 절연막을 식각하여 콘택홀을 형성하는 단계; 핵 생성 공정을 진행하여 콘택홀을 포함한 층간절연막 표면을 따라 금속 핵을 형성하는 단계; 핵 생성 공정에 연속하여 성장 공정을 진행하여 콘택홀 내부를 완전히 매립시키기는 금속층을 형성하는 단계; 및 금속층 및 희생 절연막을 식각하여 층간 절연막 부분의 콘택홀 내부가 금속층으로 매립된 콘택 플러그를 형성하는 단계를 포함하여 이루어진다.A contact hole filling method of a semiconductor device according to an embodiment of the present invention comprises the steps of forming an interlayer insulating film on the substrate; Forming a sacrificial insulating film having a different etching selectivity on the interlayer insulating film; Forming a contact hole by etching the sacrificial insulating film and the interlayer insulating film by a contact mask process and an etching process; Performing a nucleation process to form a metal nucleus along a surface of an interlayer insulating film including a contact hole; Forming a metal layer to completely fill the inside of the contact hole by performing a growth process subsequent to the nucleation process; And etching the metal layer and the sacrificial insulating layer to form a contact plug in which the inside of the contact hole of the interlayer insulating layer portion is embedded with the metal layer.
상기에서, 콘택홀은 희생 절연막이 포지티브 경사를 이루고, 층간 절연막이 버티컬 형상을 이루는 입구 부분이 하부 보다 크며, 포지티브 경사는 그 경사각이 30 내지 80。 범위이고, 희생 절연막은 500 내지 1000 Å의 두께로 형성한다.In the above, the contact hole has a positive inclination of the sacrificial insulating film, the inlet portion of which the interlayer insulating film has a vertical shape is larger than the lower portion, the positive inclination of the inclination angle is in the range of 30 to 80 °, and the sacrificial insulating film has a thickness of 500 to 1000 kPa. To form.
희생 절연막은 동일한 식각 조건에서 층간 절연막보다 빨리 식각되는 물질로 형성하는데, 층간 절연막이 PE-TEOS를 이용한 SiO2막 또는 HDP 장비를 사용하여 증착한 SiO2막으로 형성하면 희생 절연막은 PSG, USG, SOG 와 같은 산화막으로 형성한다.When the sacrificial insulating film to form a material which is quickly etched than the insulating film between layers in the same etching conditions, an interlayer insulating film is formed of PE-TEOS as a SiO 2 film is deposited by using the SiO 2 film or HDP equipment using the sacrificial insulating film is PSG, USG, It is formed of an oxide film such as SOG.
콘택 플러그를 형성하기 위한 식각 공정은 화학적 기계적 연마 방법이나, 금속층을 층간 절연막의 표면부 까지 1차로 식각하고, 2차로 희생 절연막을 제거하는 방법을 사용한다.The etching process for forming the contact plug uses a chemical mechanical polishing method or a method of first etching the metal layer to the surface portion of the interlayer insulating film and secondly removing the sacrificial insulating film.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따란 반도체 소자의 콘택홀 매립 방법을 설명하기 위한 소자의 단면도이다.2A to 2D are cross-sectional views of devices for explaining a method of filling contact holes in a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된기판(21) 상에 층간 절연막(22)을 형성한다. 층간 절연막(22) 상에 층간 절연막(22)가 식각 선택비가 다른 희생 절연막(220)을 일정 두께 형성하고, 그 상부에 콘택홀 형성을 위한 포토레지스트 패턴(23)을 형성한다. 포토레지스트 패턴(23)을 식각 마스크로 한 식각 공정으로 희생 절연막(220) 및 층간 절연막(22)을 식각하여 희생 절연막(22) 부분에서 포지티브(positive) 경사를 이루고 층간 절연막(22)에서 버티컬(vertical)한 형상을 이루는 입구 부분이 하부 보다 큰 콘택홀(24)을 형성한다.Referring to FIG. 2A, an interlayer insulating layer 22 is formed on a substrate 21 on which various elements for forming a semiconductor device are formed. A sacrificial insulating film 220 having different etching selectivity is formed on the interlayer insulating film 22 by a predetermined thickness, and a photoresist pattern 23 for forming a contact hole is formed on the interlayer insulating film 22. In the etching process using the photoresist pattern 23 as an etching mask, the sacrificial insulating film 220 and the interlayer insulating film 22 are etched to form a positive inclination at the portion of the sacrificial insulating film 22 and the vertical (in the interlayer insulating film 22) An inlet portion constituting a vertical shape forms a contact hole 24 larger than the lower portion.
상기에서, 콘택홀(24)에 의해 노출되는 기판(21) 부분은 반도체 기판에 형성된 접합부이거나 또는 워드 라인, 비트 라인 및 금속 배선등의 전도성 패턴이다. 희생 절연막(220)은 500 내지 1000 Å의 두께로 형성하며, 식각 공정에 의해 포지티브 경사를 이루는데, 그 경사각은 30 내지 80。 정도이다. 입구 부분이 하부 구조보다 큰 콘택홀(24)을 얻기 위하여, 층간 절연막(22)과 희생 절연막(220)은 식각 선택비가 다른 물질로 형성해야 하는데, 동일한 식각 조건으로 식각할 때 희생 절연막(220)이 층간 절연막(22)보다 빨리 식각되도록 물질을 선택하여야 한다. 예를 들어, 층간 절연막(22)으로 PE-TEOS를 이용한 SiO2막 또는 HDP 장비를 사용하여 증착한 SiO2막을 사용할 경우, 희생 절연막(220)은 PSG, USG, SOG 등의 산화막을 사용한다.In the above description, the portion of the substrate 21 exposed by the contact hole 24 is a junction formed in the semiconductor substrate or a conductive pattern such as a word line, a bit line, and a metal wiring. The sacrificial insulating film 220 is formed to a thickness of 500 to 1000 GPa, and forms a positive inclination by an etching process, and the inclination angle is about 30 to 80 degrees. In order to obtain a contact hole 24 having an inlet portion larger than a lower structure, the interlayer insulating film 22 and the sacrificial insulating film 220 should be formed of materials having different etching selectivity. The material should be selected to be etched faster than this interlayer insulating film 22. For example, when the SiO 2 film using PE-TEOS or the SiO 2 film deposited using HDP equipment is used as the interlayer insulating film 22, the sacrificial insulating film 220 uses an oxide film such as PSG, USG, or SOG.
도 2b를 참조하면, 포토레지스트 패턴(23)을 제거한 후, 화학기상증착법에 의한 금속 증착 공정중 핵 생성 공정을 진행하여 콘택홀(24)을 포함한 층간절연막(22) 표면을 따라 금속 핵(25A)을 형성한다.Referring to FIG. 2B, after the photoresist pattern 23 is removed, a nucleation process is performed during the metal deposition process by chemical vapor deposition, and the metal nucleus 25A is formed along the surface of the interlayer insulating film 22 including the contact hole 24. ).
상기에서, 콘택홀(14)의 입구가 넓기 때문에 금속 핵(25A)이 종래처럼 입구를 막는 현상이 발생하기 않으며, 콘택홀(14) 내부에도 균일하게 형성된다. 금속 핵(25A)은 100 내지 700 Å의 두께로 형성한다. 금속 핵(25A)은 그 두께가 얇을 수록 매립 특성이 향상되므로 콘택홀(24) 바닥에 다른 영향이 없는 한 얇게 형성하는 것이 바람직하다. 금속 핵(25A)을 더욱 균일하게 형성하기 위하여 금속 핵(25A)을 형성하기 전에 콘택홀(24) 바닥에 생성되는 자연 산화막을 건식 세정 공정으로 제거한다. 건식 세정 공정은 먼저 RF 전력을 200 내지 550 Watt 범위로 하여 1차로 진행하고, 2차로 RF 전력을 200 내지 500 Watt 범위로 하여 진행하여, 콘택홀(24)의 모양을 좀더 완만하게 하여 금속 핵(25A) 형성에 도움이 되도록 할 수 있다.In the above, since the inlet of the contact hole 14 is wide, the phenomenon in which the metal core 25A blocks the inlet does not occur as in the prior art, and is uniformly formed in the contact hole 14. The metal core 25A is formed to a thickness of 100 to 700 mm 3. The thinner the metal core 25A is, the better the embedding characteristics are. Therefore, it is preferable to form the metal core 25A as long as there is no other effect on the bottom of the contact hole 24. In order to form the metal core 25A more uniformly, the natural oxide film formed at the bottom of the contact hole 24 is removed by a dry cleaning process before the metal core 25A is formed. In the dry cleaning process, the RF power is first performed in the range of 200 to 550 Watt, and the RF power is secondly performed in the range of 200 to 500 Watt, so that the shape of the contact hole 24 is more gentle, so that the metal core ( 25A) may help to form.
도 2c를 참조하면, 콘택홀(24) 내부를 완전히 매립시키기 위하여 금속 증착 공정중 성장 공정을 진행하여 금속층(25)을 형성한다.Referring to FIG. 2C, in order to completely fill the inside of the contact hole 24, a growth process may be performed in the metal deposition process to form the metal layer 25.
상기에서, 금속 핵(25A) 성장시 콘택홀(24)의 입구가 막히지 않았기 때문에 금속층(25)은 콘택홀(24) 내부에서 보이드 없이 양호하게 매립되어진다.In the above, since the inlet of the contact hole 24 is not blocked during the growth of the metal core 25A, the metal layer 25 is well buried without voids in the contact hole 24.
도 2d를 참조하면, 금속층(25) 및 희생 절연막(220)을 층간 절연막(22)의 표면이 노출되는 시점까지 전면 식각 공정으로 식각하여 층간 절연막(22) 부분의 콘택홀(24) 내부가 금속층(25)으로 매립된 콘택 플러그(250)를 형성한다.Referring to FIG. 2D, the metal layer 25 and the sacrificial insulating layer 220 are etched by the entire surface etching process until the surface of the interlayer insulating layer 22 is exposed, so that the inside of the contact hole 24 of the interlayer insulating layer 22 is the metal layer. A contact plug 250 embedded in 25 is formed.
상기에서, 전면 식각 공정은 화학적 기계적 연마(CMP) 방법을 사용하거나, 먼저 금속층(25)을 금속 식각제로 층간 절연막(22)의 표면부 까지 식각하고, 이후 건식 또는 습식 식각 공정으로 희생 절연막(220)을 제거하는 방법을 사용한다. 습식 식각으로 희생 절연막(220)을 제거할 경우 습식 식각의 식각 방지막으로 적용하기 위해 층간 절연막(22)과 희생 절연막(220) 사이에 식각 방지막(도시 않음)을 형성할 수도 있다. 층간 절연막(22) 및 희생 절연막(220)이 산화물로 형성할 경우 식각 방지막은 질화물로 형성한다.In the above, the front surface etching process may use a chemical mechanical polishing (CMP) method, or first, the metal layer 25 is etched to the surface portion of the interlayer insulating layer 22 with a metal etchant, and then the sacrificial insulating layer 220 is formed by a dry or wet etching process. ) To remove it. When the sacrificial insulating layer 220 is removed by wet etching, an etch stop layer (not shown) may be formed between the interlayer insulating layer 22 and the sacrificial insulating layer 220 in order to be used as an etching preventing layer of wet etching. When the interlayer insulating layer 22 and the sacrificial insulating layer 220 are formed of oxide, the etch stop layer is formed of nitride.
상술한 바와 같이, 본 발명은 화학기상증착법으로 금속을 증착하여 콘택홀을 매립할 때, 반도체 소자의 고집적화로 콘택홀의 크기가 작아 질 경우 금속 핵 생성 단계에서 콘택홀 입구가 막히는 것을 방지하기 위하여, 층간 절연막상에 식각 선택비가 다른 희생 절연막을 형성하고, 식각 선택비의 차이에 의해 희생 절연막은 포지티브(positive) 경사를 이루고 층간 절연막은 은 버티컬(vertical) 형상으로 되어, 입구 부분이 크진 콘택홀을 얻을 수 있고, 이러한 콘택홀 내부를 화학기상증착에 의해 금속을 양호하게 매립시킨 후, 전면 식각 공정을 층간 절연막의 표면 부분까지 실시하여 포지티브 경사 부분을 제거하므로, 입구가 좁은 콘택홀 내부를 금속으로 양호하게 매립시킬 수 있다.As described above, the present invention, when filling the contact hole by depositing the metal by chemical vapor deposition, in order to prevent the contact hole inlet is blocked in the nucleation step of the metal when the contact hole becomes small due to high integration of the semiconductor device, A sacrificial insulating film having a different etching selectivity is formed on the interlayer insulating film. The sacrificial insulating film has a positive inclination due to the difference in the etching selectivity, and the interlayer insulating film has a silver vertical shape. Since the inside of the contact hole is well filled with metal by chemical vapor deposition, the front side etching process is performed to the surface portion of the interlayer insulating film to remove the positive inclined portion, so that the inside of the narrow contact hole is made of metal. It can be buried well.
Claims (14)
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| KR1020000037019A KR20020002733A (en) | 2000-06-30 | 2000-06-30 | Method of filling a contact hole in a semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100913331B1 (en) * | 2007-09-20 | 2009-08-20 | 주식회사 동부하이텍 | MOS transistor and method for manufacturing the transistor |
| KR101024260B1 (en) * | 2008-11-17 | 2011-03-29 | 주식회사 하이닉스반도체 | Method for manufacturing phase change memory device |
| CN116033749A (en) * | 2023-03-27 | 2023-04-28 | 长鑫存储技术有限公司 | Method for preparing semiconductor structure and semiconductor structure |
-
2000
- 2000-06-30 KR KR1020000037019A patent/KR20020002733A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100913331B1 (en) * | 2007-09-20 | 2009-08-20 | 주식회사 동부하이텍 | MOS transistor and method for manufacturing the transistor |
| KR101024260B1 (en) * | 2008-11-17 | 2011-03-29 | 주식회사 하이닉스반도체 | Method for manufacturing phase change memory device |
| CN116033749A (en) * | 2023-03-27 | 2023-04-28 | 长鑫存储技术有限公司 | Method for preparing semiconductor structure and semiconductor structure |
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