KR100282285B1 - Stacked multichip module and manufacturing method thereof - Google Patents

Abstract

The circuit assembly includes semiconductor dies having first and second surfaces that are substantially parallel and opposite each other, and at least one electrical contact mounted on the first surface. A first element having substantially parallel and opposing first and second surfaces and at least one electrical contact mounted on one of the surfaces is mounted on the first surface of the semiconductor die and is mounted on the second surface. It is at least partially supported by the first surface of the semiconductor die. The first element is arranged to expose a semiconductor die electrical contact. The fine conductor having the first and second ends is connected to the semiconductor die electrical contact or the first element electrical contact at the first end. Also disclosed is a method of making such a circuit assembly.

Description

Stacked multichip module and manufacturing method thereof

1 is a cross-sectional view of a multichip module according to the present invention.

2 is a plan view of the multichip module of FIG.

3 is a cross-sectional view of one embodiment of a multichip module according to the invention having three elements.

4 is a cross-sectional view of one variant embodiment of a multichip module according to the invention having three elements.

5 is a cross-sectional view of a second variant embodiment of a multichip module according to the invention having three elements.

6 is a plan view of a third variant embodiment of a multichip module according to the invention with three elements.

7 is a cross-sectional view of a fourth variant embodiment of a multichip module according to the invention with three elements.

8 is a cross-sectional view of one embodiment of a multichip module according to the invention having four elements.

9 is a cross-sectional view of a first variant embodiment of a multichip module according to the invention having four elements.

10 is a cross-sectional view of a second modified embodiment of a multichip module according to the invention having four elements.

FIG. 11 is a cross-sectional view of one embodiment of a multichip module according to the present invention having three elements, one of which has at least one hole or slot therethrough.

12 is a perspective view of the same scale for an element having a through hole or slot.

13 is a perspective view of the same scale for three elements, with one element having a cut cross section.

14 is a cross-sectional view of a variant embodiment of a multichip module according to the invention with three elements, one of which has at least one hole or slot therethrough.

Figure 15 is a plan view of a second variant embodiment of a multichip module according to the invention with three elements, one of which has at least one hole or slot therethrough.

[Field of Invention]

The present invention relates to semiconductor package technology, and more particularly to a semiconductor package comprising a plurality of semiconductor dies and / or substrates.

[Description of Related Technology]

Very large integrated circuit (VLSI) semiconductor dies are usually housed in semiconductor packages. Usually, one semiconductor package contains only one die.

There are three types of conventional semiconductor packages. The molded plastic package includes a lead frame molded into the plastic body. The lead frame is a sheet metal framework with several electrical leads and a die attach pad (DAP) that functions as a principal mounting surface or seating plane. The die may be bonded directly to the DAP or substrate attached to the DAP. The electrical leads provide an electrical path from the inside of the molded plastic to the outside of the plastic. Some common forms of molded plastic packages include plastic chip carriers (PCCs), molded dual inline packages (MDIPs), plastic quad flat packs (PQFPs), and small outs. Small Outline (SO), Shrink Small Outline Package (SSOP), Transistor Outline Package (TO), Very Small Outline Package (VSOP), and Thin Small Thin Small Outline Package (TSOP).

The second conventional semiconductor package form is a cavity package. In the cavity package, a cavity base is included in the hollow housing that functions as the non-mounting surface (or seating surface) on which the die is mounted. Unlike the molded plastic package, the die inherent in the cavity package is surrounded by air. Several electrical leads provide an electrical path from the inside of the housing to the outside of the housing. Some common forms of common packages are ceramic packages, metal cans, plastic packages, and any combination thereof.

A third conventional semiconductor structure is a chip-on-board (COB) assembly. In the COB, the die is bonded directly to the circuit board or the board serving as the non-adhering surface (or seating surface). The die is usually coated and protected with a plastic material. Various types of electrical leads can be used to provide an electrical path from inside the plastic material to the outside of the plastic material.

Although the three conventional semiconductor package types have various different shapes and sizes, each of them includes an insulated surface (or seating surface) on which several electric leads and dies are mounted.

A common method for forming electrical connections between the die and the electrical leads and used in each of the three conventional forms of the package is wire bonding. Wire bonding is a method of forming electrical interconnects between components in separate packages by welding microwires to individual components. Thus, one end of the fine wire conductor is connected to the electrical lead and the other end is connected to the electrical contact on the die. Wire bonding is a common method of interconnecting dies. Capillary design, wire bonding process control, and wire characteristics have been improved to enable the formation of finer pitch bonding.

Often, two or more semiconductor dies are electrically interconnected to provide a single circuit assembly. If there is one die per package paradigm, interconnecting two or more dies requires as much real space as the number of packages. In addition to improving device performance, several attempts have been made to combine two or more dies into a single package to reduce size and weight. In the high density integrated circuit package industry, combining two or more dies into a single package is commonly referred to as a Multi-Chip Module (MCM) or a Multi-Chip Package (MCP). Although the technical terms of multi-chip module and multi-chip package are slightly different in meaning, the two terms are used interchangeably in this specification for the disclosure of the present invention.

The most common MCM is the "side-by-side" MCM. In this case, two or more dies are mounted next to each other (or in parallel to each other) on the all-in-one face of the plastic molding package, the joint package, or the COB package. The die may be mounted directly to the insulated surface or may be mounted on a substrate material that is mounted directly to the insulated surface. The interconnection between the die and the electrical leads is typically formed through wire bonding.

However, the parallel MCM has many disadvantages. Placing the die in parallel on the insulated surface inherent in the molded plastic package or the cavity package is not the best way to use the real area of the package. Such real estate is strictly limited because in most cases the die has to fit some standard form factor that is predesigned for just one die. If the dies are not properly placed, the limit on the real area will limit the number of dies that can be incorporated in the MCM. Furthermore, non-optimal die layouts correspondingly result in sub-optimal wire bonding resulting in cross-wire crossing, long wire lengths and small wire-wire separation. Wire cross over, in which one wire forms a loop on another wire, is very undesirable because short circuiting may occur as a result of molding conditions. Likewise, longer wire lengths and smaller wire-wire separations can pose a critical risk to wire sweeps under rapid molding transition conditions or high resin viscosities.

Another attempt to form an MCM involves placing two or more die on top of each other and then securing a "stack" of die within the package. The manufacture of currently available stacked MCMs is accomplished by first laminating the entire wafer and then cutting the stacked wafer into a lamination die. Thus, each die in a particular stack is the same size.

One drawback of currently available stacked MCMs is that they are all memory devices, and no mixed technology devices in stacked form appear to be available at present. Another disadvantage of stacked MCMs currently available is that they require a single, specialized package. Furthermore, the method used to form electrical interconnects between dies is complex and expensive, and the methods of interconnection currently in use include Controlled Collapse Chip Connection (C ₄ ) and tape automation bonding ( Tape Automated Bonding (TAB).

Controlled Collabs chip connections (C ₄ ), also known as "flip chips," relate to the use of multiple solder bumps on die surfaces that can be face down bonded. have. The effect is improved thermal performance, electrical properties and reworkability. On the other hand, the commonly recognized disadvantages are the need for precise alignment, difficulty in cleaning and overhauling, forming a uniform solder joint height for all connections and having a low coefficient of thermal expansion for substrates with longer thermal cycle life. Point and so on. Furthermore, in order to use C ₄ , all solder bumps and interconnections must be implemented prior to or during the die stacking, that is, no additional interconnect can be formed after the dies are stacked.

Tape automated bonding (TAB) refers to a process in which dies are bonded by metal patterned onto a polymer tape using thermal compression bonding. Next, the attachment to the board or the board is performed by outer lead bonding. Tape automated bonding (TAB) shows only a limited range of applications for MCM. Although TAB has many advantages, it hinders its widespread use, and the need to switch to single-point bonding with large dies to overcome the high start-up costs for custom tapes, the wettability and flatness of polyimide tapes. And so on.

Therefore, there is a demand for being able to overcome the problems of the currently used MCM as a low cost MCM.

[Summary of invention]

The present invention provides a circuit assembly having a semiconductor die having first and second surfaces that are substantially parallel and oppositely facing, and at least one electrical contact mounted on the first surface. do. The first element has substantially parallel and oppositely facing first and second surfaces and is mounted with at least one electrical contact on one of the surfaces, the first element being the first element of the semiconductor die. It is mounted on one surface and is at least partially supported by the first surface of the semiconductor die at the second surface. The first element is arranged such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected to either the semiconductor die electrical contact or the first element electrical contact at the first end.

The method of manufacturing the circuit assembly includes dispensing a semiconductor die on a carrier member having an insulated surface and a plurality of electrical leads. The semiconductor die should be at least partially supported at the second surface by the non-adherent surface. The first element is then disposed on the semiconductor die first surface. The first element must be partially supported at the second surface by the semiconductor die, and the first element must be arranged such that the semiconductor die electrical contacts are exposed.

For a more in-depth understanding of the features and effects of the present invention, reference is made to the accompanying drawings showing embodiments that embody the technical idea of the present invention and the detailed description of the invention.

Detailed Description of the Preferred Embodiments of the Invention

1 illustrates one embodiment of a multichip module 20 in accordance with the present invention. The module 20, or briefly described, the circuit assembly 20 includes a first element 24 "stacked" on the semiconductor die 22. The semiconductor die 22 has first and second surfaces that are substantially parallel and opposite, with at least one electrical contact 32 mounted on the first surface 30. The first element 24 has substantially parallel and oppositely facing first and second surfaces 36, 34, and at least one electrical contact is mounted on the first or second surface 36, 34. have. In the embodiment shown in FIG. 1, the electrical contact 38 is shown mounted on the first surface 36.

The first element 24 may be a semiconductor die or a substrate material. If the first element 24 is a substrate material, the first element 24 can be used as an interconnect medium (described below). The substrate material may be, but is not limited to, a ceramic, metal, silicon, or plastic circuit board (PCB) material. Multilayer ceramic (MLC) substrates are very popular because of the simplicity and ease of use of the substrate materials. Metal substrates provide effects such as toughness (compared to MLC), high strength, low cost and high thermal conductivity. Proper combination of a metal layer, such as copper-inbat-copper or copper-molybdenum-copper, can minimize thermal mismatch between the polymer thin film and the substrate. Some typical base metals include aluminum, copper, copper / molybdenum, copper / tungsten, invar, and cobar.

Copper forms one of the main base metals because of its high thermal conductivity, which tends to minimize thermal stress. The benefits of silicon substrates include ease of application to integrated circuit (IC) fabrication technologies, integration into both active and passive devices, and good thermal matching with other silicon ICs attached to the substrate. The dielectric layer may be either polyimide or SiO ₂ , both of which are standard dielectrics in the manufacture of ICs. On the other hand, a major disadvantage of silicon substrates is that silicon substrates are expensive, their size is limited to wafer size, and silicon has lower thermal conductivity than metal substrates.

The semiconductor die 22 may be mounted on the carrier member 42 and at least partially supported by the non-mounting surface (or seating surface) 40 of the carrier member 42. By "mounted on the carrier member 42" is meant that a particular element (die 22 in this case) is attached directly to the carrier member 42, or a particular element is any other element, laminated element or It is attached to other structures or combinations of structures that adhere directly to the carrier member, such as adhesives.

Generally, the carrier member 42 includes two or more electrical leads 44, 46. In the embodiment shown in FIG. 1, the carrier member 42 is a lead frame, and the non-adhesive surface 40 is a die attach pad (DAP) of the lead frame 42. The electrical leads 44 and 46 are the leads of the lead frame 42. The lead frame 42 is housed in a mold compound 25 of a conventional molded plastic dual inline package (DIP) 26.

One advantage of the present invention is that any one of the three conventional semiconductor packages described above, namely, molded plastic packages, co-packages, and chip-on-board (COB) packages, are stacked elements and dies ( 24, 22). Furthermore, any other package with a hard-on face and electrical leads can likewise be used to contain the stack. With conventional packages, multichip modules can be used immediately in current electrical systems, with little or no modification to the system, as well as cost savings. Thus, although the DIP is shown in FIG. 1, it is obvious that the stacked multichip module according to the present invention may be virtually stored in any semiconductor package.

The semiconductor die 22 may be mounted to the non-adhesive surface 40 by the adhesive material 48. The adhesive 48 may be an epoxy adhesive, soft solder, or other adhesive suitable for mounting the die to the substrate. The adhesive 48 may be electrically conductive or non-conductive. Conductivity is determined by the type of filler incorporated into the gelatin. For example, metal fillers provide good electrical and heat dissipation, while inorganic fillers such as fused silica or diamond mainly improve thermal performance. One example of an adhesive that works particularly well in ceramic packages is part number 11 Staystik, from Staystik, Santa Ana, California, United States. An example of an adhesive with aluminum nitride for high thermal conductivity for plastic packages is part number 282 Staystik.

The first element 24 is also mounted to the carrier member 42. The first element 24 is mounted to be at least partially supported on the second surface by the first surface 30 of the die 22. Furthermore, the first element 24 is arranged to be accessible for exposing the electrical contacts 32 of the die 22 to form electrical connections to the electrical contacts 32. The first element 24 shown in FIG. 1 is fully supported by the die 22, but in another embodiment according to the invention (described below) a second element is associated with the die 22. The first element 24 is partially supported.

The first element 24 is carried by the carrier member 42 by an adhesive material 50 applied to the first surface 30 of the die 22 and the second surface 34 of the first element 24. It can be mounted on. The adhesive 50 may also be a conductive or nonconductive adhesive. The Staystik adhesives described above also work particularly well here.

Wire bonding includes the interconnect portion between the electrical contacts 32, 58 of the die 22, the interconnect portion between the electrical contacts 38, 54 of the first element 24, and the electrical leads 44, 46. It is used to form the electrical connection between them. Since wire bonding is used to form electrical connections between the die and other elements in the stack, the die and other elements expose at least one of the electrical contacts of the die and / or other elements to form a microwire therein. It must be stacked in an accessible manner to establish a connection. As shown in FIG. 1, the first element 24 is smaller than the die 22 so that the electrical contacts 32, of the die 22, when the first element 24 is stacked in the center of the die 22. 58) are exposed. However, the first element 24 need not be smaller than the die 22. That is, if at least one of the electrical contacts 32, 58 is exposed and the first element 24 is disposed on the die 22 in an accessible manner so that a microwire connection is made therein, the first element 24 It may have the same size or larger size as die 22. As described below, there may even be a hole or slot through the first element 24 to expose at least one of the electrical contacts of the die 22.

The particular interconnect portion formed using the wire bonding method may vary depending on the particular use for which the multichip module 20 is to be used. For example, the electrical contact 38 of the first element 24 may be connected to the electrical lead 46 by a microwire conductor 52 connecting the contact 38 directly to the lead 46. Can be. In addition, the electrical contacts can be indirectly connected to the leads using wire bonding. For example, the microwire conductor 56 connects the contact 54 and the contact 58, and then connects the contact 58 and the lead 44 with another microwire conductor 60 to connect the electrical contact 54. ) May be connected to the lead 44.

FIG. 2 shows that the first element 24 is used as an interconnect medium, ie a surface capable of forming various long distance interconnections and line paths. When an element is used as the interconnect media, the element is made from any of the above substrate materials. One example of a long distance interconnect is to use an electrical “strip” contact 68 to connect electrical contact 62 to lead 64. Specifically, the microwire conductor 66 is used to connect the contact 62 to one end of the strip contact 68. Another microwire conductor 70 is used to connect the other end of the strip contact 68 to the lead 64. Thus, when the first element 24 is used as an interconnect medium, the first element 24 is a printed circuit board for transmitting electrical signals from one side of the circuit assembly 20 to the other side. Long strip contacts similar to). Again, the particular interconnect portion that is manufactured will vary depending on the particular use for which the multichip module 20 is used and will depend on that particular use. Moreover, while FIG. 2 illustrates the use of the first element 24 as an interconnect medium, the first element 24 may alternatively be a semiconductor die, in which case from one die to the other. It is apparent that similar interconnect portions can be formed.

The laminated structure shows that expansion and placement in three dimensions (as opposed to parallel placement) can significantly increase the density of the MCM. More die can be stored in a stacked MCM for the same space, which increases the performance, power and versatility of the MCM. The size of the die or substrate is gradually reduced in size to expose and access the bond pads. However, gradually decreasing the size is not necessary as described above.

The stack structure can be varied in various ways to optimize three-dimensional use. The dies can be placed on top of each other, each die being attached to the other die by thermoplastic tape that fits the non-conductive diebonding or footprint of the upper die. The number of dies that can be included in one stack can be limited by the cavity height in the ceramic package or the thickness of the molded plastic package.

Substrates can be stacked into dies to provide interconnect media and line path means between the dies, which helps to rule out long wire bond lengths. Substrates placed on top of other dies do not need to cover the entire die surface. It can also be used as an intermediary means for wiring arrangement to other die arranged side by side on the substrate.

By properly placing the die or die / substrate, wire bonding can be realized at no wire crossover and at an acceptable wire-wire separation level. Furthermore, the lamination die may provide a configuration having a wire bond length that meets standard assembly specifications. Maintaining a short wire bond length minimizes the potential for wire sweep in the forming of the MCM.

The embodiment of the invention shown in FIGS. 1 and 2 illustrates a stacked MCM having only two elements, die 22 and die or substrate 24. However, there is no limit to the number of elements that can be stacked. The present invention is directed to a semiconductor die in which at least one of the elements of the stack is at least one other element on top of the die, wherein at least one electrical contact of the at least one element is exposed to form a wire bonded connection thereon. When the elements are stacked in an accessible manner, they include lamination to any number of elements. Some of the elements of the stack may be controlled by a controlled collapsing chip connection (when the elements are stacked in an accessible manner to expose the electrical contacts of at least one of the at least one element and form a wire bonding connection therein). It should be noted that it may be interconnected using a C ₄ ), or “flip chip” connection.

3 shows another embodiment of the invention with three lamination elements. The multichip module 72 includes three elements 74, 76, 78 mounted on the non-contact surface 80 of the carrier member 82. Each of the elements 74, 76, 78 has a flat, opposite facing surface, and if at least one of the elements 74, 76 is a semiconductor, then each of the elements 74, 76, 78 is a semiconductor die or substrate It may be a material. A first element 74 is mounted to the secured attachment surface 80 by an adhesive 84, a second element 76 is mounted to the first element 74 by an adhesive 86, and a third element. 78 is mounted to the second element 76 by an adhesive 88. The third element 78 must be at least partially supported by the second element 76 and the second element 76 must be at least partially supported by the first element 74. Furthermore, the second element 76 should be arranged to be accessible to expose the electrical contacts 94, 100 of the first element 74 and form a microwire connection therein. The third element 78 can likewise be arranged to be accessible to expose the electrical contacts 96, 102 of the second element 76 and to form a microwire connection therein. Although the elements 76 and 78 are progressively smaller in size, this is not necessary if the elements are arranged to expose at least one of the electrical contacts of the underlying element.

Wire bonding can be used to electrically connect any or all of the contacts 94, 96, 98, 100, 102, 104 to either or both of the electrical leads 106, 108. As shown in FIG. 3, the microwire conductors 110, 112, 114 connect the contacts 94, 96, 98 to the leads 108, and the microwire conductors 116, 118, 120 connect the The contacts 100, 102, 104 are connected to the leads 106.

The carrier member 82 may be any one of the three conventional semiconductor packages described above. For example, the multichip module 122 shown in FIG. 4 has three elements 124, 126 mounted on a carrier member 130 having electrical leads 132 on only one side of the non-adhering surface 134. , 128). The multichip module 144 shown in FIG. 5 includes three elements 146, 148, 150 mounted on the carrier member 152. The carrier member 152 may be a ceramic package or metal can with an electrical lead (not shown) mounted directly below the non-adhering surface 154. 6 is a plan view of a multichip module 156 having three elements 158, 160, 162 mounted on the non-contact surface 164 of the carrier member 166. The carrier member 166 includes electrical leads 168 on all four sides of the carrier member 166.

If the top element is not the only die, any combination of the three elements may be a semiconductor die and / or substrate material. On the other hand, the choice of dyna substrate as well as the particular wire bonding interconnect portion to be formed depends on the particular application in which the multichip module is used. 7 illustrates a multichip module 135 having three elements 136, 138, 140 mounted on a carrier member 142. The first and third elements 136, 140 are semiconductor dies, and the second element 138 is a substrate material.

8 illustrates another embodiment of a multichip module 170 in accordance with the present invention. Four elements 172, 174, 176, 180 are mounted on the non-contact surface 182 of the carrier member 184. Each of the elements 172, 174, 176, 180 has a flat, oppositely facing surface, and when at least one of the elements 172, 174, 176 is a die, the elements 172, 174, 176, 180 are Each may be a semiconductor die or either substrate material. Both second and third elements 174, 176 are supported by first element 172. The fourth element 178 is partially supported by the second element 174 and partially supported by the third element 176. Furthermore, elements 174, 176 are arranged to expose at least one of the electrical contacts of element 172 for wire bonding, and element 178 is an electrical contact of any one of elements 174, 176. At least one of which is arranged to be exposed for wire bonding. Adhesives 186, 188, 190 are used to mount each of the elements 172, 174, 176, 178 to the carrier member 184. Meanwhile, the carrier member 184 may be any type of carrier in the conventional semiconductor package. FIG. 9 illustrates an embodiment basically the same as that shown in FIG. 8 except that the carrier member 192 is in the form seen in a ceramic package or metal can.

10 illustrates another embodiment of a multichip module 193 according to the present invention. Four elements 194, 196, 198, 200 are mounted on the non-contact surface 202 of the carrier member 204. Each of the elements 194, 196, 198, 200 has a flat, oppositely facing surface. The elements 194, 198 are semiconductor dies, and the elements 196, 200 may be semiconductor dies or substrate materials, respectively. The four elements 194, 196, 198, 200 are arranged in two separate stacks 206, 208. The first stack 206 includes a first element 194 mounted on the insulated surface 202 and a second element 196 is at least partially supported by the first element 194. The second stack 208 includes a third element 198 mounted on the non-slip surface 202 and the fourth element 200 is at least partially supported by the third element 198.

11 illustrates another embodiment of a multichip module 210 according to the present invention. Three elements 212, 214, 216 are mounted on the non-contact surface 218 of the carrier member 220. Each of the elements 212, 214, 216 has a flat, opposite facing surface and each of the elements 212, 214, 216 is a semiconductor die or substrate when at least one of the elements 214, 216 is a die. It may be a material. The first element 212 is mounted on the insulated surface 218, the second element 214 is at least partially supported by the first element 212, and the third element 216 is It is at least partially supported by the second element 214. The basic difference between the multichip module 210 and other embodiments described above is that the second element 214 extends through the second element 214 from the first surface 226 to the second surface 228. Or slots 222 and 224.

The purpose of the holes 222, 224 is to expose the electrical contacts 236, 242 of the element 212 and make them accessible to form microwire connections therein. In other words, the elements 214 are arranged in such a way that they can be accessed through the holes 222, 224 by exposing the electrical contacts 236, 242. By using the holes 222, 224 to expose the electrical contacts 236, 242, even though the element 214 is larger than the element 212, the wire bonding interconnect portion between the elements 216, 214, 212. This can be formed. For example, the microwire conductor 230 extends to connect the electrical contact 234 and the electrical contact 236 through the hole 224. As another example, the microwire conductor 238 extends from the electrical contact 240 through the hole 222 to connect with the electrical contact 242. Thus, when the second element 214 is larger than the first element 212 such that the first element 212 is completely covered by the second element 214, the holes 222 and 224 are formed of the first element 212. Allows direct electrical connection between the first element 212 and the third element 216 via a microwire conductor.

One reason that the second element 214 is larger than the first element 212 is that the first surface 226 may be used to form many interconnecting portions between the first and third elements 212, 216. It can accommodate a large amount of circuitry. Usually the second element 214 is a substrate material for use as an interconnect medium. However, the second element 214 may also be a semiconductor die with holes on the die portion without any circuitry.

12 illustrates one way in which holes or slots 244 can be formed through elements having parallel and oppositely facing surfaces. The hole 244 may be of any desired size or shape, for example, the hole 244 may be a small round hole, a long rectangular hole, a square hole, or the like.

13 illustrates a second element 250 sandwiched between a first element 248 and a third element 252. Instead of using holes or slots, the second element 250 provides a cutting portion 254 that allows the microwire conductor 256 to extend from the third element 252 to the first element 248. Have Thus, the cutting portion in any of the above elements can serve for similar purposes of holes or slots.

14 shows a multichip module 258 having three elements 260, 262, 264 mounted on the non-contact surface 266 of the carrier member 268. The second element 262 includes holes 270 and 272. The carrier member 268 is in the form seen in ceramic packages or metal cans. FIG. 15 is a plan view of a multichip module 274 having three elements 276, 278, and 280 mounted on the non-contact surface 282 of the carrier member 284. The carrier member 284 has a shape with an electrical lead 286 on all four surfaces of the non-adhering surface 282. The second element 278 includes four slots 288, 290, 292, 294 extending through the second element 278 to expose the electrical contacts of the first element 276. Thus, the microwire conductor 296 is allowed to extend from the third element 280 through the slot 292 to the first element 276.

Returning to FIG. 1, the method of manufacturing the multichip module 20 begins by applying an adhesive or ductile-solder 48 on the non-contact surface 40 of the carrier member 42. The semiconductor die 22 is then combined onto the adhesive 48 at a pressure of approximately 8-10 pounds per square inch (psi).

The next step is to apply the adhesive or epoxy 50 on the first surface 30 of the die 22. The first element 24 is then dispensed onto the adhesive 50 at a pressure of approximately 3-5 psi. The first element 24 must be at least partially supported by the die 22, on which the first element 24 is laid at least one of the electrical contacts of the die 22, whereby a wire bonding connection is made. It must be arranged to be accessible. The first element 24 may be a semiconductor die or substrate material.

If a second element is needed, an adhesive or epoxy is applied to the first surface 36 of the first element 24 and the second element is combined on the first surface 36. If additional elements are needed, the same step is followed by applying an adhesive or epoxy on the surface of the finally combined element and then combining the other elements on the final element.

After the desired number of elements are mounted on the carrier 42, electrical contacts on the elements such as contacts 32, 38, 54, 58 and electrical leads on the carrier 42, such as leads 44, 46, are wire bonded together. do.

After the wire bonding is completed, the carrier member 42 is sealed in the semiconductor package 26. This step usually involves forming the molding compound 25 around the carrier 42 such that the die and the first elements 22, 24 are completely covered with the molding compound 25 and only the leads 44, 46 are exposed. do. Although the semiconductor package 26 is a DIP, it is obvious that any of the conventional semiconductor packages can be used.

A variant method of manufacturing the multi-chip module 20 begins by assembling the stacked die and the first elements 22, 24 before mounting the preassembled stack on the carrier member 42. In other words, the desired number of elements, such as two, three or four, are first stacked and bonded together with an adhesive. Then, the stack is mounted on the non-adhering surface 40. After the wire bonding interconnect is made, the circuit assembly is sealed in the semiconductor package. This alternative method has the effect that all dies are mounted on the carrier member in a single step rather than individual dies mounted on the carrier member one at a time.

It is obvious that various modifications in the embodiments of the invention described herein can be used to practice the invention as falling within the scope of the invention. The scope of the following claims define the scope of the invention, and the structures and methods falling within the spirit of the scope of the claims are within the scope of the present invention.

Claims (40)

A semiconductor die having first and second surfaces substantially parallel and oppositely facing, and at least one electrical contact disposed on the first surface; first and second surfaces substantially parallel and oppositely facing the first surface; A first substrate interconnect medium having at least one electrical contact disposed thereon, wherein only a passive circuit is mounted thereon, mounted on the semiconductor die first surface and at the second surface by the semiconductor die first surface. A first substrate interconnect medium at least partially supported and disposed such that the semiconductor die electrical contacts are exposed; And a fine wire conductor having first and second ends, wherein the first ends are connected to the substrate interconnect medium electrical contacts. 2. The circuit assembly of claim 1, wherein the second end of the fine wire conductor is connected to the semiconductor die electrical contact. 2. The circuit assembly of claim 1, wherein the circuit assembly further comprises a carrier member having a claim attachment surface and a plurality of electrical leads, wherein the semiconductor die is mounted on the claim attachment surface and at the second surface thereof. At least partly supported by the circuit assembly. 4. The circuit assembly of claim 3, wherein the second end of the fine wire conductor is connected to one of the plurality of electrical leads. 10. The hole of claim 1 wherein the first substrate interconnect medium extends through the first substrate interconnect medium to the second surface of the first substrate interconnect medium to expose the semiconductor die electrical contact. And the fine wire conductor extends through the hole. 2. The circuit assembly of claim 1, further comprising an adhesive disposed between the semiconductor die and the first substrate interconnect medium. 4. The circuit assembly of claim 3, further comprising an adhesive disposed between the non-adhering surface and the semiconductor die. 4. The circuit assembly of claim 3, wherein the carrier member comprises a lead frame and the claim facet comprises a die attach pad. 2. The circuit assembly of claim 1, wherein the circuit assembly further comprises a first element having first and second surfaces substantially parallel and oppositely facing, and at least one electrical contact disposed at one of the surfaces, wherein the first element And an element mounted on the first substrate interconnect medium first surface and supported at least in part by the first substrate interconnect medium first surface on the second surface. 4. The circuit assembly of claim 3, wherein the circuit assembly further comprises a second element having first and second surfaces that are substantially parallel and oppositely facing, wherein the second element is mounted to the claim surface and wherein the claim surface and And a circuit assembly disposed between the semiconductor dies. A semiconductor die having first and second surfaces substantially parallel and oppositely facing and at least one electrical contact disposed at the first surface; A first substrate interconnect medium having substantially parallel and oppositely facing first and second surfaces, comprising: at least one electrical contact disposed on the first substrate interconnect medium first surface, the semiconductor die first Mounted on a surface and at least partially supported by the semiconductor die first surface at a second surface thereof, the first substrate interconnect at a first surface of the first substrate interconnect medium to expose the semiconductor die electrical contacts. A first substrate interconnect medium having holes extending through the medium second surface; And a fine wire conductor having first and second ends, wherein the first end extends through the hole in the first substrate interconnect medium and is connected to the semiconductor die electrical contact. Assembly. 12. The circuit assembly of claim 11, wherein the second end of the fine wire conductor is connected to the first substrate interconnect medium electrical contact. 12. The circuit assembly of claim 11, wherein the circuit assembly further comprises a carrier member having a claim attachment surface and a plurality of electrical leads, wherein the semiconductor die is mounted on the claim attachment surface and at the second surface thereof. At least partly supported by the circuit assembly. The circuit assembly according to claim 13, wherein said second end of said fine wire conductor is connected to one of said plurality of electrical leads. 12. The circuit assembly of claim 11, further comprising an adhesive disposed between the semiconductor die and the first substrate interconnect medium. 14. The circuit assembly of claim 13, further comprising an adhesive disposed between the non-adhering surface and the semiconductor die. 14. The circuit assembly of claim 13, wherein the carrier member comprises a lead frame and the non-attachment surface comprises a die attach pad. 14. The circuit assembly of claim 13, wherein the circuit assembly further comprises a first element having first and second surfaces that are substantially parallel and oppositely facing, wherein at least one electrical contact is disposed on the first element first surface, The first element mounted on a first surface of the first substrate interconnect medium and supported at least in part by the first substrate interconnect medium first surface on the second surface; A circuit assembly, characterized in that arranged to expose the contact. 14. The circuit assembly of claim 13, wherein the circuit assembly further comprises a second element having first and second surfaces that are substantially parallel and oppositely facing, wherein the second element is mounted to the claim mounting surface, And a circuit assembly disposed between the semiconductor dies. A carrier member having a non-adhering surface and a plurality of electrical leads; A semiconductor die having substantially parallel and oppositely facing first and second surfaces, comprising: at least one electrical contact disposed on the semiconductor die first surface; A semiconductor die mounted to a carrier member and supported at least in part by the non-adhering surface at a second surface thereof; And a first substrate interconnect medium for use in line path formation and line interconnection, the first substrate interconnect medium having substantially parallel and oppositely facing surfaces and at least one electrical contact disposed on one of the surfaces, And a first substrate interconnect medium mounted on said semiconductor die first surface and at least partially supported by said semiconductor die first surface at said second surface, said first substrate interconnect medium disposed to expose said semiconductor die electrical contacts. Circuit assembly. 21. The circuit assembly of claim 20, further comprising a fine wire conductor having first and second ends, wherein the first end is connected to the semiconductor die electrical contact. A circuit assembly according to claim 21, wherein said second end of said fine wire conductor is connected to one of said plurality of electrical leads. 22. The apparatus of claim 21, wherein the electrical contact of the first substrate interconnect medium is disposed on the first surface of the first substrate interconnect medium, and the second end of the fine wire conductor is connected to the first substrate interconnect. A circuit assembly connected to a medium electrical contact. 21. The circuit assembly of claim 20, wherein the first substrate interconnect medium has holes extending from the first surface to the second surface to expose the semiconductor die electrical contacts. 21. The apparatus of claim 20, wherein the first substrate interconnect medium electrical contact is disposed on the first surface of the first substrate interconnect medium, and the circuit assembly faces first and second surfaces that are substantially parallel and oppositely facing. A first element having at least one electrical contact disposed on a first surface of the first element, the first element mounted on a first surface of the first substrate interconnect medium and the first surface on the second surface of the first element And a first element at least partially supported by the substrate interconnect medium first surface and arranged to expose the first substrate interconnect medium electrical contact. 21. The apparatus of claim 20, wherein the circuit assembly further comprises a second element having first and second surfaces that are substantially parallel and oppositely facing, wherein the second element is mounted to the carrier member, And a circuit assembly disposed between the semiconductor dies. A circuit assembly manufacturing method comprising: (a) a semiconductor die having substantially parallel and oppositely facing first and second surfaces, and an electrical contact disposed on said first surface, with a non-adhering surface and a plurality of electrical leads Disposing on one carrier member, the semiconductor die being at least partially supported by the non-adhering surface at its second surface; (b) a first having a substantially parallel and oppositely facing first and second surface; A first substrate interconnect medium, comprising: disposing a first substrate interconnect medium on the semiconductor die first surface, the first substrate interconnect medium having electrical contacts disposed on a first surface of the first substrate interconnect medium; A medium is at least partially supported by the semiconductor die at its second surface, and the first substrate interconnect medium is adapted to expose the semiconductor die electrical contacts. Call connection from a medium comprising: a first surface having a hole extending through the first substrate interconnect medium, a second surface; And (c) connecting the first end of the first fine wire conductor to the semiconductor die electrical contact such that the first fine wire conductor extends through the hole in the first substrate interconnect medium. The circuit assembly manufacturing method. 28. The method of claim 27, further comprising connecting a second end of the first fine wire conductor to the first substrate interconnect medium electrical contact. 28. The method of claim 27, further comprising applying an adhesive to the non-adhesive surface of the carrier member before step (a) is performed. 28. The method of claim 27, further comprising applying an adhesive to the first surface of the semiconductor die before step (b) is performed. 28. The method of claim 27, wherein the manufacturing method comprises a first element having first and second surfaces that are substantially parallel and oppositely facing, the first element having an electrical contact disposed on the first surface of the first element. Disposing on the first surface of the substrate interconnect medium, wherein the first element is at least partially supported by the first substrate interconnect medium at the second surface, and the first element is Wherein the first substrate interconnect medium electrical contacts are arranged to expose. 32. The method of claim 31, further comprising connecting a first end of a second fine wire conductor to the first element electrical contact. Disposed on the semiconductor die having first and second surfaces that are substantially parallel and oppositely facing, and electrical contacts disposed on the first surface, and first and second surfaces that are substantially parallel and oppositely facing, and the first surface Disposing a first substrate interconnect medium having a connected electrical contact, the first substrate interconnect medium having only passive circuitry mounted thereon, at least partially by the semiconductor die first surface at the second surface thereof; And is disposed to expose the semiconductor die electrical contacts. 34. The method of claim 33, wherein the fabrication method further comprises disposing the semiconductor die and the first substrate interconnect medium on a carrier member having an insulated mounting surface and a plurality of electrical leads. And at least partly supported by said insisting surface on its second surface. 35. The method of claim 34, further comprising connecting a first end of the first fine wire conductor to one of the electrical contacts. 36. The method of claim 35, further comprising connecting a second end of the first fine wire conductor to one of the carrier member electrical leads. 34. The method of claim 33, further comprising disposing an adhesive between the semiconductor die and the first substrate interconnect medium. 35. The method of claim 34, further comprising disposing an adhesive between the non-adhering surface of the carrier member and the semiconductor die. 34. The method of claim 33, wherein the manufacturing method comprises a second element having first and second surfaces that are substantially parallel and oppositely facing, and electrical contacts disposed on the first surface. Disposing on a surface, wherein the second element is at least partially supported by the first substrate interconnect medium at the second surface, and the second element is the first substrate interconnect medium electrical contact. The circuit assembly manufacturing method, characterized in that arranged to expose. 40. The method of claim 39, further comprising connecting a first end of a second fine wire conductor to the second element electrical contact.