KR100268965B1 - 반도체장치 및 그 제조방법 - Google Patents
반도체장치 및 그 제조방법 Download PDFInfo
- Publication number
- KR100268965B1 KR100268965B1 KR1019970015499A KR19970015499A KR100268965B1 KR 100268965 B1 KR100268965 B1 KR 100268965B1 KR 1019970015499 A KR1019970015499 A KR 1019970015499A KR 19970015499 A KR19970015499 A KR 19970015499A KR 100268965 B1 KR100268965 B1 KR 100268965B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- diffusion layer
- impurity diffusion
- type impurity
- forming
- Prior art date
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP96-105207 | 1996-04-25 | ||
JP8105207A JPH09293790A (ja) | 1996-04-25 | 1996-04-25 | 半導体装置およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR100268965B1 true KR100268965B1 (ko) | 2000-10-16 |
Family
ID=14401230
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019970015499A KR100268965B1 (ko) | 1996-04-25 | 1997-04-25 | 반도체장치 및 그 제조방법 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPH09293790A (ja) |
KR (1) | KR100268965B1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6693001B2 (en) | 1997-03-14 | 2004-02-17 | Renesas Technology Corporation | Process for producing semiconductor integrated circuit device |
US6858484B2 (en) | 2000-02-04 | 2005-02-22 | Hitachi, Ltd. | Method of fabricating semiconductor integrated circuit device |
JP3408463B2 (ja) | 1999-08-17 | 2003-05-19 | 日本電気株式会社 | 半導体装置の製造方法 |
KR20010066327A (ko) * | 1999-12-31 | 2001-07-11 | 박종섭 | 듀얼 게이트전극 제조방법 |
KR100356482B1 (ko) * | 2000-12-22 | 2002-10-18 | 주식회사 하이닉스반도체 | 반도체 소자의 금속 배선 형성 방법 |
KR100514166B1 (ko) * | 2004-01-20 | 2005-09-13 | 삼성전자주식회사 | 상보형 반도체 소자 형성방법 |
JP4917328B2 (ja) * | 2006-02-28 | 2012-04-18 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
-
1996
- 1996-04-25 JP JP8105207A patent/JPH09293790A/ja active Pending
-
1997
- 1997-04-25 KR KR1019970015499A patent/KR100268965B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPH09293790A (ja) | 1997-11-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6124189A (en) | Metallization structure and method for a semiconductor device | |
US5723893A (en) | Method for fabricating double silicide gate electrode structures on CMOS-field effect transistors | |
US6274421B1 (en) | Method of making metal gate sub-micron MOS transistor | |
JP2999172B2 (ja) | 自己整合された局所的相互接続及びコンタクトを行うための製造方法 | |
US6335249B1 (en) | Salicide field effect transistors with improved borderless contact structures and a method of fabrication | |
US6103610A (en) | Integrated circuit structure with dual thickness cobalt silicide layers and method for its manufacture | |
US5933741A (en) | Method of making titanium silicide source/drains and tungsten silicide gate electrodes for field effect transistors | |
US20050130380A1 (en) | Semiconductor device structures including metal silicide interconnects and dielectric layers at substantially the same fabrication level | |
JP2861869B2 (ja) | 半導体装置の製造方法 | |
US6214656B1 (en) | Partial silicide gate in sac (self-aligned contact) process | |
JPH11150268A (ja) | 半導体装置及びその製造方法 | |
US6461951B1 (en) | Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers | |
US20020001935A1 (en) | Method of forming gate electrode in semiconductor device | |
US5882964A (en) | Process for the production of an integrated CMOS circuit | |
JPH09260607A (ja) | 半導体記憶装置の製造方法 | |
US5866459A (en) | Method of fabricating a contact structure for an MOS transistor entirely on isolation oxide | |
KR100268965B1 (ko) | 반도체장치 및 그 제조방법 | |
JPH1187529A (ja) | 集積回路コンタクト | |
US5858846A (en) | Salicide integration method | |
US6204539B1 (en) | Semiconductor apparatus and manufacturing method therefor | |
JP3211374B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
US20030143828A1 (en) | Novel method of fabricating metallic local interconnections that also improves transistor performance | |
JP2000091560A (ja) | 半導体装置及びその製造方法 | |
JPH06204173A (ja) | 半導体装置の製造方法 | |
JP2004273556A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20030708 Year of fee payment: 4 |
|
LAPS | Lapse due to unpaid annual fee |