KR100264520B1 - Method for fabricating bipolar integrated circuit - Google Patents
Method for fabricating bipolar integrated circuit Download PDFInfo
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- KR100264520B1 KR100264520B1 KR1019980024330A KR19980024330A KR100264520B1 KR 100264520 B1 KR100264520 B1 KR 100264520B1 KR 1019980024330 A KR1019980024330 A KR 1019980024330A KR 19980024330 A KR19980024330 A KR 19980024330A KR 100264520 B1 KR100264520 B1 KR 100264520B1
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- metal line
- forming
- contact hole
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000009792 diffusion process Methods 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 230000007547 defect Effects 0.000 description 7
- 239000012535 impurity Substances 0.000 description 4
- 239000005001 laminate film Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명에 의한 바이폴라 직접회로 제조방법은, 반도체 기판 내에 p형 확산저항을 형성하는 공정과; 상기 확산저항 형성부의 상기 기판 표면이 소정 부분 노출되도록, 상기 결과물 상에 (20±3) x (30±3)㎛ 사이즈의 콘택 홀이 구비된 절연막을 형성하는 공정; 및 상기 콘택 홀을 포함한 상기 절연막 상의 소정 부분에 50㎛ 이상의 선폭을 갖는 메탈 라인을 형성하고, 이를 소정 온도에서 열처리하는 공정으로 이루어져, 메탈 라인과 기판간의 접촉 특성을 향상시키기 위하여 열처리 공정을 실시해 주더라도 확산저항이 오픈되는 것을 막을 수 있게 된다.A bipolar integrated circuit manufacturing method according to the present invention comprises the steps of forming a p-type diffusion resistor in a semiconductor substrate; Forming an insulating film having a contact hole having a size of (20 ± 3) × (30 ± 3) μm on the resultant portion so that the substrate surface of the diffusion resistance forming portion is partially exposed; And forming a metal line having a line width of 50 μm or more in a predetermined portion on the insulating film including the contact hole, and heat-treating it at a predetermined temperature, thereby performing a heat treatment process to improve contact characteristics between the metal line and the substrate. Also, the diffusion resistor can be prevented from opening.
Description
본 발명은 바이폴라 집적회로 제조방법에 관한 것으로, 보다 상세하게는 선폭(critical dimension)이 50㎛ 이상인 와이드 메탈 라인이 구비된 소자 제조시 야기되는 확산저항의 오픈(open)을 방지할 수 있도록 한 바이폴라 집적회로 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar integrated circuit, and more particularly, to a bipolar that prevents the opening of diffusion resistance caused when manufacturing a device having a wide metal line having a critical dimension of 50 μm or more. An integrated circuit manufacturing method.
바이폴라 집적회로 제조시에는 불순물이 도핑된 반도체(예컨대, 확산저항)와 메탈 라인 간을 전기적으로 연결하기 위하여, 통상 불순물 이온주입 및 확산 공정을 거쳐 반도체 기판(실리콘 기판) 내부 소정 부분에만 선택적으로 p형 확산저항을 형성한 뒤, 확산저항이 형성된 부분의 기판 표면이 소정 부분 노출되도록 상기 기판 상에 콘택 홀이 구비된 절연막을 형성하고, 콘택 홀을 포함한 절연막 상의 소정 부분에 메탈 라인을 형성한 다음, 메탈 라인과 기판간의 접촉 특성을 향상시키기 위하여 약 500℃의 온도에서 열처리를 실시해 주는 방식으로 공정을 진행하고 있다. 이 경우, 메탈 라인은 Al-0.8(%)Si으로 형성되고, 콘택 홀은 8 x 12㎛의 사이즈로 형성된다.In the manufacture of a bipolar integrated circuit, in order to electrically connect a semiconductor (eg, diffusion resistance) doped with an impurity to a metal line, a p-selective process is performed selectively to a predetermined portion of the semiconductor substrate (silicon substrate) through a process of implanting and diffusing impurities. After forming the type diffusion resistor, an insulating film with a contact hole is formed on the substrate to expose a predetermined portion of the substrate surface of the portion where the diffusion resistance is formed, and a metal line is formed on a predetermined portion on the insulating film including the contact hole. In order to improve the contact characteristics between the metal line and the substrate, the process is performed in a manner that heat treatment is performed at a temperature of about 500 ° C. In this case, the metal line is formed of Al-0.8 (%) Si, and the contact hole is formed in a size of 8 x 12 mu m.
그러나, 이러한 방식을 적용하여 불순물이 도핑된 반도체(예컨대, 확산저항)와 메탈 라인간을 전기적으로 연결할 경우에는 공정 진행 과정에서 다음과 같은 문제가 발생된다.However, when the method is used to electrically connect a semiconductor line (for example, diffusion resistance) doped with impurities with a metal line, the following problem occurs during the process.
일반적으로 열처리 온도가 500℃일 때 기판을 이루는 실리콘이 메탈 라인쪽으로 이동할 수 있는 고용 한계(메탈 라인내로의 실리콘 용해도)는 0.8% 정도이다. 따라서, 메탈 라인이 좁은 선폭을 가질 경우에는 별 문제가 발생되지 않으나, 50㎛ 이상의 선폭을 갖는 와이드한 메탈 라인이 상기에 언급된 작은 사이즈(예컨대, 8 x 12㎛ 사이즈)의 콘택 홀을 통해 실리콘 기판 내의 확산저항과 연결될 경우에는 열처리 공정후 기판내로의 메탈 이동량이 많아지는 많큼 메탈 라인쪽으로의 실리콘 이동량 또한 많아지게 되므로 콘택 저항이 증가되는 현상이 야기될 뿐 아니라 심한 경우 메탈 라인과 실리콘 기판간에 실리콘 적층막이 형성되어져, 확산저항이 오픈되는 불량이 발생되기도 한다.In general, when the heat treatment temperature is 500 ° C, the solid solution limit (silicon solubility in the metal line) that the silicon constituting the substrate can move toward the metal line is about 0.8%. Therefore, there is no problem when the metal line has a narrow line width, but a wide metal line having a line width of 50 μm or more is formed through the contact hole of the small size mentioned above (eg, 8 × 12 μm size). When connected to the diffusion resistance in the substrate, the amount of metal movement into the substrate increases after the heat treatment process, and thus the amount of silicon movement toward the metal line also increases, which causes not only the increase in contact resistance but also severe silicon between the metal line and the silicon substrate. The laminated film is formed, so that a defect that opens the diffusion resistance may occur.
이에 본 발명의 목적은, 와이드 메탈 라인이 구비된 바이폴라 집적회로 제조시, 상기 메탈 라인과 기판 내의 확산저항을 전기적으로 연결시켜 주는 콘택 홀을 기존보다 큰 사이즈로 형성해 주므로써, 확산저항이 오픈되는 불량을 제거할 수 있도록 한 바이폴라 집적회로 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to form a contact hole that electrically connects the diffusion line in the substrate with the metal line to a larger size than before, when manufacturing a bipolar integrated circuit having a wide metal line. The present invention provides a bipolar integrated circuit manufacturing method capable of eliminating defects.
도 1 및 도 2는 본 발명에 의한 와이드 메탈 라인이 구비된 바이폴라 집적회로 제조방법을 도시한 공정수순도이다.1 and 2 are process flowcharts illustrating a method of manufacturing a bipolar integrated circuit having a wide metal line according to the present invention.
상기 목적을 달성하기 위하여 본 발명에서는, 반도체 기판 내에 p형 확산저항을 형성하는 공정과; 상기 확산저항 형성부의 상기 기판 표면이 소정 부분 노출되도록, 상기 결과물 상에 (20±3) x (30±3)㎛ 사이즈의 콘택 홀이 구비된 절연막을 형성하는 공정; 및 상기 콘택 홀을 포함한 상기 절연막 상의 소정 부분에 50㎛ 이상의 선폭을 갖는 메탈 라인을 형성하고, 이를 소정 온도에서 열처리하는 공정으로 이루어진 바이폴라 집적회로 제조방법이 제공된다.In order to achieve the above object, the present invention provides a process for forming a p-type diffusion resistor in a semiconductor substrate; Forming an insulating film having a contact hole having a size of (20 ± 3) × (30 ± 3) μm on the resultant portion so that the substrate surface of the diffusion resistance forming portion is partially exposed; And forming a metal line having a line width of 50 μm or more in a predetermined portion on the insulating film including the contact hole, and heat-treating the same at a predetermined temperature.
상기와 같이 바이폴라 집적회로를 제조할 경우, 와이드 메탈 라인과 확산저항이 (20±3) x (30±3)㎛ 사이즈의 콘택 홀을 통해 서로 전기적으로 연결되므로, 이후 메탈 라인과 기판간의 접촉 특성을 향상시켜 주기 위하여 열처리를 실시해주더라도 확산저항이 오픈되는 불량이 발생하지 않게 된다.When manufacturing a bipolar integrated circuit as described above, since the wide metal line and the diffusion resistance are electrically connected to each other through a contact hole having a size of (20 ± 3) x (30 ± 3) ㎛, the contact characteristics between the metal line and the substrate Even if heat treatment is performed to improve the efficiency, the defect of opening the diffusion resistance does not occur.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
본 발명은, 콘택 홀 사이즈 변경을 통하여 와이드 메탈 라인이 구비된 바이폴라 집적회로 제조시 문제시되던 확산저항의 오픈을 방지할 수 있도록 하는데 주안점을 둔 기술로서, 이를 도 1 및 도 2에 제시된 공정수순도를 참조하여 제 2 단계로 구분하여 살펴보면 다음과 같다. 여기서, 도 1 및 도 2는 와이드 메탈 라인이 구비된 본 발명에 의한 바이폴라 집적회로 제조방법을 나타낸다.The present invention is a technology that focuses on preventing the opening of diffusion resistors, which is a problem when manufacturing a bipolar integrated circuit equipped with a wide metal line by changing a contact hole size, which is illustrated in FIGS. 1 and 2. Referring to the description of the second step as follows. 1 and 2 illustrate a method of manufacturing a bipolar integrated circuit according to the present invention having a wide metal line.
제 1 단계로서, 도 1에 도시된 바와 같이 불순물 이온주입 및 열처리 공정을 이용하여 n형 반도체 기판(실리콘 기판)(10) 내부 소정 부분에 p형의 확산저항(12)을 형성하고, 그 전면에 산화막 재질의 절연막(14)을 형성한 다음, 확산저항(12) 형성부의 기판(10) 표면이 소정 부분 노출되도록 상기 절연막(14)을 식각하여 콘택 홀을 형성한다. 이때, 콘택 홀은 (20±3) x (30±3)㎛ 사이즈로 형성된다.As a first step, as shown in FIG. 1, a p-type diffusion resistor 12 is formed in a predetermined portion inside the n-type semiconductor substrate (silicon substrate) 10 using impurity ion implantation and heat treatment processes, and the front surface thereof. An insulating film 14 made of an oxide film is formed on the insulating film 14, and then the insulating film 14 is etched to expose a predetermined portion of the surface of the substrate 10 of the diffusion resistor 12 forming part to form a contact hole. At this time, the contact hole is formed to a size (20 ± 3) x (30 ± 3) ㎛.
이와 같이, 콘택 홀 사이즈를 기존의 8 x 12㎛ 사이즈에서 (20±3) x (30±3)㎛ 사이즈로 변경시켜 준 것은 열처리 공정 진행후 메탈 라인쪽으로의 실리콘 이동에 의해 야기될 수 있는 불량(예컨대, 콘택 저항이 증가되는 불량이나 혹은 메탈 라인과 실리콘 기판간에 실리콘 적층막이 형성되는 불량) 발생을 제거하기 위함이다.As such, changing the contact hole size from the existing 8 x 12 μm size to the (20 ± 3) x (30 ± 3) μm size defects that may be caused by the silicon movement toward the metal line after the heat treatment process is performed. (Eg, a defect in which contact resistance is increased or a defect in which a silicon laminate film is formed between a metal line and a silicon substrate) is eliminated.
제 2 단계로서, 도 2에 도시된 바와 같이 상기 콘택 홀을 포함한 절연막(14) 상에 Al 재질의 도전성막을 형성하고, 메탈 라인 형성부를 한정하는 감광막 패턴을 마스크로 이용하여 이를 소정 부분 선택식각하여 메탈 라인(16)을 형성한 다음, 메탈 라인(16)과 실리콘 기판(10)간의 접촉 특성을 향상시키기 위하여 500±50℃의 온도 범위내에서 열처리를 실시한다. 열처리 과정에서 콘택 홀 내부에 형성된 메탈 라인(16)의 일부가 Al-0.8(%)Si으로 변화되기는 하나, 이 경우에는 콘택 홀 사이즈가 (20±3) x (30±3)㎛인 관계로 인해 메탈 라인(16)과 기판(10)간에 실리콘 적층막이 형성되는 불량이 발생하지 않게 된다. 이때, 메탈 라인(16)은 (20±3) x (30±3)㎛의 선폭을 가지도록 형성된다.As a second step, as shown in FIG. 2, an Al conductive film is formed on the insulating film 14 including the contact hole, and a predetermined portion is selectively etched using a photosensitive film pattern defining a metal line forming part as a mask. After the metal line 16 is formed, heat treatment is performed in a temperature range of 500 ± 50 ° C. in order to improve contact characteristics between the metal line 16 and the silicon substrate 10. Although part of the metal line 16 formed inside the contact hole is changed to Al-0.8 (%) Si during the heat treatment, in this case, the contact hole size is (20 ± 3) x (30 ± 3) ㎛. Therefore, a defect in which the silicon laminate film is formed between the metal line 16 and the substrate 10 does not occur. At this time, the metal line 16 is formed to have a line width of (20 ± 3) x (30 ± 3) ㎛.
상기와 같이 공정을 진행할 경우, 콘택 홀이 (20±3) x (30±3)㎛의 사이즈를 가지므로, 메탈 라인(16)을 와이드한 선폭을 가지도록 설계하더라도 메탈 라인과 기판간의 접촉부에 실리콘 적층막이 형성되는 것을 막을 수 있게 되어, 확산저항이 오픈되는 현상이 발생하지 않게 된다.When the process is carried out as described above, the contact hole has a size of (20 ± 3) x (30 ± 3) ㎛, even if the metal line 16 is designed to have a wide line width in the contact portion between the metal line and the substrate It is possible to prevent the silicon laminate film from being formed, so that the phenomenon of opening the diffusion resistance does not occur.
이상에서 살펴본 바와 같이 본 발명에 의하면, 와이드 메탈 라인이 구비된 바이폴라 집적회로 제조시, 상기 메탈 라인과 확산저항간을 전기적으로 연결시켜 주는 콘택 홀을 (20±3) x (30±3)㎛ 사이즈로 형성해 주므로써, 메탈 라인과 기판간의 접촉 특성을 향상시키기 위하여 열처리 공정을 실시해 주더라도 확산저항이 오픈되는 것을 막을 수 있게 된다.As described above, according to the present invention, when manufacturing a bipolar integrated circuit having a wide metal line, a contact hole for electrically connecting the metal line and the diffusion resistance is (20 ± 3) x (30 ± 3) ㎛. By forming the size, even if the heat treatment process is performed to improve the contact characteristics between the metal line and the substrate, the diffusion resistance can be prevented from opening.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024330A KR100264520B1 (en) | 1998-06-26 | 1998-06-26 | Method for fabricating bipolar integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980024330A KR100264520B1 (en) | 1998-06-26 | 1998-06-26 | Method for fabricating bipolar integrated circuit |
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| KR100264520B1 true KR100264520B1 (en) | 2000-09-01 |
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