KR100256875B1 - Method for manufacturing thin flim actuated mirror array - Google Patents

Abstract

PURPOSE: A thin-film micromirror array-actuated(TMA) manufacturing method prevents the permeation of a hydrogen fluoride vapor towards an active matrix or an active layer through a supporting layer during the etching process of a sacrificial layer, thereby preventing the damage of the active matrix. CONSTITUTION: An Iso-Cutting process is performed in a bottom electrode layer(129) to separate the respective pixels. A silicide layer composed of a silica or an amorphous silicon is formed in the upper of the Iso-Cut-formed bottom electrode layer(129), and is laminated with the thickness of 0.1 to 1.0 micrometer by using a PECVD method. An Iso-Cut passivation layer(170) is formed by etching to remove the other portion of the silicide layer except for the laminated portion on an Iso-Cut portion(165) of the bottom electrode layer(129). Even though the portion of the first layer(124) under the Iso-Cut portion(165) is damaged, the Iso-Cut passivation layer(170) on the Iso-Cut portion(165) prevents the damage of an active layer or an active matrix(100) including a passivation layer(110).

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method of manufacturing AMA (Actuated Mirror Array), which is a thin film type optical path control device. More specifically, after iso-cutting a lower electrode layer, an iso-cut protective layer made of silica or amorphous silicon is formed on an iso-cut portion. Forming so that the support layer underneath the Iso-Cut site is not damaged during the subsequent etching process, so that when the sacrificial layer is etched, hydrogen fluoride vapor penetrates through the Iso-Cut site into the strained layer or active matrix, The present invention relates to a method for manufacturing a thin film type optical path control device that can prevent the matrix from being damaged.

Optical path modulators or optical light modulators for projecting optical energy onto a screen may be applied to various fields such as optical communication, image processing, and information display devices. An image processing apparatus using such an optical modulator is generally divided into a direct-view image display device and a projection-type image display device according to a method of displaying optical energy on a screen. do.

An example of a direct-view image display device is a CRT (Cathode Ray Tube). The CRT device is called a CRT, which has excellent image quality but increases in weight and volume as the screen is enlarged, leading to an increase in manufacturing cost. There is. Examples of the projection image display apparatus include a liquid crystal display (LCD), a deformable mirror device (DMD), and an AMA. Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, due to the polarity of the light, the light efficiency is low, there is a problem inherent in the liquid crystal material, for example, there is a disadvantage that the response speed is slow and the inside is easy to overheat. In addition, the maximum light efficiency of existing transmission light modulators is limited to a range of 1-2%, requiring dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, its structure and operation principle are simple, and high light efficiency (more than 10% light efficiency) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a brighter and clearer image.

Each actuator of the AMA generates a deformation in accordance with the electric field generated by the applied electric picture signal and the bias signal. As the actuator deforms, each of the mirrors mounted thereon is tilted. Accordingly, the inclined mirrors reflect light incident from the light source at a predetermined angle to form an image on the screen. Piezoelectric materials such as PZT (Pb (Zr, Ti) O ₃ ) or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used as actuators for driving the respective mirrors. The actuator may also be configured as a warping material such as PMN (Pb (Mg, Nb) O ₃ ).

These AMA devices are largely divided into bulk type and thin film type. The bulk optical path control device is disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path adjusting device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode formed therein in an active matrix in which a transistor is embedded, and then processing by a sawing method and installing a mirror thereon. However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the strained layer is slow.

Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed. The thin film type optical path control device is a patent application No. 96-42197 (Applicant's name: thin film type optical path control device that can control the stress of the membrane and a method of manufacturing the same) of the applicant filed a patent application of the Republic of Korea Patent Office on September 24, 1996 Is disclosed.

Figure 1 shows a cross-sectional view of the thin film type optical path control device described in the preceding application. Referring to FIG. 1, the thin film type optical path adjusting device includes an active matrix 1 and an actuator 70 formed on the active matrix 1. The active matrix 1 includes a protective layer 10 stacked on the active matrix 1 and the drain pad 5, and an etch stop layer 15 stacked on the protective layer 10.

One side of the actuator 70 is in contact with a portion where the drain pad 5 is formed at the bottom of the etch stop layer 15, and the other side is formed with a membrane 25 and a membrane 25 horizontally through the air gap 60. ), The lower electrode 30 stacked on top of the bottom electrode, the strained layer 35 stacked on top of the lower electrode 30, the upper electrode 40 stacked on top of the strained layer 35, and the strained layer 35. The lower electrode may be formed in the via hole 45 formed from one side of the drain pad 5 through the strained layer 35, the lower electrode 30, the membrane 25, the etch stop layer 15, and the protective layer 10. 30 and via pads 50 formed to be connected to each other.

Hereinafter, the manufacturing method of the above-mentioned thin film type optical path control apparatus is demonstrated with reference to drawings.

2A to 2E are manufacturing process diagrams of the apparatus shown in FIG. Referring to FIG. 2A, an M × N (M, N is an integer) MOS transistor (not shown) is formed therein and is formed on top of an active matrix 1 having a drain pad 5 extending from the drain of the transistor. The protective layer 10 is formed. The protective layer 10 is formed of phosphorus silicate glass (PSG) to have a thickness of about 1.0 to about 2.0 μm using a chemical vapor deposition (CVD) method. The protective layer 10 protects the active matrix 1 in which the MOS transistor is embedded during the subsequent process.

An etch stop layer 15 is formed on the passivation layer 10. The etch stop layer 15 is formed to have a thickness of about 1000 to 2000 kPa using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 15 prevents the active matrix 1 and the protective layer 10 from being etched and damaged during the subsequent etching process.

The sacrificial layer 20 is stacked on the etch stop layer 15. The sacrificial layer 20 is formed of phosphorus silicate glass (PSG) having a high concentration of phosphorus (PG) to have a thickness of about 1.0 to 3.0 µm using the atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 20 covers the upper portion of the active matrix 1 in which the transistor is embedded, the flatness of the surface thereof is very poor. Therefore, the surface of the sacrificial layer 20 is planarized by polishing using a spin on glass (SOG) method or a chemical mechanical polishing (CMP) method. Subsequently, a portion of the sacrificial layer 20 is etched to expose a portion where the drain pad 5 is formed below the etch stop layer 15.

Referring to FIG. 2B, the membrane 25 is stacked on the exposed etch stop layer 15 and the sacrificial layer 20 to have a thickness of about 0.1 to 1.0 μm. The membrane 25 is formed of silicon carbide (SiC) using a plasma enhanced CVD (PECVD) method.

The lower electrode 30 is stacked on the membrane 25. The lower electrode 30 is laminated with a metal such as platinum (Pt) or platinum-tantalum (Pt-Ta) so as to have a thickness of about 500 to 2000 kW using a sputtering method. Subsequently, the lower electrode 30 is iso-cutted so as to apply an independent first signal (image signal) for each pixel.

Referring to FIG. 2C, a strained layer 35 is stacked on the lower electrode 30. The strained layer 35 is formed by forming a piezoelectric material such as PZT or PLZT to have a thickness of about 0.01 to 1.0 탆 using a sol-gel method, and then forming the strained layer 35. The piezoelectric material to be constituted is subjected to a heat treatment by a rapid heat treatment (RTA) method to phase change. In the strained layer 35, a second signal (bias signal) is applied to the upper electrode 40, and a first signal is applied to the lower electrode 30, according to a potential difference between the upper electrode 40 and the lower electrode 30. It is deformed by the generated electric field.

The upper electrode 40 is stacked on top of the strained layer 35. The upper electrode 40 is formed of a metal having electrical conductivity and reflectivity, such as aluminum or platinum, to have a thickness of about 500 to 2000 kPa using a sputtering method. The second signal is applied to the upper electrode 40 through a common electrode line (not shown) from the outside. Since the upper electrode 40 has both electrical conductivity and reflectivity at the same time, not only the function of the bias electrode generating the electric field but also the function of the mirror reflecting light incident from the light source is performed.

Next, the upper electrode 40 is patterned into a predetermined pixel shape. At this time, a stripe 55 is formed on a part of the upper electrode 40. The stripe 55 uniformly operates the upper electrode 40 so that the light incident from the light source is diffusely reflected at the boundary between the portion of the upper electrode 40 that is deformed and the portion that is not deformed due to the deformation of the strained layer 35. prevent. Subsequently, the strained layer 35 and the lower electrode 30 are each patterned into a predetermined pixel shape.

Referring to FIG. 2D, the strained layer 35, the lower electrode 30, the membrane 25, the etch stop layer 15, and the protective layer 10 from one side of the strained layer 35 to the top of the drain pad 5. Are sequentially etched to form the via holes 45 from the strained layer 35 to the drain pad 5. Subsequently, a metal such as tungsten (W) or titanium (Ti) is deposited in the via hole 45 using a sputtering method to deposit the via contact 50 so as to connect the lower electrode 30 to the drain pad 5. Form.

Subsequently, the membrane 25 is patterned to have a predetermined pixel shape. Then, the sacrificial layer 20 is removed using hydrogen fluoride (HF) vapor to form an air gap 60 at the position of the sacrificial layer 20, and then cleaning and drying are performed to complete the AMA device. .

In the above-described manufacturing method of the thin film type optical path adjusting device, the first signal is applied to the lower electrode 30 from the outside through the MOS transistor, the drain pad 5, and the via contact 50 embedded in the active matrix 1. . In addition, a second signal is applied to the upper electrode 40 from the outside through the common electrode line to generate an electric field between the upper electrode 40 and the lower electrode 30. Due to this electric field, the strained layer 35 stacked between the upper electrode 40 and the lower electrode 30 causes deformation. The strained layer 35 contracts in a direction perpendicular to the generated electric field, and the actuator 70 including the strained layer 35 is bent in a direction opposite to the direction in which the membrane 25 is formed. Therefore, the upper electrode 40 on the actuator 70 also inclines in the same direction. Light incident from the light source is reflected by the upper electrode 40 at a predetermined angle, and then is projected onto the screen to form an image.

However, in the above-described method for manufacturing a thin film type optical path control device, the Iso of the lower electrode is subjected to etching processes for patterning thin films constituting the actuator such as the upper electrode, the strain layer, the lower electrode, and the membrane into predetermined pixel shapes, respectively. The membrane and the etch stop layer under the cut are continuously damaged. This will be described in more detail with reference to the drawings.

3 is a plan view showing an enlarged Iso-Cut part in the above-described thin film type optical path control device. Referring to FIG. 3, an Iso-Cut region (see A) is performed when etching processes for patterning the upper electrode 40, the strained layer 35, the lower electrode 30, and the membrane 25 into predetermined pixel shapes, respectively. ) Is exposed without being covered with photoresist. In this case, the etching process needs to proceed sufficiently to ensure that the upper electrode 40, the strained layer 35, the lower electrode 30, and the membrane 25 each have an accurate pixel shape. During the process, the membrane 25 and the etch stop layer 15 under the Iso-Cut region A, which are not protected by the photoresist, are excessively etched and damaged. When the membrane 25 and the etch stop layer 15 are damaged in this manner, when the sacrificial layer 20 is removed using hydrogen fluoride (HF) vapor, the hydrogen fluoride vapor is released from the membrane 25 and the etch stop layer. Penetrating through the damaged portion of (15) there is a problem that the deformation layer on the membrane 25, the protective layer 10 under the etch stop layer 15 and the active matrix (1) containing the transistor is damaged.

Accordingly, it is an object of the present invention to form an Iso-Cut protective layer composed of silica or amorphous silicon on the Iso-Cut site after iso-cutting the lower electrode layer so that the support layer under the Iso-Cut site is damaged during the subsequent etching process. To prevent the hydrogen fluoride vapor from penetrating through the support layer toward the strained layer or the active matrix when the sacrificial layer is etched, thereby preventing the strained layer or the active matrix from being damaged. To provide.

1 is a cross-sectional view of a thin film type optical path adjusting device described in the applicant's prior application.

2A to 2E are manufacturing process diagrams of the apparatus shown in FIG.

3 is an enlarged plan view of an iso-cut portion of the device described in the preceding application.

4 is a plan view of a thin film type optical path control apparatus according to the present invention.

FIG. 5 is a cross-sectional view taken along line B′B ′ of the apparatus shown in FIG. 4.

6A to 6D are manufacturing process diagrams of the apparatus shown in FIG. 5.

<Explanation of symbols for main parts of drawing>

100: Active matrix 105: Drain pad

110: protective layer 115: etching prevention layer

120: victim layer 125: support layer

130: lower electrode 135: deformation layer

140: upper electrode 145: empty hole

150: free contact 160: air gap

165 ： Iso-Cut site 170 ： Iso-Cut protective layer

200: Actuator

In order to achieve the above object, the present invention provides a method comprising the steps of providing an active matrix having M x N (M, N is an integer) MOS transistor embedded therein and a drain pad extending from the drain of the transistor; Forming a protective layer and an etch stop layer on top of the active matrix; Forming a first layer on top of the etch stop layer; Forming a lower electrode layer on the first layer, and then forming an Iso-Cut region that separates each pixel on the lower electrode layer; Forming a silicide layer on the lower electrode layer; Patterning a silicide layer to form an Iso-Cut protective layer on an Iso-Cut region of the lower electrode layer; Forming a second layer and an upper electrode layer on the lower electrode layer and the Iso-Cut protective layer; Patterning the upper electrode layer and the second layer to form an upper electrode and a strain layer; Patterning the lower electrode layer to form a lower electrode; And it provides a method of manufacturing a thin film type optical path control device comprising the step of forming a support layer by patterning the first layer.

According to the manufacturing method of the thin film type optical path control apparatus according to the present invention, after performing Iso-Cutting to separate each pixel on the lower electrode layer, a silicide layer composed of silica (SiO ₂ ) or amorphous silicon is formed and silicide The layer is patterned to leave only the Iso-Cut portion of the lower electrode layer to form an Iso-Cut protective layer. The deformation layer on the upper portion of the Iso-Cut portion or the active matrix under the damage is damaged during the etching process in which the thin films constituting the actuator are formed into predetermined pixel shapes by the Iso-Cut protective layer formed on the Iso-Cut portion among the lower electrodes. Will not receive. Therefore, when etching the sacrificial layer, it is possible to prevent hydrogen fluoride vapor from penetrating through the support layer toward the strained layer or the active matrix to damage the strained layer or the active matrix.

Hereinafter, a method of manufacturing a thin film type optical path control apparatus according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view showing a thin film type optical path adjusting device according to the present invention, and FIG. 5 is a cross-sectional view taken along line B′B ′ of the device shown in FIG. 4.

4 and 5, the thin film type optical path adjusting device according to the present invention includes an active matrix 100 and an active matrix 100 in which M × N (M and N are integers) P-MOS transistors (not shown) are embedded. And an actuator 200 formed on the upper portion of the 100.

The active matrix 100 includes a drain pad 105 extending from the drain of the P-MOS transistor, a protective layer 110 formed on the active matrix 100 and the drain pad 105, and an upper portion of the protective layer 110. The anti-etching layer 115 is formed on.

The actuator 200 may include a support layer having one side contacting a portion of the etch stop layer 115 at which a drain pad 105 is formed below, and the other side of the actuator 200 disposed horizontally with a lower portion of the active matrix 100 via the air gap 160 ( 125, the lower electrode 130 formed on the support layer 125, the Iso-Cut protective layer 170, the Iso-Cut protective layer 170, and the lower electrode 130 formed on one side of the lower electrode 130. The strained layer 135 formed on the top of the strained layer 135, the upper electrode 140 formed on the strained layer 135, and the strained layer 135, the lower electrode 130, and the support layer 125 from one side of the strained layer 135. The via contact 150 formed to connect the lower electrode 130 and the drain pad 105 to the via hole 145 formed to the upper portion of the drain pad 105 through the etch stop layer 115 and the protective layer 110. Include. The support layer 125 performs the function of a membrane supporting the actuator of the thin film type optical path adjusting device described in the previous application.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the drawings.

6A to 6D show a manufacturing process diagram of the thin film type optical path control device shown in FIG. In Figs. 6A to 6D, the same reference numerals are used for the same members as in Fig. 5.

Referring to FIG. 6A, a drain pad 105 is formed on an active matrix 100 having M × N P-MOS transistors (not shown). The drain pad 105 is formed using a metal such as tungsten or titanium. The drain pad 105 serves to apply the first signal (image signal) transmitted from the outside through the MOS transistor embedded in the active matrix 100 to the lower electrode 130 through the via contact 150.

The protection layer 110 is formed on the drain pad 105 and the active matrix 100 to protect the active matrix 100 having the MOS transistors embedded therein. The protective layer 110 is formed of a silicate glass (PSG) to have a thickness of about 1.0 to about 2.0 μm using a chemical vapor deposition (CVD) method.

An etch stop layer 115 is stacked on the passivation layer 110. The etch stop layer 115 is formed to have a thickness of about 1000 to 2000 GPa using nitride by low pressure chemical vapor deposition (LPCVD). The etch stop layer 115 prevents the active matrix 100 and the protective layer 110 from being etched and damaged during the subsequent etching process.

The sacrificial layer 120 is stacked on the etch stop layer 115. The sacrificial layer 120 is formed of phosphorus silicate glass (PSG) containing phosphorus (P) at a high concentration to have a thickness of about 1.0 to 3.0 μm by the atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 120 covers the upper portion of the active matrix 100 in which the transistor is embedded, the flatness of the surface thereof is very poor. Accordingly, the surface of the sacrificial layer 120 is planarized by polishing the surface by using spin on glass (SOG) or chemical mechanical polishing (CMP). Subsequently, a portion of the sacrificial layer 120 where the drain pad 105 is formed is etched to expose a portion of the etch stop layer 115 to form a position at which an anchor, which is a support of the actuator 200, is formed.

The first layer 124 is stacked on the exposed etch stop layer 115 and the sacrificial layer 120. The first layer 124 is formed to have a thickness of about 0.01 to 1.0 탆 using a low pressure chemical vapor deposition (LPCVD) method such as nitride or metal. The first layer 124 is later patterned with a support layer 125 that supports the actuator 200.

Referring to FIG. 6B, the lower electrode layer 129 is formed on the first layer 124 using a metal such as platinum, tantalum, or platinum-tantalum having excellent electrical conductivity. The lower electrode layer 129 is laminated to have a thickness of about 0.01 to 1.0 µm using a sputtering method. Subsequently, the lower electrode layer 129 is iso-cutted so as to apply an independent first signal (image signal) for each pixel.

As described above, a silicide layer 169 made of silica (SiO ₂ ) or amorphous silicon is formed on the lower electrode layer 129 having the Iso-Cut 165 formed thereon. The silicide layer 169 is laminated so as to have a thickness of about 0.01 to 1.0 탆 using the PECVD method.

Referring to FIG. 6C, the Iso-Cut protective layer 170 is etched by removing the remaining portions except the parts stacked on the Iso-Cut portion 165 of the lower electrode layer 129 at the bottom of the silicide layer 169. Form. In the present invention, since the Iso-Cut protective layer 170 is formed on the Iso-Cut region 165 as described above, when the thin films constituting the actuator 200 are subsequently patterned into predetermined pixel shapes, respectively, Iso- Even if a portion of the first layer 124 under the cut portion 165 is etched and damaged, the active matrix 100 including the strained layer 135 or the protective layer 110 due to the Iso-Cut protective layer 170. ) Can be prevented from being damaged. Accordingly, when the sacrificial layer 120 is etched, hydrogen fluoride (HF) vapor penetrates through the support layer 125 toward the strained layer 135 or the active matrix 100, and thus the strained layer 135 or the active matrix 100. Can be prevented from being damaged.

The second layer 134 is stacked on the lower electrode layer 129 and the Iso-Cut protective layer 170. The second layer 134 is formed using a piezoelectric material such as PZT or PLZT so as to have a thickness of 0.1 to 1.0 mu m, preferably about 0.4 mu m. The second layer 134 is formed using a sol-gel method, a sputtering method, or a chemical vapor deposition (CVD) method. Preferably, the second layer 134 is formed of PZT using the sol-gel method. Subsequently, the piezoelectric material constituting the second layer 134 is heat-treated to undergo a phase change by using a rapid heat treatment (RTA) method. The second layer 134 is later patterned into the strained layer 135.

The upper electrode layer 139 is stacked on the second layer 134. The upper electrode layer 139 is formed of a metal having electrical conductivity and reflectivity such as aluminum, silver, or platinum so as to have a thickness of about 0.01 to 1.0 탆 using a sputtering method. The upper electrode layer 139 is later patterned with the upper electrode 140 to which a second signal (bias signal) is applied.

Referring to FIG. 6D, the upper electrode layer 139 is patterned to form an upper electrode 140 having a predetermined pixel shape. At this time, when the actuator 200 causes deformation in a part of the upper electrode 140, the light incident from a light source (not shown) is deformed in the upper electrode 140 so that the upper electrode 140 is uniformly operated. As the layer 135 is deformed, stripes (not shown) are formed to prevent diffuse reflection at the boundary between the deformed and undeformed portions. The second signal is applied to the upper electrode 140 through a common electrode line (not shown) from the outside. Subsequently, the second layer 134 is patterned to form a strained layer 135 having a pixel shape larger than that of the upper electrode 140, and then the lower electrode layer 129 is patterned to be wider than the strained layer 135. A lower electrode 130 having a pixel shape of an area is formed. The first signal transmitted from the outside is applied to the lower electrode 130. Therefore, when the second signal is applied to the upper electrode 145 and the first signal is applied to the lower electrode 135, an electric field is generated according to the potential difference between the upper electrode 145 and the lower electrode 135. The deformation layer 140 causes deformation.

Subsequently, the strained layer 135, the lower electrode 130, the first layer 124, the etch stop layer 115, and the protective layer 110 are sequentially formed from one side of the strained layer 135 to an upper portion of the drain pad 105. The via holes 145 are formed by etching. Therefore, the via hole 145 is formed from one side of the strained layer 135 to the top of the drain pad 105. In addition, a via contact 150 may be formed by depositing a metal having electrical conductivity such as tungsten (W), aluminum, or titanium (Ti) in the via hole 145 using a sputtering method. The via contact 150 connects the drain pad 105 and the lower electrode 130. Therefore, the first signal applied from the outside is applied to the lower electrode 130 through the transistor, the drain pad 105, and the via contact 150 embedded in the active matrix 100. Subsequently, the first layer 124 is patterned to form the support layer 125 having a predetermined pixel shape having a larger area than the lower electrode 130.

In addition, the sacrificial layer 120 is etched using hydrogen fluoride (HF) vapor to form an air gap 160 at the position of the sacrificial layer 120, and then a rinse and dry treatment is performed. Complete the AMA device.

In the above-described thin film type optical path control apparatus according to the present invention, the first signal transmitted from the outside is the lower electrode 130 through the MOS transistor, the drain pad 105 and the via contact 150 embedded in the active matrix 100. Is applied to. At the same time, a second signal is applied to the upper electrode 140 through the common electrode line to generate an electric field according to a potential difference between the upper electrode 140 and the lower electrode 130. Due to this electric field, the deformation layer 135 formed between the upper electrode 140 and the lower electrode 130 causes deformation. The strained layer 135 contracts in a direction orthogonal to the generated electric field, whereby the actuator 200 is bent upward at a predetermined angle. Since the upper electrode 140, which also functions as a mirror that reflects light, is formed on the actuator 200, the upper electrode 140 is inclined together with the actuator 200. Accordingly, the upper electrode 140 reflects the light incident from the light source at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

According to the manufacturing method of the thin film type optical path control apparatus according to the present invention, after Iso-Cutting the lower electrode layer, Iso-Cut protective layer composed of silica or amorphous silicon is formed on the Iso-Cut site, Iso-Cut during the subsequent etching process Ensure that the support layer below the site is not damaged. Therefore, when etching the sacrificial layer, hydrogen fluoride vapor can penetrate through the support layer toward the strained layer or the active matrix, thereby preventing the active matrix including the strained or protective layer from being damaged.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art can understand that the present invention can be variously modified and changed without departing from the spirit and scope of the present invention. There will be.

Claims (2)

Providing an active matrix having M × N (M, N is an integer) embedded therein and having a drain pad extending from the drain of the transistor; Forming a protective layer and an etch stop layer on the active matrix; Forming a first layer on the etch stop layer; Forming a lower electrode layer on the first layer, and then forming an Iso-Cut region for separating each pixel on the lower electrode layer; Depositing silica (SiO ₂ ) or amorphous silicon on the lower electrode layer; Patterning the deposited silica or amorphous silicon to form an Iso-Cut protective layer on an Iso-Cut region of the lower electrode layer; Forming a second layer and an upper electrode layer on the lower electrode layer and the Iso-Cut protective layer; Patterning the upper electrode layer and the second layer to form an upper electrode and a strain layer; Patterning the lower electrode layer to form a lower electrode; And And patterning the first layer to form a support layer. The method of claim 1, wherein the depositing silica or amorphous silicon on the lower electrode layer is performed using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.

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