KR100252543B1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR100252543B1
KR100252543B1 KR1019950066152A KR19950066152A KR100252543B1 KR 100252543 B1 KR100252543 B1 KR 100252543B1 KR 1019950066152 A KR1019950066152 A KR 1019950066152A KR 19950066152 A KR19950066152 A KR 19950066152A KR 100252543 B1 KR100252543 B1 KR 100252543B1
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layer
well
polysilicon layer
barrier metal
forming
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KR970053092A (en
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임재은
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Abstract

PURPOSE: A method for manufacturing semiconductor devices is provided to prevent generation of defects due to damage of a gate oxide film by intervening a TiN barrier metal layer between a polysilicon layer and a metal silicide film. CONSTITUTION: A method for manufacturing semiconductor devices forms an N well(2) and a P well(3) on one side and other side of a semiconductor substrate(1). A device separation film(4) defining an active region is formed at a device separation region between the N well(2) and the P well(3). A gate oxide film and a polysilicon layer(6) is sequentially formed on the entire structure. P and N-type impurities are injected into the polysilicon layer(6) on the N and P wells(2,3). The first metal silicide film(7A) pattern is formed only on the N type polysilicon layer(6B). A barrier metal layer is formed on the entire structure. By forming the second metal silicide film(7A) pattern only on the P type polysilicon layer(6A), the first stack structure of the P-type polysilicon layer(6B)/the barrier metal layer(8)/the second metal silicide film(7B) is formed on the N well(2) and the second stack structure of the N type polysilicon layer(6B)/the first metal silicide film(7A)/the barrier metal layer(8) is formed on the P well(3). The first and second stack structures are patterned to form P-type and N type gate electrodes(10A,10B), respectively. The first and second stack structures coexist in the gate electrode included in a boundary of the N well and the P well. The gate electrode has a dual gate electrode(10C) to which the barrier metal layer(8) is connected.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

제1a도 내지 제1d도는 본 발명에 따른 반도체소자의 제조 공정도.1A to 1D are manufacturing process diagrams of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 반도체 기판 2 : N웰1 semiconductor substrate 2 N well

3 : P웰 4 : 소자분리 산화막3: P well 4: Device isolation oxide film

5 : 게이트 산화막 6 : 다결정실리콘층5 gate oxide film 6 polysilicon layer

6A : P+다결정실리콘층 6B : N+다결정실리콘층6A: P + polycrystalline silicon layer 6B: N + polycrystalline silicon layer

7A : 제1W-실리사이드막 7B : 제2W-실리사이드막7A: 1W-silicide film 7B: 2W-silicide film

8 : 장벽금속층 9 : 감광막패턴8: barrier metal layer 9: photosensitive film pattern

10A : P+게이트전극 10B : N+게이트전극10A: P + gate electrode 10B: N + gate electrode

10C : 이중게이트전극 11A : P형소오스/드레인영역10C: double gate electrode 11A: P-type source / drain region

12 : 층간절연막 11B : N형소오스/드레인영역12: interlayer insulating film 11B: N-type source / drain region

본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 N웰과 P웰을 연결시키는 이중(N+P/+) 게이트 구조를 가지는 상보형 모스 전계효과 트랜지스터(Complementary Metal Oxide Semiconductor Field Effect Transistor : 이하 CMOS FET라 칭함)에서 게이트 전극을 폴리사이드 구조로 형성할 때, P+다결정실리콘층과 금속실리사이드막사이에 TiN층을 개재시켜 B불순물의 게이트산화막으로의 확산을 방지하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, a complementary metal oxide semiconductor field effect transistor having a double (N + P / +) gate structure connecting an N well and a P well (hereinafter CMOS) When the gate electrode is formed of a polyside structure in a FET, a TiN layer is interposed between the P + polysilicon layer and the metal silicide layer to prevent diffusion of B impurities into the gate oxide layer, thereby improving process yield and device operation reliability. A method for manufacturing a semiconductor device that can be improved.

반도체소자에서 게이트전극의 상측에 마스크 산화막을 형성하고, P+게이트전극 형성을 위한 이온주입으로 상기 마스크 산화막내로 한 후, 열처리하여 F에 의한 게이트산화막의 열화를 방지하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다.In the semiconductor device, a mask oxide film is formed on the upper side of the gate electrode, into the mask oxide film by ion implantation for forming a P + gate electrode, and then thermally treated to prevent deterioration of the gate oxide film by F, thereby improving process yield and device operation reliability. A method for manufacturing a semiconductor device that can be improved.

일반적으로 반도체 회로를 구성하는 트랜지스터의 기능에서 가장 중요한 기능은 전류구동능력이며, 이를 고려하여 모스 전계효과 트랜지스터(Metal Oxide Semiconductor Field Effect Transister : 이하 MOS FET라 칭함)의 채널폭을 조정한다.In general, the most important function in the function of the transistors constituting the semiconductor circuit is the current driving capability, and in consideration of this, the channel width of the metal oxide field effect transistor (hereinafter referred to as MOS FET) is adjusted.

가장 널리 쓰이는 MOSFET는 게이트전극으로 불순물이 도핑된 폴리실리콘층을 사용하고, 소오스/드레인전극은 반도체기판상에 불순물이 도핑된 확산영역이 사용된다.The most widely used MOSFET uses a polysilicon layer doped with an impurity as a gate electrode, and a diffusion region doped with impurities on a semiconductor substrate is used as a source / drain electrode.

또한 1기가(Giga) DRAM 이상의 고집적화된 DRAM 소자 및 로직(Logic) 소자에서는 이중(N+/P+) 게이트 구조를 형성하게 되는데, 이러한 이중 게이트 구조는 각각의 이온 주입에 의해 형성된다.In addition, in highly integrated DRAM devices and logic devices of 1 Giga DRAM or more, a double (N + / P +) gate structure is formed, which is formed by each ion implantation.

종래 기술에 따른 이중 게이트 구조를 가지는 반도체소자의 제조방법을 살펴보면 다음과 같다.Looking at the manufacturing method of a semiconductor device having a double gate structure according to the prior art as follows.

먼저, 반도체기판상에 서로 인접한 N웰 및 P웰을 형성하고, 소자분리 산화막을 형성하고, 상기 활성영역으로 예정되어있는 반도체기판상에 게이트산화막을 형성하고, 다결정실리콘층과 금속실리사이드막 패턴으로된 폴리사이드 구조의 게이트전극을 형성하되, N 및 P웰상에는 숏채널 효과를 방지하고, Vt조절을 용이하게 하기 위하여 각각 P 및 N형 불순물이 고농도로 포함된 P+ 및 N+형 다결정실리콘층패턴으로 형성한다.First, N wells and P wells adjacent to each other are formed on a semiconductor substrate, an isolation layer is formed, a gate oxide film is formed on a semiconductor substrate intended as the active region, and a polysilicon layer and a metal silicide layer pattern are formed. P + and N + type polysilicon layer patterns containing high concentrations of P and N type impurities, respectively, to form a gate electrode having a polyside structure, to prevent short channel effects on the N and P wells, and to facilitate Vt control. Form.

그후, 상기 P형 N형의 소오스/드레인 영역과 스페이서를 형성한다.Thereafter, the P-type N-type source / drain regions and spacers are formed.

여기서 상기 이중 게이트 구조의 반도체 소자의 제조방법은 공정의 단순화를 위하여 N+/P+형의 소오스/드레인 영역 이온주입 공정시 N+/P+ 게이트전극 도핑을 동시에 실시할 수도 있다.In the method of manufacturing the double gate semiconductor device, the N + / P + gate electrode doping may be simultaneously performed during the N + / P + type source / drain region ion implantation process to simplify the process.

상기와 같은 N+/P+ 게이트전극 형성을 위한 불순물 이온주입은 N형의 경우에는 인(P)이나 As을 사용하며, P형의 경우에는 B나 BF2를 사용한다.In the impurity ion implantation for forming the N + / P + gate electrode as described above, phosphorus (P) or As is used in the case of the N type, and B or BF 2 is used in the case of the P type.

특히 P+다결정실리콘층 게이트전극의 도핑은 불소(Fluorine)에 의한 게이트 산화막의 열화를 방지하기 위해 BF2보다는 B을 사용하게 되는데, B은 질량이 가벼워 이온주입 채널링(implant channeling) 현상이 심각하며, 폴리사이드 구조의 게이트전극에서는 금속실리사이드막이 불순물 확산의 통로 역할을 하여 반대 도전형 게이트로 확산되어 문턱전압을 변화시키는 등 불량 발생이 증가하는 문제점이 있다.In particular, the doping of the P + polysilicon layer gate electrode uses B rather than BF 2 to prevent deterioration of the gate oxide film caused by fluorine, and B is light in mass, which causes severe ion implantation channeling. In the gate electrode having a polyside structure, the metal silicide layer serves as a passage for impurity diffusion and diffuses to the opposite conductivity type gate to change the threshold voltage.

본 발명은 상기와 같은 문제점들을 해결하기 위한 것으로서, 본 발명의 목적은 P+폴리사이드 구조의 게이트전극에서 다결정실리콘층과 금속실리사이드막의 사이에 장벽금속층을 개재시켜 피형 도전층에서의 불순물이 실리사이드막을 통하여 반대 게이트로 확산되어 소자의 문턱전압의 변화를 방지하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to interpose a barrier metal layer between a polysilicon layer and a metal silicide layer in a gate electrode having a P + polyside structure, so that impurities in the conductive layer are formed through the silicide layer. The present invention provides a method of manufacturing a semiconductor device that can be diffused to the opposite gate to prevent a change in the threshold voltage of the device, thereby improving process yield and reliability of device operation.

상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은, N+/P+이중 게이트 구조를 구비하는 CMOS의 반도체소자의 제조방법에 있어서,In the semiconductor device manufacturing method according to the present invention for achieving the above object, in the semiconductor device manufacturing method of CMOS having a N + / P + double gate structure,

반도체기판의 일측 및 타측에 N웰 및 P웰을 형성하는 공정과,Forming an N well and a P well on one side and the other side of the semiconductor substrate,

상기 반도체기판의 N웰 및 P웰 사이의 소자분리 영역에 활성영역을 정의하는 소자분리막을 형성하는 공정과,Forming an isolation layer defining an active region in the isolation region between the N well and the P well of the semiconductor substrate;

상기 구조의 전표면에 게이트산화막을 형성하는 공정과,Forming a gate oxide film on the entire surface of the structure;

상기 구조의 전표면에 다결정실리콘층을 형성하는 공정과,Forming a polysilicon layer on the entire surface of the structure;

상기 N 및 P웰 상의 다결정실리콘층을 각각 P 및 N형 불순물을 주입하는 공정과,Implanting P and N type impurities into the polysilicon layers on the N and P wells, respectively;

상기 N형 다결정실리콘층 상부에만 제1금속실리사이드막 패턴을 형성하는 공정과,Forming a first metal silicide film pattern only on the N-type polysilicon layer;

상기 구조의 전표면에 장벽금속층을 형성하는 공정과,Forming a barrier metal layer on the entire surface of the structure;

상기 P형 다결정실리콘층 상측에만 제2금속실리사이드막을 형성함으로써 상기 엔웰 상부에 피형 다결정실리콘층/장벽금속층/제2금속실리사이드막의 제1적층구조를 형성하는 동시에 상기 피웰 상부에 엔형 다결정실리콘층/제1금속실리사이드막/장벽금속층 제2적층구조를 형성하는 공정과,By forming a second metal silicide layer only on the upper side of the P-type polysilicon layer, a first stacked structure of a polysilicon layer, a barrier metal layer, and a second metal silicide layer is formed on the top of the enwell, and at the same time, an en-type polysilicon layer / agent on the top of the pwell 1 process of forming a metal silicide film / barrier metal layer second laminated structure,

상기 제1적층구조와 제2적층구조를 패터닝하여 엔웰 및 피웰 상에 각각 피형과 엔형의 게이트전극을 형성하되, 엔웰과 피웰의 경계부에 구비되는 게이트전극은 제1적층구조와 제2적층구조가 상존하며 장벽금속층이 연결되는 이중게이트전극을 구비하는 것을 특징으로 한다.Patterning the first stacked structure and the second stacked structure to form a gate electrode having a shape and a shape on the enwell and the pewell, respectively, wherein the gate electrode provided at the boundary between the enwell and the pewell has a first stacked structure and a second stacked structure. It is characterized in that it comprises a double gate electrode that is present and connected to the barrier metal layer.

이하, 본 발명에 따른 반도체소자의 제조방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

제1a도 내지 제1d도는 본 발명에 따른 반도체소자의 제조 공정도로서, 이중 폴리사이드 게이트 구조의 예이다.1A to 1D are manufacturing process diagrams of a semiconductor device according to the present invention, which is an example of a double polyside gate structure.

먼저, 반도체기판(1)상의 일측 및 타측에 각각 N웰(2) 및 P웰(3)을 형성하고, 반도체기판(1)에서 소자 분리 영역으로 예정되어있는 부분상에 소자분리 산화막(4)을 형성한 후, 상기 반도체기판(1)상에 게이트 산화막(5)을 형성하고, 상기 구조의 전표면에 화학기상증착(chemical vapor deposition; 이하 CDV라 칭함) 방법으로 다결정실리콘층(6)을 형성한다.First, N wells 2 and P wells 3 are formed on one side and the other side of the semiconductor substrate 1, respectively, and the element isolation oxide film 4 is formed on the portion of the semiconductor substrate 1, which is intended as an element isolation region. After forming the gate oxide film 5 on the semiconductor substrate 1, the polysilicon layer 6 is formed on the entire surface of the structure by chemical vapor deposition (hereinafter referred to as CDV). Form.

그다음 N 및 P웰(2),(3) 상측의 다결정실리콘층(6)에 각각 P 및 N형 불순물을 주입하여 P 및 N형 다결정실리콘층(6A),(6B)을 형성한 후, 상기 N+다결정실리콘층(6B)상에 금속, 예를 들어 제1W-실리사이드막(7A) 패턴을 형성하고, 상기 구조의 전표면에 불순물 확산을 방지하기 위한 장벽금속층(8)을 TiN으로 스퍼터링이나 화학기상증착(chemical vapor deposition; 이하 CVD라 칭함) 방법으로 50∼200Å 정도 두께로 형성한다.(제1a도 참조).Then, P and N type impurities are implanted into the polycrystalline silicon layer 6 on the upper sides of the N and P wells 2 and 3 to form the P and N type polysilicon layers 6A and 6B, respectively. Sputtering or chemically forming a barrier metal layer 8 with TiN to form a metal, for example, a first W-silicide film 7A pattern on the N + polycrystalline silicon layer 6B, and to prevent impurity diffusion on the entire surface of the structure. It is formed to a thickness of about 50 to 200 kPa by chemical vapor deposition (hereinafter referred to as CVD) (see FIG. 1a).

그후, 전체표면상부에 제2W-실리사이드막(7B)을 형성하고, 상기 N웰(2)상측의 제2W-실리사이드막(7B)상에 P웰 마스크용의 감광막패턴(9)을 형성한다.(제1b도 참조).Thereafter, a second W-silicide film 7B is formed over the entire surface, and a photoresist film pattern 9 for a P well mask is formed on the second W-silicide film 7B above the N well 2. (See also Figure 1b).

그 다음 상기 감광막패턴(9)에 의해 노출되어 있는 P웰(3) 상측의 제2W-실리사이드막(7B)을 제거하고 상기 감광막패턴(9)을 제거한다.(제1C도 참조).Then, the second W-silicide film 7B on the upper side of the P well 3 exposed by the photoresist pattern 9 is removed and the photoresist pattern 9 is removed (see also FIG. 1C).

그후, 상기 N웰(2)상의 제2W-실리사이드막(7B)-장벽금속층(8)-P+다결정실리콘층(6A)과, P웰(3)상의 장벽금속층(8)-제1W-실리사이드막(7A)-N+다결정실리콘층(6B)을 각각의 패터닝 마스크를 사용하여 순차적으로 패턴닝하여 제2W-실리사이드막(7B) 패턴-장벽금속층(8) 패턴-P+다결정실리콘층(6A) 패턴으로된 P+게이트전극(10A)과, 장벽금속층(8) 패턴-제1W-실리사이드막(7A)패턴-N+다결정실리콘층(6B) 패턴으로된 N+게이트전극(10B)을 형성한다. 이때 소자분리 산화막(4)상에는 이중게이트(10C)가 형성된다.Thereafter, the second W-silicide film 7B on the N well 2-the barrier metal layer 8-P + polycrystalline silicon layer 6A and the barrier metal layer 8 on the P well 3-the first W-silicide film The (7A) -N + polysilicon layer 6B was sequentially patterned using respective patterning masks to form the second W-silicide film 7B pattern-barrier metal layer 8 pattern-P + polycrystalline silicon layer 6A pattern. A P + gate electrode 10A and an N + gate electrode 10B having a barrier metal layer 8 pattern-first W-silicide film 7A pattern-N + polysilicon layer 6B pattern. At this time, the double gate 10C is formed on the device isolation oxide film 4.

여기서, 상기 제1a도에서 형성된 장벽금속층(8)은 엔웰과 피웰의 경계부에 형성되어 서로 다른 적층구조를 갖는 게이트전극(10A,10B)에 연결되어 있는 이중게이트전극(10C)을 구비한다.Here, the barrier metal layer 8 formed in FIG. 1a includes a double gate electrode 10C formed at the boundary between the enwell and the pewell and connected to the gate electrodes 10A and 10B having different stacked structures.

그리고, 상기 장벽금속층(8)은 상기 피형 게이트전극(10A)의 피형 다결정실리콘층(6A)에 함유된 불순물이 금속실리사이드막인 제2W-실리사이드막(7B)으로 확산되는 현상을 방지하며, 상기 이중게이트(10C)에서는 상기 제2W-실리사이드막(7B)으로 확산된 불순물 또는 상기 제2W-실리사이드막(7B)이 함유하는 불순물이 엔형 게이트 전극(10B)의 제1W-실리사이드막(7A)으로 확산되는 현상을 방지하는 역할을 한다.In addition, the barrier metal layer 8 prevents impurities contained in the polycrystalline silicon layer 6A of the gate electrode 10A from being diffused into the second W-silicide layer 7B, which is a metal silicide layer. In the double gate 10C, impurities diffused into the second W-silicide layer 7B or impurities contained in the second W-silicide layer 7B are transferred to the first W-silicide layer 7A of the N-type gate electrode 10B. It prevents the phenomenon of spreading.

그 다음, 상기 게이트전극(10A),(10B)들 양측의 반도체기판(1)에 각각 P 및 N형 불순물로 소오스/드레인 영역(11A),(11B)을 형성한 후, 상기 구조의 전표면에 층간절연막(12)을 산화막과 비.피.에스.지(Boro Phospho Silicate Glass; BPSG)의 적층 구조로 형성한다.(제1d도 참조).Then, source / drain regions 11A and 11B are formed on the semiconductor substrate 1 on both sides of the gate electrodes 10A and 10B with P and N-type impurities, respectively, and then the entire surface of the structure. The interlayer insulating film 12 is formed in a lamination structure of an oxide film and Boro Phospho Silicate Glass (BPSG) (see also FIG. 1D).

이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 제조방법은 P+폴리사이드의 구조의 P+게이트전극에서 다결정실리콘층과 금속실리사이드막의 사이에 TiN 장벽금속층을 개재시켜 다결정실리콘층에 도핑된 불순물이 금속실리사이드막을 통해 확산되는 통로를 원천적으로 제거하여 게이트 산화막 손상에 따른 불량 발생을 방지하였으므로, 문턱전압 변화가 방지되고, 게이트 산화막의 열화를 방지하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, an impurity doped in a polysilicon layer is formed by interposing a TiN barrier metal layer between a polysilicon layer and a metal silicide layer in a P + gate electrode having a P + polyside structure. Since the path diffused through the silicide film is eliminated at the source to prevent defects caused by damage to the gate oxide film, the threshold voltage can be prevented and the gate oxide film can be prevented from deteriorating, thereby improving process yield and device operation reliability. have.

Claims (4)

N+/P+이중 게이트 구조를 구비하는 CMOS의 반도체소자의 제조방법에 있어서,In the method for manufacturing a semiconductor device of CMOS having an N + / P + double gate structure, 가지는 반도체기판의 일측 및 타측에 N웰 및 P웰을 형성하는 공정과,Forming an N well and a P well on one side and the other side of the semiconductor substrate; 상기 반도체기판의 N웰 및 P웰 사이의 소자분리 영역에 활성영역을 정의하는 소자분리막을 형성하는 공정과,Forming an isolation layer defining an active region in the isolation region between the N well and the P well of the semiconductor substrate; 상기 구조의 전표면에 게이트 산화막을 형성하는 공정과,Forming a gate oxide film on the entire surface of the structure; 상기 구조의 전표면에 다결정실리콘층을 형성하는 공정과,Forming a polysilicon layer on the entire surface of the structure; 상기 N 및 P웰 상의 다결정실리콘층을 각각 P 및 N형 불순물을 주입하는 공정과,Implanting P and N type impurities into the polysilicon layers on the N and P wells, respectively; 상기 N형 다결정실리콘층 상부에만 제1금속실리사이드막 패턴을 형성하는 공정과,Forming a first metal silicide film pattern only on the N-type polysilicon layer; 상기 구조의 전표면에 장벽금속층을 형성하는 공정과,Forming a barrier metal layer on the entire surface of the structure; 상기 P형 다결정실리콘층 상측에만 제2금속실리사이드막을 형성함으로써 상기 엔웰 상부에 피형 다결정실리콘층/장벽금속층/제2금속실리사이드막의 제1적층구조를 형성하는 동시에 상기 피웰 상부에 엔형 다결정실리콘층/제1금속실리사이드막/장벽금속층 제2적층구조를 형성하는 공정과,By forming a second metal silicide layer only on the upper side of the P-type polysilicon layer, a first stacked structure of a polysilicon layer, a barrier metal layer, and a second metal silicide layer is formed on the top of the enwell, and at the same time, an en-type polysilicon layer / agent on the top of the pwell 1 process of forming a metal silicide film / barrier metal layer second laminated structure, 상기 제1적층구조와 제2적층구조를 패터닝하여 엔웰 및 피웰 상에 각각 피형과 엔형의 게이트전극을 형성하되, 엔웰과 피웰의 경계부에 구비되는 게이트전극은 제1적층구조와 제2적층구조가 상존하며 장벽금속층이 연결되는 이중게이트전극을 구비하는 공정을 포함하는 반도체소자의 제조방법.Patterning the first stacked structure and the second stacked structure to form a gate electrode having a shape and a shape on the enwell and the pewell, respectively, wherein the gate electrode provided at the boundary between the enwell and the pewell has a first stacked structure and a second stacked structure. A method of manufacturing a semiconductor device comprising a step of having a double gate electrode that is present and connected to the barrier metal layer. 제1항에 있어서,The method of claim 1, 상기 장벽금속층이 TiN으로 형성되어 있는 것을 특징으로 하는 반도체 소자의 제조방법.And the barrier metal layer is formed of TiN. 제1항에 있어서,The method of claim 1, 상기 장벽금속층이 50∼200Å두께로 형성되어 있는 것을 특징으로 하는 반도체소자의 제조방법.A method for manufacturing a semiconductor device, wherein the barrier metal layer is formed to have a thickness of 50 to 200 GPa. 제1항에 있어서,The method of claim 1, 상기 금속실리사이드막이 W-실리사이드로 형성되는 것을 특징으로 하는 반도체소자의 제조방법.The metal silicide layer is formed of W-silicide.
KR1019950066152A 1995-12-29 1995-12-29 Method for manufacturing semiconductor device KR100252543B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6165470A (en) * 1984-09-07 1986-04-04 Hitachi Ltd Semiconductor ic device
JPS6254467A (en) * 1985-09-02 1987-03-10 Seiko Epson Corp Semiconductor device
JPH0194664A (en) * 1987-10-05 1989-04-13 Nec Corp Field-effect transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6165470A (en) * 1984-09-07 1986-04-04 Hitachi Ltd Semiconductor ic device
JPS6254467A (en) * 1985-09-02 1987-03-10 Seiko Epson Corp Semiconductor device
JPH0194664A (en) * 1987-10-05 1989-04-13 Nec Corp Field-effect transistor

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