JPH0194664A - Field-effect transistor - Google Patents
Field-effect transistorInfo
- Publication number
- JPH0194664A JPH0194664A JP25207087A JP25207087A JPH0194664A JP H0194664 A JPH0194664 A JP H0194664A JP 25207087 A JP25207087 A JP 25207087A JP 25207087 A JP25207087 A JP 25207087A JP H0194664 A JPH0194664 A JP H0194664A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- high melting
- layer
- point metal
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 13
- 238000002844 melting Methods 0.000 claims abstract description 36
- 230000008018 melting Effects 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 150000004767 nitrides Chemical class 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 4
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 abstract description 11
- 239000010937 tungsten Substances 0.000 abstract description 11
- -1 tungsten nitride Chemical class 0.000 abstract description 6
- 239000011248 coating agent Substances 0.000 abstract description 5
- 238000000576 coating method Methods 0.000 abstract description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 abstract 17
- 239000011229 interlayer Substances 0.000 abstract 1
- 238000005755 formation reaction Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910021341 titanium silicide Inorganic materials 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電界効果トランジスタに関し、特にＭＯ３型構
造の電界効果トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor, and in particular to a field effect transistor of MO3 type structure.
従来のＭＯ３型電界効果トランジスタは、半導体基板上
に設けたゲート絶縁膜上に設けた高融点金属又は不純物
をドープした多結晶シリコン層と高融点金属層を積層し
て設けたゲート電極と、前記ゲート電極に隣接する前記
半導体基板中に設けたソース及びドレイン領域とを備え
て構成される。A conventional MO3 type field effect transistor includes a gate electrode formed by laminating a polycrystalline silicon layer doped with a high melting point metal or an impurity and a high melting point metal layer provided on a gate insulating film provided on a semiconductor substrate, and The semiconductor device includes source and drain regions provided in the semiconductor substrate adjacent to the gate electrode.
上述した従来のＭＯ３型電界効果トランジスタは、ゲー
ト電極の高融点金属が、ゲート絶縁膜の酸化シリコン膜
やゲート電極の一部を構成する多結晶シリコン膜或いは
ゲート電極を被覆して設けられた眉間絶縁膜め酸化シリ
コン膜と直接接触する構造となっているので、高融点金
属と酸化シリコン膜の反応によるゲート絶縁膜の絶縁耐
圧の劣化やリーク電流の増加やトランジスタのしきい電
圧の変動が生じたり、高融点金属と多結晶シリコンの硅
化物形成によるゲート電極の抵抗率の増加や硅化物形成
反応時に発生する応力によるゲート絶縁膜の薊れやクラ
ックのため、デバイスの信頼性の低下が生じたり、高融
点金属と酸化シリコン膜の反応による眉間絶縁膜の絶縁
耐圧の劣化やリーク電流の増加が生じるという問題点が
ある。The above-mentioned conventional MO3 type field effect transistor has a high melting point metal of the gate electrode, which is formed by covering the silicon oxide film of the gate insulating film, the polycrystalline silicon film forming part of the gate electrode, or the gate electrode. Since the structure is such that the insulating film is in direct contact with the silicon oxide film, the reaction between the high melting point metal and the silicon oxide film may cause deterioration of the dielectric strength of the gate insulating film, increase in leakage current, and fluctuations in the threshold voltage of the transistor. In addition, the reliability of the device decreases due to an increase in the resistivity of the gate electrode due to the formation of silicide between the high-melting point metal and polycrystalline silicon, and divots and cracks in the gate insulating film due to the stress generated during the silicide formation reaction. Another problem is that the dielectric strength of the glabellar insulating film deteriorates and leakage current increases due to the reaction between the high melting point metal and the silicon oxide film.
本発明の電界効果トランジスタは、半導体基板上に設け
たゲート絶縁膜上に設けたゲート電極を有する電界効果
トランジスタにおいて、前記ゲート電極が前記ゲート絶
縁股上に設けた高融点金属窒化物層と、前記高融点金属
窒化物層の上に設けた高融点金属層又は高融点金属硅化
物層と、前記高融点金属層又は高融点金属硅化物層の表
面を被覆した高融点金属窒化物層又は高融点金属酸化物
層を有するように構成される。The field effect transistor of the present invention is a field effect transistor having a gate electrode provided on a gate insulating film provided on a semiconductor substrate, wherein the gate electrode includes a high melting point metal nitride layer provided on the gate insulating crotch; A high melting point metal layer or high melting point metal silicide layer provided on the high melting point metal nitride layer, and a high melting point metal nitride layer or high melting point coating the surface of the high melting point metal layer or high melting point metal silicide layer. The metal oxide layer is configured to have a metal oxide layer.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例を説明するための半導体
チップの断面図である。FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.
第１図に示すように、−導電型のシリコン基板１の主表
面に設けて素子形成領域を区画するフィールド絶縁膜２
と、前記素子形成領域の表面に設けたゲート絶縁膜３と
、ゲート絶縁膜３の上に障壁層として厚さ５０ｎｍの窒
化ダンゲステン層４及び厚さ０．４μｍのタングステン
層５を積層して設は且つタングステン層５の表面を被覆
して設けた厚さ５０’ｎｍの窒化タングステン層６から
なるゲート電極と、該ゲート電極及びフィールド絶縁膜
２に整合して前記素子形成領域内に設けた逆導電型拡散
層のソース領域７及びドレイン領域８により電界効果ト
ランジスタが構成される。As shown in FIG. 1, a field insulating film 2 is provided on the main surface of a -conductivity type silicon substrate 1 to partition an element formation region.
A gate insulating film 3 is provided on the surface of the element formation region, and a 50 nm thick dungesten nitride layer 4 and a 0.4 μm thick tungsten layer 5 are laminated as barrier layers on the gate insulating film 3. and a gate electrode made of a tungsten nitride layer 6 with a thickness of 50 nm provided covering the surface of the tungsten layer 5; The source region 7 and drain region 8 of the conductive type diffusion layer constitute a field effect transistor.
第２図は本発明の第２の実施例を説明するための半導体
チップの断面図である。FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.
第２図に示すように、−導電型のシリコン基板１の主表
面に設けて素子形成領域を区画するフィールド絶縁膜２
と、前記素子形成領域の表面に設けたゲート絶縁膜３と
、ゲート絶縁膜３の上に厚さ５０〜１５０ｎｍの多結晶
シリコン層９と障壁層としての厚さ５０ｎｍの窒化タン
グステン層４と厚さ０．２μｍの硅化チタン層１ｏとを
順次積層して設は且つ硅化チタン層１０の表面を被覆し
て設けた窒化チタン層１１からなるゲート電極と、該ゲ
ート電極及びフィールド絶縁膜２に整合して前記−素子
形成領域内に設けた逆導電型拡散層のソース領域７及び
ドレイン領域８により電界効果トランジスタが構成され
る。この場合、トランジスタのしきい電圧を従来の多結
晶シリコンゲートのＭＯ３型電界効果トランジスタと同
じ値に設定できるという効果がある。As shown in FIG. 2, a field insulating film 2 is provided on the main surface of a -conductivity type silicon substrate 1 to partition an element formation region.
, a gate insulating film 3 provided on the surface of the element formation region, a polycrystalline silicon layer 9 with a thickness of 50 to 150 nm on the gate insulating film 3, a tungsten nitride layer 4 with a thickness of 50 nm as a barrier layer, and a A gate electrode consisting of a titanium nitride layer 11 formed by sequentially laminating a titanium silicide layer 1o with a thickness of 0.2 μm and covering the surface of the titanium silicide layer 10 is aligned with the gate electrode and the field insulating film 2. A field effect transistor is constituted by the source region 7 and drain region 8 of the reverse conductivity type diffusion layer provided in the above-mentioned element forming region. In this case, there is an advantage that the threshold voltage of the transistor can be set to the same value as that of a conventional polycrystalline silicon gate MO3 field effect transistor.
以上説明したように本発明は、ゲート電極を構成する高
融点金属層の周囲を高融点金属窒化物層で被覆すること
により、ゲート絶縁膜又は眉間絶縁膜とゲート電極の高
融点金属層が反応して生ずる絶縁耐圧の劣化や、トラン
ジスタのしきい電圧変動を抑制し、半導体装置の信頼性
を向上させるという効果を有する。As explained above, in the present invention, by coating the periphery of the high melting point metal layer constituting the gate electrode with a high melting point metal nitride layer, the gate insulating film or the glabella insulating film and the high melting point metal layer of the gate electrode react. This has the effect of suppressing the deterioration of the dielectric strength voltage caused by this and the fluctuation of the threshold voltage of the transistor, thereby improving the reliability of the semiconductor device.
第１図及び第２図は本発明の第１及び第２の実施例を説
明するための半導体チップの断面図である。
１・・・シリコン基板、２・・・フィールド絶縁膜、３
・・・ゲート絶縁膜、４・・・窒化タングステン層、５
・・・タングステン層、６・・・窒化タングステン層、
７・・・ソース領域、８・・ニドレイン領域、９・・・
多結晶シリコン層、１０・・・硅化チタン層、１１・・
・窒化チタン層。1 and 2 are cross-sectional views of a semiconductor chip for explaining first and second embodiments of the present invention. 1... Silicon substrate, 2... Field insulating film, 3
...gate insulating film, 4...tungsten nitride layer, 5
... Tungsten layer, 6... Tungsten nitride layer,
7... Source region, 8... Nidrain region, 9...
Polycrystalline silicon layer, 10...Titanium silicide layer, 11...
・Titanium nitride layer.
Claims (1)
電極を有する電界効果トランジスタにおいて、前記ゲー
ト電極が前記ゲート絶縁膜上に設けた高融点金属窒化物
層と、前記高融点金属窒化物層の上に設けた高融点金属
層又は高融点金属硅化物層と、前記高融点金属層又は高
融点金属硅化物層の表面を被覆した高融点金属窒化物層
又は高融点金属酸化物層を有することを特徴とする電界
効果トランジスタ。In a field effect transistor having a gate electrode provided on a gate insulating film provided on a semiconductor substrate, the gate electrode includes a high melting point metal nitride layer provided on the gate insulating film, and a high melting point metal nitride layer provided on the gate insulating film. A high melting point metal layer or a high melting point metal silicide layer provided above, and a high melting point metal nitride layer or a high melting point metal oxide layer covering the surface of the high melting point metal layer or high melting point metal silicide layer. A field effect transistor featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25207087A JPH0194664A (en) | 1987-10-05 | 1987-10-05 | Field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25207087A JPH0194664A (en) | 1987-10-05 | 1987-10-05 | Field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0194664A true JPH0194664A (en) | 1989-04-13 |
Family
ID=17232131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25207087A Pending JPH0194664A (en) | 1987-10-05 | 1987-10-05 | Field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0194664A (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01265542A (en) * | 1988-04-15 | 1989-10-23 | Toshiba Corp | Semiconductor device |
| EP0849806A2 (en) * | 1996-12-19 | 1998-06-24 | Texas Instruments Incorporated | Improvements in or relating to semiconductor devices having tungsten nitride sidewalls |
| KR100232196B1 (en) * | 1996-04-04 | 1999-12-01 | 김영환 | Method of manufacturing semiconductor device |
| KR100252543B1 (en) * | 1995-12-29 | 2000-04-15 | 김영환 | Method for manufacturing semiconductor device |
| JP2000332259A (en) * | 1999-03-17 | 2000-11-30 | Semiconductor Energy Lab Co Ltd | Wiring material, semiconductor device with wiring using the same and manufacture of the semiconductor device |
| JP2001007110A (en) * | 1999-06-22 | 2001-01-12 | Semiconductor Energy Lab Co Ltd | Wiring material, semiconductor device with wiring using the same and manufacture thereof |
| US6265297B1 (en) | 1999-09-01 | 2001-07-24 | Micron Technology, Inc. | Ammonia passivation of metal gate electrodes to inhibit oxidation of metal |
| US6432803B1 (en) | 1998-12-14 | 2002-08-13 | Matsushita Electric Industrial Co., Inc. | Semiconductor device and method of fabricating the same |
| US6458714B1 (en) | 2000-11-22 | 2002-10-01 | Micron Technology, Inc. | Method of selective oxidation in semiconductor manufacture |
| EP1786037A2 (en) * | 1999-04-12 | 2007-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| US7816191B2 (en) | 1999-06-29 | 2010-10-19 | Semiconductor Energy Laboratory Co., Ltd. | Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof |
| US7906429B2 (en) | 1999-06-22 | 2011-03-15 | Semiconductor Energy Laboratory Co., Ltd. | Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof |
| JP2012124508A (en) * | 2012-01-26 | 2012-06-28 | Semiconductor Energy Lab Co Ltd | Semiconductor device, liquid crystal module, electronic equipment, and wiring |
| JP2012160737A (en) * | 2012-03-08 | 2012-08-23 | Toshiba Corp | Method of manufacturing semiconductor device |
| US9045831B2 (en) | 1999-07-22 | 2015-06-02 | Semiconductor Energy Laboratory Co., Ltd. | Wiring and manufacturing method thereof, semiconductor device comprising said wiring, and dry etching method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60147163A (en) * | 1984-01-11 | 1985-08-03 | Seiko Epson Corp | Semiconductor device |
| JPS6213075A (en) * | 1985-07-10 | 1987-01-21 | Nec Corp | Semiconductor device |
-
1987
- 1987-10-05 JP JP25207087A patent/JPH0194664A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60147163A (en) * | 1984-01-11 | 1985-08-03 | Seiko Epson Corp | Semiconductor device |
| JPS6213075A (en) * | 1985-07-10 | 1987-01-21 | Nec Corp | Semiconductor device |
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01265542A (en) * | 1988-04-15 | 1989-10-23 | Toshiba Corp | Semiconductor device |
| KR100252543B1 (en) * | 1995-12-29 | 2000-04-15 | 김영환 | Method for manufacturing semiconductor device |
| KR100232196B1 (en) * | 1996-04-04 | 1999-12-01 | 김영환 | Method of manufacturing semiconductor device |
| EP0849806A2 (en) * | 1996-12-19 | 1998-06-24 | Texas Instruments Incorporated | Improvements in or relating to semiconductor devices having tungsten nitride sidewalls |
| EP0849806A3 (en) * | 1996-12-19 | 1999-08-25 | Texas Instruments Incorporated | Improvements in or relating to semiconductor devices having tungsten nitride sidewalls |
| US6432803B1 (en) | 1998-12-14 | 2002-08-13 | Matsushita Electric Industrial Co., Inc. | Semiconductor device and method of fabricating the same |
| JP2000332259A (en) * | 1999-03-17 | 2000-11-30 | Semiconductor Energy Lab Co Ltd | Wiring material, semiconductor device with wiring using the same and manufacture of the semiconductor device |
| EP1786037A2 (en) * | 1999-04-12 | 2007-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| EP1786037A3 (en) * | 1999-04-12 | 2012-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| US8866143B2 (en) | 1999-04-12 | 2014-10-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2001007110A (en) * | 1999-06-22 | 2001-01-12 | Semiconductor Energy Lab Co Ltd | Wiring material, semiconductor device with wiring using the same and manufacture thereof |
| US9660159B2 (en) | 1999-06-22 | 2017-05-23 | Semiconductor Energy Laboratory Co., Ltd. | Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof |
| US8357611B2 (en) | 1999-06-22 | 2013-01-22 | Semiconductor Energy Laboratory Co., Ltd. | Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof |
| US7906429B2 (en) | 1999-06-22 | 2011-03-15 | Semiconductor Energy Laboratory Co., Ltd. | Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof |
| US7816191B2 (en) | 1999-06-29 | 2010-10-19 | Semiconductor Energy Laboratory Co., Ltd. | Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof |
| US9045831B2 (en) | 1999-07-22 | 2015-06-02 | Semiconductor Energy Laboratory Co., Ltd. | Wiring and manufacturing method thereof, semiconductor device comprising said wiring, and dry etching method |
| US6617624B2 (en) | 1999-09-01 | 2003-09-09 | Micron Technology, Inc. | Metal gate electrode stack with a passivating metal nitride layer |
| US6265297B1 (en) | 1999-09-01 | 2001-07-24 | Micron Technology, Inc. | Ammonia passivation of metal gate electrodes to inhibit oxidation of metal |
| US6458714B1 (en) | 2000-11-22 | 2002-10-01 | Micron Technology, Inc. | Method of selective oxidation in semiconductor manufacture |
| JP2012124508A (en) * | 2012-01-26 | 2012-06-28 | Semiconductor Energy Lab Co Ltd | Semiconductor device, liquid crystal module, electronic equipment, and wiring |
| JP2012160737A (en) * | 2012-03-08 | 2012-08-23 | Toshiba Corp | Method of manufacturing semiconductor device |
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