JP2000332259A - Wiring material, semiconductor device with wiring using the same and manufacture of the semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device exhibiting high TFT characteristics. SOLUTION: In a method of manufacturing an active matrix display unit, low electrical resistivity of an electrode material is maintained by preventing the implantation of oxygen ions into electrodes, when impurity ions are doped. As a result, a display unit having electrodes whose electrical resistivity is low can be obtained. The wiring material is mainly composed of tungsten, has an oxygen content of 30 ppm or less, and also contains argon. The electrical resistivity of the wire is 40 μΩ.cm or less. The semiconductor device includes wiring having a laminated structure, where a tungsten film and a tungsten nitride film are laminated on an insulating surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit constituted by thin film transistors (hereinafter, referred to as TFTs) and a method for manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic device equipped with such an electro-optical device as a component.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and are particularly rapidly developed as switching elements for image display devices.

For example, in a liquid crystal display device, a pixel unit for individually controlling pixel units arranged in a matrix, a driving circuit for controlling the pixel unit, and a logic circuit (processor circuit or memory) for processing an external data signal are provided. Attempts have been made to apply TFTs to any electric circuit such as a circuit.

Conventionally, as a wiring material of the above-mentioned TFT, A
Conductive materials such as l, Ta, and Ti are used, and among them, aluminum having low resistivity is frequently used. However, when a TFT is manufactured using aluminum as a wiring material, heat treatment may cause protrusions such as hillocks and whiskers, and diffusion of aluminum atoms into a channel formation region, resulting in malfunction of the TFT and deterioration of TFT characteristics. I was

[0006]

As described above, aluminum is not a preferable wiring material in a TFT manufacturing process because of its low heat resistance.

The present invention has been made in view of the above problems, and has a sufficiently low electric resistivity and low heat resistance as wirings or electrodes of each circuit of an electro-optical device represented by AM-LCD. It is an object to provide an electro-optical device having high reliability using a sufficiently high material and a manufacturing method thereof.

[0008]

In order to solve the above-mentioned problems, the present invention provides a high melting point metal film obtained by a sputtering method using a target made of high purity high melting point metal as a wiring material. Typically, one of the features of the present invention is to use tungsten (W) as a high melting point metal. Examples of other high melting point metals include molybdenum (Mo), tantalum (Ta), chromium (Cr), niobium (Nb), and vanadium (V). Further, an alloy (e.g., a molybdenum tantalum alloy) that is a eutectic with another high melting point metal (such as molybdenum) may be used.

A target having a purity of 4N or more is used as a target, and a single gas such as argon (Ar), krypton (Kr), xenon (Xe) or a mixed gas thereof can be used as a sputtering gas. In addition, it is preferable to form a film using only a single gas of Ar because impurity elements are less likely to be mixed. The conditions such as sputtering power, gas pressure, and substrate temperature may be appropriately controlled by the practitioner.

The refractory metal film (tungsten) thus obtained contains almost no impurity elements, and can have an oxygen content of 30 ppm or less, and an electric resistivity of 40 μΩ · cm or less. Has 6μ ~ 15
μΩ · cm. The stress of the film is-
It can be set to 5 × 10 ^{9 to} 5 × 10 ⁹ dyn / cm ² .

Another feature of the present invention is that the wiring of the semiconductor device has a laminated structure of a high melting point metal film and a nitrided high melting point metal film. For example, after tungsten nitride (WNx (where 0 <x <1)) is formed on an insulating surface, tungsten (W) is stacked. Further, a structure in which a silicon film having conductivity (for example, a phosphorus-doped silicon film, a boron-doped silicon film, or the like) is provided under tungsten nitride (WNx) to improve adhesion may be employed. The wiring had a line width of 5 μm or less and a film thickness of 0.1 μm.
It can be formed with a thickness of about 0.7 μm.

In general, a high melting point metal has no resistance to oxidation and is easily oxidized by heat treatment in an atmosphere in which several ppm of residual oxygen exists. As a result, an increase in electrical resistivity and peeling of the film occur. In addition, at the time of ion doping, a small amount of an impurity element such as oxygen contained in the reaction gas is injected into the high melting point metal film, so that the electrical resistivity increases.

Therefore, in the method of manufacturing a TFT according to the present invention, before heat-treating the substrate provided with the high-melting-point metal film, the surface of the high-melting-point metal film is nitrided by nitriding such as thermal nitriding or plasma nitriding. It is characterized by being covered with a material film. When a wiring having tungsten nitride (WNx) as a lower layer and tungsten (W) as an upper layer is nitrided, the tungsten film has a wiring structure in which the upper surface, side surfaces, and lower surface are surrounded by tungsten nitride (WNx).

When a heat treatment is performed by forming a passivation film such as a silicon nitride film or a silicon oxynitride film in order to prevent oxidation, pinholes are generated, and oxidation sometimes proceeds inside the tungsten film.

FIG. 25 shows a laminated film having WNx (thickness: 30 nm) as a lower layer and W (thickness: 120 nm) as an upper layer formed on a quartz substrate (127 mm × 127 mm). After the treatment, the number of pinholes at 100 mm ² was measured using a surface inspection device (GI-46, manufactured by Hitachi, Ltd.).
00).

Condition 1) After nitriding plasma treatment using ammonia gas, forming a silicon nitride film (thickness 25 nm), and then heat-treating (550 ° C., 4 hours) Condition 2) Formation of silicon nitride film (thickness 25 nm) After film formation, heat treatment (550 ° C., 4 hours) Condition 3) After forming a silicon nitride film (25 nm thickness), form a silicon oxynitride film (200 nm thickness), and perform heat treatment (550 ° C., 4 hours) Condition 4) A silicon oxynitride film (thickness: 200 nm) is formed and heat-treated (550 ° C., 4 hours)

Table 1 shows the film forming conditions for WNx and W.

[0018]

[Table 1]

The plasma processing conditions and the silicon nitride film and the silicon oxynitride film SiOxNy (where 0 <x, y
Table 2 shows the film forming conditions of <1).

[0020]

[Table 2]

FIG. 25 confirms that the number of pinholes generated by the nitriding plasma treatment using ammonia gas is significantly reduced.

In the method of manufacturing a TFT according to the present invention, when ion doping for forming an impurity region is performed, at least the upper surface of the gate electrode is covered with a mask,
Another feature is to prevent impurity ions, particularly oxygen ions, from being implanted into the wiring. This mask may be a mask made of a photosensitive resin such as a resist exposed using a photomask, or may be a mask mainly composed of silicon patterned using a resist mask or the like. However, this mask needs to have a thickness capable of preventing implantation of oxygen ions or the like into the gate electrode.

According to the structure of the invention disclosed in this specification, in a semiconductor device including at least a pixel portion and a driving circuit on the same substrate, an n-channel TFT forming the driving circuit is provided.
Is arranged so that at least part or all of the LDD region overlaps with the gate wiring of the n-channel TFT, and the LDD region of the n-channel TFT forming the driving circuit has a larger area than the LDD region of the pixel TFT. The gate wiring includes a first gate wiring formed in contact with an insulating film and a first gate wiring formed in contact with an insulating film.
A second gate wiring formed in contact with the first gate wiring and formed inside the first gate wiring; and a third gate wiring formed in contact with the first gate wiring and the second gate wiring. A semiconductor device having the following.

According to another aspect of the present invention, in a semiconductor device including at least a pixel portion and a drive circuit on the same substrate, an LD of an n-channel TFT forming the drive circuit is provided.
The D region is at least partly or wholly arranged so as to overlap the gate wiring of the n-channel TFT, and the LDD region of the pixel TFT forming the pixel portion is
And the LDD region of the n-channel TFT forming the driving circuit
An impurity element that imparts n-type is included at a higher concentration than the LDD region of the pixel TFT, and the gate wiring is formed in contact with a first gate wiring formed in contact with an insulating film and in contact with the first gate wiring. A second gate line formed inside the first gate line, and a third gate line formed in contact with the first gate line and the second gate line. A semiconductor device characterized by the above-mentioned.

In each of the above structures, the first gate wiring is made of a material mainly containing a tungsten nitride layer, and the second gate wiring is made of a material mainly containing tungsten. The gate wiring of No. 3 is characterized by being made of a material mainly composed of a nitride layer formed by nitriding the second gate wiring.

The structure of the present invention in the manufacturing process is as follows:
In a method for manufacturing a semiconductor device including at least a pixel portion and a driver circuit over the same substrate, a step of forming an active layer on a substrate, a step of forming a gate insulating film in contact with the active layer, and a step of forming the gate insulating film Forming a gate wiring containing tungsten as a main component thereon, and forming an impurity region by adding an impurity element in a self-aligned manner using the gate wiring as a mask. And a gate wiring provided with a mask on at least the upper surface as a mask.

Another aspect of the present invention in a manufacturing process is a method for manufacturing a semiconductor device including at least a pixel portion and a driver circuit on the same substrate, wherein a step of forming an active layer on a substrate; Forming a gate insulating film in contact with the substrate, forming a gate wiring mainly containing tungsten on the gate insulating film, and adding an impurity element in a self-aligned manner using the gate wiring as a mask. Forming a nitride film on the surface of the gate wiring to form a nitride film on a surface of the gate wiring.

In the above structure, the nitriding treatment is performed by generating plasma in an ammonium gas atmosphere.

In each of the above structures, the gate wiring is characterized in that it has a stacked structure including a tungsten film and a tungsten nitride film.

Further, in each of the above structures, the gate wiring is formed by a sputtering method.

[0031] In this specification, the term "electrode" refers to
It is a part of the “wiring” and refers to a portion where electrical connection with another wiring or a portion intersecting with a semiconductor layer is made. Therefore,
For convenience of explanation, we use "wiring" and "electrode" properly,
It is assumed that the term “electrode” always includes “wiring”.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described.
A detailed description will be given using the following embodiments.

[0033]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. Here, a method for simultaneously manufacturing TFTs of a pixel portion and a driving circuit provided around the pixel portion will be described. However, for the sake of simplicity, the driving circuit shows a CMOS circuit which is a basic circuit such as a shift register circuit and a buffer circuit, and an n-channel TFT forming a sampling circuit.

In FIG. 1A, it is desirable to use a glass substrate or a quartz substrate as the substrate 100. Alternatively, a substrate obtained by forming an insulating film on a surface of a silicon substrate, a metal substrate, or a stainless steel substrate may be used as the substrate. If heat resistance permits, a plastic substrate can be used.

Then, the TFT of the substrate 100 is formed.
On the surface, an insulating film containing silicon (in this specification)
Of silicon oxide film, silicon nitride film, or silicon oxynitride film
Plasma CVD method for the base film 101 comprising
And a thickness of 100 to 400 nm by a sputtering method.
In this specification, a silicon oxynitride film is SiOx
Ny (where 0 <x, y <1)
And an insulating film containing silicon, oxygen, and nitrogen at a predetermined ratio.
You. The silicon oxynitride film is made of SiH_FourAnd N_TwoO and NH _Three
Should be prepared as a source gas, and the nitrogen concentration contained
It is good to be more than 25 atomic% and less than 50 atomic%.

In this embodiment, as the base film 101, a silicon oxynitride film is formed to a thickness of 25 to 100 nm, here 50 nm, and a silicon oxide film is formed to a thickness of 50 to 300 nm, here 150 nm.
It was formed in a two-layer structure having a thickness of nm. The base film 101 is provided to prevent impurity contamination from the substrate, and is not necessarily provided when a quartz substrate is used.

Next, on the underlying film 101, 20 to 100 nm
A semiconductor film including an amorphous structure (in this embodiment, an amorphous silicon film (not shown)) having a thickness of 3 mm was formed by a known film forming method. Note that the semiconductor film having an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film, and further includes a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film.

Then, according to the technique described in Japanese Patent Application Laid-Open No. Hei 7-130652 (corresponding to US Pat. No. 5,643,826), a semiconductor film (crystalline silicon film in this embodiment) 102 having a crystal structure was formed. The technology described in the publication discloses a catalyst element (nickel, cobalt, germanium,
This is a crystallization means using one or more elements selected from tin, lead, palladium, iron and copper, typically nickel).

More specifically, heat treatment is performed with the catalytic element held on the surface of the amorphous silicon film to change the amorphous silicon film into a crystalline silicon film. In this embodiment, the technology described in the first embodiment of the publication is used, but the technology described in the second embodiment may be used. In addition,
The crystalline silicon film includes a so-called single-crystal silicon film and a polycrystalline silicon film. The crystalline silicon film formed in this embodiment is a silicon film having crystal grain boundaries.
(Fig. 1 (A))

Although it depends on the hydrogen content, the amorphous silicon film is preferably subjected to dehydrogenation treatment by heating at 400 to 550 ° C. for several hours so that the hydrogen content is reduced to 5 atom% or less, and the crystallization step is performed. It is desirable. Although an amorphous silicon film may be formed by another manufacturing method such as a sputtering method or an evaporation method, it is preferable that impurity elements such as oxygen and nitrogen contained in the film be sufficiently reduced.

Here, since the base film and the amorphous silicon film can be formed by the same film forming method, both may be formed continuously. Once the base film is formed, it is possible to prevent the surface from being contaminated by not being exposed to the air atmosphere once, and it is possible to reduce the characteristic variation of the TFT to be manufactured.

Next, the crystalline silicon film 102 is irradiated with light (laser light) emitted from a laser light source (hereinafter referred to as “laser light”).
By performing laser annealing, a crystalline silicon film 103 having improved crystallinity was formed. As laser light,
Although a pulse oscillation type or continuous oscillation type excimer laser beam is desirable, a continuous oscillation type argon laser beam may be used. The beam shape of the laser beam may be linear or rectangular. (FIG. 1 (B))

Further, instead of laser light, light emitted from a lamp (lamp light) may be irradiated (hereinafter, referred to as lamp annealing). Halogen lamp,
Lamp light emitted from an infrared lamp or the like can be used.

The step of performing the heat treatment (annealing) by the laser light or the lamp light in this manner is called a light annealing step. Since the high-temperature heat treatment can be performed in a short time in the light annealing step, an effective heat treatment step can be performed with high throughput even when a substrate having low heat resistance such as a glass substrate is used. Of course, since the purpose is annealing, furnace annealing (also referred to as thermal annealing) using an electric furnace can be used instead.

In this embodiment, the laser annealing step was performed by processing the pulse oscillation type excimer laser beam into a linear shape. Laser annealing conditions are as follows: XeCl
Using gas, processing temperature is room temperature, pulse oscillation frequency is 30
Hz and laser energy density 250-500mJ
/ cm ² (typically 350 to 400 mJ / cm ² ).

The laser annealing step performed under the above conditions has the effects of completely crystallizing the amorphous region remaining after thermal crystallization and reducing defects in the crystalline region already crystallized. Therefore, this step can also be called a step of improving the crystallinity of the semiconductor film by optical annealing or a step of promoting crystallization of the semiconductor film. Such an effect can also be obtained by optimizing the lamp annealing conditions. In this specification, such a condition will be referred to as a first annealing condition.

Next, a protective film 104 was formed on the crystalline silicon film 103 for the purpose of adding impurities later. Protective film 1
04 is 100 to 200 nm (preferably 130 to 170 nm)
nm) of a silicon oxynitride film or a silicon oxide film. The protective film 104 has a meaning to prevent the crystalline silicon film from being directly exposed to plasma at the time of adding an impurity and to enable fine concentration control.

Then, a resist mask 105 was formed thereon, and an impurity element imparting p-type (hereinafter, referred to as a p-type impurity element) was added via the protective film 104. As the p-type impurity element, an element belonging to Group 13 typically, typically, boron or gallium can be used.
This step (called a channel doping step) is a step for controlling the threshold voltage of the TFT. Here, boron was added by an ion doping method in which diborane (B ₂ H ₆ ) was not plasma-excited without mass separation.

By this step, 1 × 10 ¹⁵ to 1 × 10 ¹⁸ at
oms / cm ³ (typically 5 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / c
An impurity region 106 containing a p-type impurity element (boron in this embodiment) at a concentration of m ³ ) was formed. Note that in this specification, an impurity region containing a p-type impurity element in at least the above concentration range is defined as a p-type impurity region (b). (Figure 1
(C))

Next, the resist mask 105 was removed, and new resist masks 107 to 110 were formed. Then, an impurity element imparting n-type (hereinafter referred to as an n-type impurity element) is added to add impurity regions 111 to 111 exhibiting n-type.
13 was formed. Note that as the n-type impurity element, an element belonging to Group XV, typically, phosphorus or arsenic can be used. (Fig. 1 (D))

The low concentration impurity regions 111 to 113 are
This is an impurity region for functioning as an LDD region later in the n-channel TFT of the CMOS circuit and the sampling circuit. The impurity region formed here contains an n-type impurity element at 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm 2.
³ (typically 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ ). In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (b).

Here, phosphorus was added at a concentration of 1 × 10 ¹⁸ atoms / cm ³ by an ion doping method in which phosphine (PH ₃ ) was excited by plasma without mass separation. In this step, phosphorus was added to the crystalline silicon film via the protective film 107.

Next, the protective film 104 was removed, and a laser beam irradiation step was performed again. Here, as the laser beam, a pulse oscillation type or a continuous oscillation type excimer laser beam is desirable, but a continuous oscillation type argon laser beam may be used. The beam shape of the laser beam may be linear or rectangular. However, since the purpose is to activate the added impurity element, it is preferable that the irradiation be performed with energy that does not melt the crystalline silicon film. Further, it is possible to perform the laser annealing step with the protective film 104 attached. (FIG. 1 (E))

In this embodiment, the laser annealing step was performed by processing the pulse oscillation type excimer laser light into a linear shape. The laser annealing conditions were as follows: KrF gas was used as the excitation gas, the processing temperature was room temperature, and the pulse oscillation frequency was 30H.
z, and the laser energy density is 100 to 300 mJ / c
m ² (typically 150 to 250 mJ / cm ² ).

The light annealing step performed under the above conditions activates the added impurity element imparting n-type or p-type, and recrystallizes the semiconductor film which has become amorphous when the impurity element is added. Has an effect. Note that it is preferable that the above conditions satisfy the atomic arrangement without melting the semiconductor film and activate the impurity element. This step can also be referred to as a step of activating an impurity element imparting n-type or p-type by optical annealing, a step of recrystallizing a semiconductor film, or a step of simultaneously performing these steps. Such an effect can also be obtained by optimizing the lamp annealing conditions. In this specification, such a condition will be referred to as a second annealing condition.

By this step, n-type impurity region (b) 11
The boundary with the boundary between 1 and 113, that is, the junction with the intrinsic region existing around the n-type impurity region (b) (the p-type impurity region (b) is also regarded as substantially intrinsic) becomes clear. This means that when the TFT is completed later, a very good junction can be formed between the LDD region and the channel forming region.

When activating the impurity element by the laser beam, activation by heat treatment may be used in combination. When activation by heat treatment is performed, heat treatment at about 450 to 550 ° C. may be performed in consideration of the heat resistance of the substrate.

Next, unnecessary portions of the crystalline silicon film are removed, and an island-like semiconductor film (hereinafter, referred to as an active layer) 114 is formed.
To 117 were formed. (FIG. 1 (F))

Next, a gate insulating film 118 was formed to cover the active layers 114 to 117. The gate insulating film 118 includes 1
The thickness may be 0 to 200 nm, preferably 50 to 150 nm. In the present embodiment, N
115 nm of silicon oxynitride film made of ₂ O and SiH ₄
It was formed in thickness. (Fig. 2 (A))

Next, a high melting point metal film to be a gate wiring was formed. Note that the gate wiring may be formed of a single-layer high-melting-point metal film, but is preferably a stacked film of two or three layers as necessary. In this embodiment, a stacked film including the first high melting point metal film 119 and the second high melting point metal film 120 is formed. (FIG. 2 (B))

The first refractory metal film 119 and the second refractory metal film 120 are made of tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), or the like. Or a conductive film (typically, a tantalum nitride film, a tungsten nitride film, a titanium nitride film) containing the aforementioned element as a main component, or an alloy film combining the above elements (typically, Mo-W alloy,
Mo-Ta alloy) can be used.

The first refractory metal film 119 has a thickness of 10 to 10.
50 nm (preferably 20 to 30 nm), and the second refractory metal film 120 is 200 to 400 nm (preferably 2 to 30 nm).
(50-350 nm). In the present embodiment, the first
A 50-nm-thick tungsten nitride (WNx) film was used as the high-melting-point metal film 119, and a 350-nm-thick tungsten (W) film was used as the second high-melting-point metal film 120. In this embodiment, the layers are continuously formed by a sputtering method without exposure to the air.

Although not shown, it is effective to form a silicon film with a thickness of about 2 to 20 nm under the first refractory metal film 119. Thereby, it is possible to improve the adhesion of the high melting point metal film formed thereon and prevent oxidation.

Next, after forming the resist masks 123 to 125, the first refractory metal film 119 and the second refractory metal film 120 are etched to form a gate wiring 121 of a 400 nm thick p-channel TFT and The wiring 122 was formed.

Then, while the resist masks 123 to 125 are provided, a p-type impurity element (boron in this embodiment) is added, and the impurity regions 126 and 12 containing boron at a high concentration are added.
7 was formed. The resist masks 123 to 125 are
At the time of the step of adding the p-type impurity element, it plays a role of preventing an impurity, particularly oxygen, from being injected into the high melting point metal film to increase the resistivity. Here, an ion doping method using diborane (B ₂ H ₆ ) is used to form 3 × 10 ^{20 to} 3 × 10 ²¹ atoms /
Boron was added at a concentration of cm ³ (typically 5 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ ). In this specification, an impurity region containing a p-type impurity element in the above concentration range is defined as a p-type impurity region (a). (FIG. 2D) Of course, the impurity region may be formed by etching the gate insulating film to expose the active layer and doping.

Next, after removing the resist masks 123 to 125, resist masks 131 to 135 are formed and etched to form n-channel TFT gate wirings 128 to 125.
130 was formed. At this time, the gate wirings 128 and 129 formed in the drive circuit have n-type impurity regions (b) 111 to
113 was formed so as to overlap with part of the gate insulating film. This overlapping portion will later become a Lov region. In addition,
Although the gate wiring 130 looks like two in cross section, it is actually formed of one continuous pattern.
(FIG. 2 (E))

Then, while the resist masks 131 to 135 were provided, an n-type impurity element (phosphorus in this embodiment) was added in a self-aligned manner using the masks 131 to 135 as masks. The resist masks 131 to 135 play a role in preventing an impurity, particularly oxygen, from being implanted into the refractory metal film during the step of adding the n-type impurity element, thereby preventing the resistivity from increasing.
Of course, the impurity region may be formed by etching the gate insulating film to expose the active layer and doping. The impurity regions 136 to 139 thus formed have the n
不純 物 to 1/10 (typically 1
/ 3 to 1/4) concentration (provided that the concentration is 5 to 10 times higher than the boron concentration added in the channel doping step described above;
Typically, it was adjusted so that phosphorus was added at 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ , typically 3 × 10 ^{17 to} 3 × 10 ¹⁸ atoms / cm ³ . In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (c). (FIG. 3 (A))

In this step, the resist mask 131 is used.
All n-type impurity regions except those hidden by 135
(B) also 1 × 10¹⁶~ 5 × 10¹⁸atoms / cm^ThreeAt the concentration of
Phosphorus is added, but the concentration is very low, so n-type
The function as the impurity region (b) is not affected. Ma
The n-type impurity regions (b) 136 to 139 already have
1 × 10 in flannel doping process¹⁵~ 1 × 10¹⁸atoms / cm^Threeof
Although boron is added at a concentration of
5 to 10 times the concentration of boron contained in the pure region (b)
In this case, boron is also an n-type impurity because phosphorus is added.
It can be considered that the function of the area (b) is not affected. Ma
Also, 1 × 10 ¹⁶~ 5 × 10¹⁸
atoms / cm^ThreePhosphorus is added at a concentration of
Concentration, the function as a p-type impurity region (a)
Has no effect.

However, strictly speaking, the n-type impurity region (b) 11
The phosphorus concentration of the portion overlapping the gate wiring among 1 to 113 remains at 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ , whereas the portion not overlapping the gate wiring is 1 × 10 ¹⁶
Phosphorus at a concentration of ~ 5 × 10 ¹⁸ atoms / cm ³ is added,
It will contain phosphorus at a slightly higher concentration.

Next, while holding the resist masks 131 to 135, new resist masks 140 to 142 are formed, and an n-type impurity element (phosphorus in this embodiment) is added to add impurity regions containing phosphorus at a high concentration. 143 to 149 were formed. Of course, the impurity region may be formed by etching the gate insulating film to expose the active layer and doping. Also in this case, the ion doping method using phosphine (PH ₃ ) is performed, and the phosphorus concentration in this region is 1 × 10 ²⁰ to
1 × 10 ²¹ atoms / cm ³ (typically 2 × 10 ^{20 to} 5 × 1
0 ²⁰ atoms / cm ³ ). (FIG. 3 (B))

In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (a). The region where the impurity regions 143 to 149 are formed contains phosphorus or boron already added in the previous step, but phosphorus is added at a sufficiently high concentration. You do not need to consider the effect of phosphorus or boron. Therefore, in this specification, the impurity regions 143 to 149 may be referred to as n-type impurity regions (a).

Phosphorus is also added at a concentration of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ to part of the impurity regions 126 and 127 (the p-type impurity region (a) which does not overlap the mask 132). But boron already has at least 3
More than twice the concentration is added. Therefore, the previously formed p-type impurity region is not inverted to N-type,
It functions as a P-type impurity region.

Further, in the formation of each of the impurity regions, an example has been described in which ion doping is performed while the resist mask is held on the upper surface of the gate electrode. However, instead of the resist mask, silicon patterned using a mask or the like is used. May be used. However, this mask needs to have a thickness capable of preventing implantation of oxygen ions or the like into the gate electrode. Note that the mask containing silicon as its main component may be formed using a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a stacked film obtained by combining them.

Next, the resist masks 131 to 135, 1
After removing 40 to 142, an insulating film 151 to be a part of the first interlayer insulating film was formed. The insulating film 151 may be formed using a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a stacked film including a combination thereof. The film thickness is 0.1 to
It may be 0.4 μm. In this embodiment, the plasma CV
Method D, using SiH ₄ , N ₂ O, and NH ₃ as source gases,
μm thick silicon oxynitride film (However, nitrogen concentration is 25-50ato
mic%).

Thereafter, a heat treatment step was performed to activate the n-type or p-type impurity element added at each concentration. This step is performed by furnace annealing, laser annealing, or rapid thermal annealing (RTA).
Method). Here, the activation step was performed by furnace annealing. The heat treatment is performed in a nitrogen atmosphere at 300 to 650 ° C., preferably 400 to 550 ° C.
C., here 550.degree. C., for 4 hours. (FIG. 3 (C))

At this time, the catalytic element (nickel in this embodiment) used for crystallization of the amorphous silicon film in this embodiment.
Moved in the direction indicated by the arrow and was captured (gettered) in the high-concentration phosphorus-containing region formed in the step of FIG. This is a phenomenon caused by the gettering effect of the metal element by phosphorus. As a result, the channel formation regions 152 to 156 to be formed later have the concentration of the catalyst element of 1 ×.
10 ¹⁷ atoms / cm ³ or less (preferably 1 × 10 ¹⁶ atoms / cm ³
Below).

On the contrary, the region which became the gettering site of the catalytic element (the impurity region 143 to
149 formed region and impurity regions 126 and 127
Part) is 5 × 10 ¹⁸ atom
s / cm ³ or more (typically 1 × 10 ^{19 to} 5 × 10 ²⁰ atoms / c
m ³ ) came to exist at a concentration.

Further, in an atmosphere containing 3 to 100% hydrogen, a heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours to hydrogenate the active layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
May be performed.

After the activation step, an interlayer insulating film 157 having a thickness of 0.5 to 1.5 μm was formed on the insulating film 151. In this embodiment, a silicon oxide film having a thickness of 0.7 μm is formed as the interlayer insulating film 157 by a plasma CVD method. Thus, a 1 μm-thick first interlayer insulating film composed of a stacked film of the insulating film (silicon oxynitride film) 151 and the interlayer insulating film (silicon oxide film) 157 was formed.

Thereafter, contact holes reaching the source region or the drain region of each TFT are formed, and the source wirings 158 to 161 and the drain wiring 162 are formed.
~ 165 was formed. Although not shown, the CMO
To form an S circuit, the drain wirings 162 and 163 are connected as the same wiring. Although not shown, in the present embodiment, this electrode is formed by
Aluminum film containing i 300 nm, Ti film 150 nm
Was formed into a three-layer laminated film continuously formed by a sputtering method.

Next, as a passivation film 166,
50 for silicon nitride film, silicon oxide film, or silicon oxynitride film
It was formed to a thickness of 500 nm (typically 200 to 300 nm). At this time, in this embodiment, a plasma treatment was performed using a gas containing hydrogen such as H ₂ and NH ₃ before forming the film, and a heat treatment was performed after the film was formed. Hydrogen excited by this pretreatment is supplied into the first interlayer insulating film. By performing the heat treatment in this state, the film quality of the passivation film 166 is improved, and the hydrogen added to the first interlayer insulating film diffuses to the lower layer side, so that the active layer is effectively hydrogenated. Was completed.

FIG. 23 shows the relationship between the pressure of the sputtering gas and the stress. The stress value after the formation of the tungsten film, the stress value of the tungsten film on which a silicon nitride film (corresponding to a passivation film) was formed, and the silicon nitride film were formed and heat treated at 800 ° C. for 1 hour. This is a result of measuring the stress value of the tungsten film. FIG. 23 shows that the stress decreases when heat treatment is applied. FIG. 24 shows the relationship between the pressure of a sputter gas and the electrical resistivity in a tungsten film formed using a target with a purity of 3.5N. As shown in FIG. 24, it is shown that the electrical resistivity decreases when heat treatment is performed. From the experimental results shown in FIGS. 23 and 24, there is no problem in the stress value and the electric resistivity even if the passivation film is formed and the heat treatment is performed after the impurity doping process in this embodiment.

After the passivation film 166 is formed, a hydrogenation step may be further performed. For example, 3
300-450 ° C. in an atmosphere containing 〜100% hydrogen
And a similar effect was obtained by using a plasma hydrogenation method. Note that an opening may be formed in the passivation film 166 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later.

Thereafter, a second interlayer insulating film 167 made of an organic resin was formed to a thickness of about 1 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. The advantages of using an organic resin film include that the film formation method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film or an organic SiO compound other than those described above can also be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used.

Next, a shielding film 168 was formed on the second interlayer insulating film 167 in a region to be a pixel portion. In addition,
In this specification, the term shielding film is used to mean that light and electromagnetic waves are shielded.

The shielding film 168 is a film made of an element selected from aluminum (Al), titanium (Ti), and tantalum (Ta) or a film containing any one of the elements as a main component.
It was formed to a thickness of 300 nm. In this embodiment, an aluminum film containing 1 wt% of titanium was formed to a thickness of 125 nm.

When an insulating film such as a silicon oxide film is formed on the second interlayer insulating film 167 in a thickness of 5 to 50 nm, the adhesion of the shielding film formed thereon can be improved. In addition, when plasma treatment using CF ₄ gas was performed on the surface of the second interlayer insulating film 167 formed of an organic resin, the adhesion of the shielding film formed on the film was improved by surface modification. .

Further, it is possible to form not only a shielding film but also other connection wirings by using the aluminum film containing titanium. For example, it is possible to form a connection wiring that connects circuits in a drive circuit. However, in that case, before forming the material for forming the shielding film or the connection wiring, the second
It is necessary to form a contact hole in the interlayer insulating film.

Next, an oxide 169 having a thickness of 20 to 100 nm (preferably 30 to 50 nm) was formed on the surface of the shielding film 168 by an anodic oxidation method or a plasma oxidation method (in this embodiment, an anodic oxidation method). In this embodiment, the shielding film 168 is used.
As a result, an aluminum oxide film (alumina film) was formed as the anodic oxide 169.

At the time of this anodizing treatment, first, an ethylene glycol tartrate solution having a sufficiently low alkali ion concentration was prepared. This is a solution in which a 15% aqueous solution of ammonium tartrate and ethylene glycol are mixed at a ratio of 2: 8. Aqueous ammonia was added to the mixture to adjust the pH to 7 ± 0.5. Then, a platinum electrode serving as a cathode is provided in the solution, and the substrate on which the shielding film 168 is formed is immersed in the solution.
A DC current of several tens mA) was passed.

The voltage between the cathode and the anode in the solution changes with time according to the growth of the anodic oxide, but the voltage is increased at a constant current of 100 V / min at a boosting rate to reach the ultimate voltage of 45 V. By the way, the anodizing treatment was terminated. In this way, the surface of the shielding film 168 has a thickness of about 50.
nm anodic oxide 169 could be formed. As a result, the thickness of the shielding film 168 became 90 nm. It is to be noted that the numerical values relating to the anodic oxidation method shown here are merely examples, and the optimum values can naturally vary depending on the size of the element to be manufactured.

Although the insulating film is provided only on the surface of the shielding film by using the anodic oxidation method here, the insulating film may be formed by a gas phase method such as a plasma CVD method, a thermal CVD method or a sputtering method. good. In this case, the film thickness is 20 to 1
It is preferably set to 00 nm (preferably 30 to 50 nm). Alternatively, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a DLC (Diamond like carbon) film, or an organic resin film may be used. Further, a stacked film combining these may be used.

Next, a contact hole reaching the drain wiring 165 was formed in the second interlayer insulating film 167 and the passivation film 166, and a pixel electrode 170 was formed. Note that each of the pixel electrodes 171 and 172 is a pixel electrode of another adjacent pixel. The pixel electrodes 170 to 172 may be formed using a transparent conductive film when a transmissive liquid crystal display device is used, and a metal film may be used when a reflective liquid crystal display device is formed. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by a sputtering method.

At this time, the pixel electrode 170 and the shielding film 1
68 overlapped via the anodic oxide 169 to form a storage capacity (capacity striation) 173. Note that in this case, it is desirable that the shielding film 168 be set to a floating state (an electrically isolated state) or a fixed potential, preferably a common potential (an intermediate potential of an image signal transmitted as data).

Thus, an active matrix substrate having a driving circuit and a pixel portion on the same substrate was completed. Note that in FIG. 4A, a p-channel TFT 301 and n-channel TFTs 302 and 303 are formed in a driver circuit, and a pixel TF including an n-channel TFT is formed in a pixel portion.
T304 was formed.

For the p-channel type TFT 301 of the driving circuit,
Are the channel forming region 201, the source region 202, and the drain.
In regions 203 are formed of p-type impurity regions (a), respectively.
Was done. However, the source region or the drain region is actually
1 × 10 in part of²⁰~ 1 × 10 ^{twenty one}atoms / cm^ThreeAt a concentration of
There is an area that includes In addition, FIG.
The catalyst element gettered in the step (C) is 5 × 10
¹⁸atoms / cm^Three(Typically 1 × 10¹⁹~ 5 × 10²⁰a
toms / cm^Three) Present in concentration.

In the n-channel type TFT 302, the channel formation region 204, the source region 205, the drain region 206, and one side (drain region side) of the channel formation region overlapping with the gate wiring via the gate insulating film. (In the present specification, such a region is referred to as an Lov region. In the description, ov is assigned to overlap.) 207 is formed. At this time, the Lov area 207 is 2 × 10 ^{16 to} 5 ×
It was formed so as to contain phosphorus at a concentration of 10 ¹⁹ atoms / cm ³ and to completely overlap with the gate wiring.

In the n-channel TFT 303, a channel forming region 208, a source region 209, a drain region 210, and LDD regions 211 and 212 are formed on both sides of the channel forming region. In this structure, LD
Since a part of the D regions 211 and 212 are arranged so as to overlap with the gate wiring, a region (Lov region) overlapping with the gate wiring via the gate insulating film and a region not overlapping with the gate wiring (in this specification, this region is referred to as “Lov region”). Such an area is referred to as an Loff area, where off means offset.).

Here, the cross-sectional view shown in FIG. 5 is an enlarged view showing a state in which the n-channel TFT 303 shown in FIG. 4A is manufactured up to the step of FIG. As shown here,
The LDD region 211 can be further distinguished into a Lov region 211a and a Loff region 211b. The Lov region 211a contains phosphorus at a concentration of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ , whereas the Loff region 211b is 1 to 2 times as large (typically 1.2 to 1 × 10 ¹⁹ atoms / cm ³ ). .5 times).

The pixel TFT 304 includes channel forming regions 213 and 214, a source region 215, a drain region 216, Loff regions 217 to 220, and an Loff region 21.
8 and 219, the n-type impurity regions (a) 221 were formed. At this time, the source region 215 and the drain region 21
6 are each formed of an n-type impurity region (a),
The regions 217 to 220 are formed by the n-type impurity regions (c).

In the present embodiment, the structure of the TFT forming each circuit was optimized in accordance with the circuit specifications required by the pixel portion and the driving circuit, and the operation performance and reliability of the semiconductor device could be improved. Specifically, an n-channel TFT
Changes the arrangement of the LDD regions according to the circuit specifications, and Lov
By selectively using the region or the Loff region, a TFT structure emphasizing high-speed operation or hot carrier measures and a TFT structure emphasizing low off-current operation are realized on the same substrate.

For example, in the case of an active matrix type liquid crystal display device, the n-channel type TFT 302 is suitable for a driving circuit such as a shift register circuit, a frequency dividing circuit, a signal dividing circuit, a level shifter circuit, and a buffer circuit, which emphasize high-speed operation. That is, by arranging the Lov region only on one side (drain region side) of the channel forming region, the structure is such that the resistance component is reduced as much as possible and the hot carrier measures are emphasized. This is because, in the case of the above circuit group, the functions of the source region and the drain region do not change,
This is because the moving direction is constant. However, Lov regions can be arranged on both sides of the channel forming region as needed.

Further, the n-channel TFT 303 is suitable for a sampling circuit (sample-hold circuit) in which both measures against hot carriers and low off-current operation are emphasized. That is, the hot carrier is prevented by arranging the Lov region, and the low off-current operation is realized by arranging the Loff region. In the sampling circuit, the functions of the source region and the drain region are inverted, and the carrier moving direction is 18
Since the angle is changed by 0 °, the structure must be line-symmetric with respect to the gate wiring. In some cases, L
There may be only the ov region.

Further, the n-channel type TFT 304 is suitable for a pixel portion and a sampling circuit (a sample-and-hold circuit) which place importance on low off-current operation. That is, a low off-current operation is realized by arranging only the Loff region without arranging the Lov region that can cause an increase in the off-current value. Also, an LD having a lower concentration than the LDD region of the drive circuit.
By using the D region as the Loff region, a measure is taken to thoroughly reduce the off-current value even if the on-current value slightly decreases. Further, it has been confirmed that the n-type impurity region (a) 221 is very effective in reducing the off-current value.

Also, if the length (width) of the Lov region 207 of the n-channel TFT 302 is 0.5 to 3.0 μm, typically 1.0 to 1.5 μm, for a channel length of 3 to 7 μm. good. The length (width) of the Lov regions 211a and 212a of the n-channel TFT 303 is 0.5 to 3.0 μm.
m, typically 1.0 to 1.5 μm, Loff region 211
The length (width) of b, 212b may be 1.0 to 3.5 μm, typically 1.5 to 2.0 μm. The pixel TF
The length (width) of the Loff regions 217 to 220 provided in the T304 is 0.5 to 3.5 μm, typically 2.0 to 2.0 μm.
The thickness may be set to 5 μm.

Further, the p-channel TFT 301 is formed in a self-aligned (self-aligned) manner,
One of the features of the present invention is that the FTs 302 to 304 are formed in a non-self-aligned manner (non-self-aligned).

In this embodiment, an alumina film having a relative dielectric constant as high as 7 to 9 is used as the dielectric of the storage capacitor.
It is possible to reduce the area for forming the required capacitance. Further, by using the shielding film formed on the pixel TFT as one electrode of the storage capacitor as in the present embodiment,
The aperture ratio of the image display section of the active matrix type liquid crystal display device could be improved.

The present invention is not limited to the structure of the storage capacitor shown in this embodiment. For example, Japanese Patent Application Laid-Open No. Hei 11-133463 and Japanese Patent Application No. Hei 10-25
The structure of the storage capacitor described in the 4097 application can also be used.

Next, a process for manufacturing an active matrix type liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 4B, an alignment film 401 was formed on the substrate in the state shown in FIG. In this embodiment, a polyimide film was used as the alignment film. Also, the counter substrate 40
In No. 2, a transparent conductive film 403 and an alignment film 404 were formed. Note that a color filter and a shielding film may be formed on the counter substrate as needed.

Next, after forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. Then, the pixel portion, the active matrix substrate on which the drive circuit was formed, and the counter substrate were bonded via a sealing material or a spacer (both not shown) by a known cell assembling process. Thereafter, liquid crystal 405 was injected between the two substrates, and completely sealed with a sealing agent (not shown). A known liquid crystal material may be used for the liquid crystal. Thus, the active matrix liquid crystal display device shown in FIG. 4B was completed.

Next, the structure of the active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. still,
In FIG. 6, common reference numerals are used in order to correspond to the sectional structural views of FIGS. Active matrix substrates
A pixel portion 601, a scanning (gate) signal line side driving circuit 602, and an image (source) signal line side driving circuit 603 formed on the glass substrate 101. The pixel TFT 304 in the pixel portion is an n-channel TFT, and a driving circuit provided around the pixel TFT 304 is basically configured by a CMOS circuit. The gate signal line side driver circuit 602 and the source signal line side driver circuit 603 are connected to the pixel portion 601 by a gate wiring 130 and a source wiring 161 respectively. Also,
Connection wirings 606 and 607 from the external input / output terminal 605 to which the FPC 604 is connected to the input / output terminal of the driving circuit are provided.

[Embodiment 2] FIG. 7 shows an example of a circuit configuration of the active matrix substrate shown in Embodiment 1. The active matrix substrate of this embodiment includes a source signal line side driving circuit 701, a gate signal line side driving circuit (A) 707,
A gate signal line side driver circuit (B) 711, a precharge circuit 712, and a pixel portion 706 are provided. Note that in this specification, a driving circuit is a general term including the image signal processing circuit 701 and the gate signal line side driving circuit 707.

The source signal line side driving circuit 701 includes a shift register circuit 702, a level shifter circuit 703, a buffer circuit 704, and a sampling circuit 705.
The gate signal line side driver circuit (A) 707 includes a shift register circuit 708, a level shifter circuit 709, and a buffer circuit 710. The gate signal line side driver circuit (B) 711 has a similar configuration.

Here, shift register circuits 702 and 708
Has a drive voltage of 5 to 16 V (typically 10 V),
N-channel type T used for CMOS circuits forming circuits
The structure shown by 302 in FIG. 4A is suitable for the FT.

The level shifter circuits 703, 709,
The buffer circuits 704 and 710 have driving voltages of 14 to 16
V, as in the case of the shift register circuit.
A CMOS circuit including the n-channel TFT 302 shown in FIG. The gate wiring has a double gate structure,
The use of a multi-gate structure such as a triple gate structure is effective in improving the reliability of each circuit.

Although the driving voltage of the sampling circuit 705 is 14 to 16 V, since the source region and the drain region are inverted and the off-current value needs to be reduced, the n-channel TFT 303 shown in FIG. Are suitable. In FIG. 4A, the n-channel type T
Although only FT is shown, when an actual sampling circuit is formed, an n-channel TFT and a p-channel TF are used.
It is formed by combining with T.

The pixel portion 706 has a drive voltage of 14 to 1
Since it is required that the off-state current is 6 V and the off-state current value is lower than that of the sampling circuit 705, it is preferable that the Lov region is not provided, and the n-channel TFT 304 in FIG. desirable.

The structure of this embodiment can be easily realized by manufacturing a TFT according to the manufacturing steps shown in the first embodiment. In this embodiment, only the configuration of the pixel portion and the driving circuit is shown. However, according to the manufacturing process of the first embodiment, a signal dividing circuit, a frequency dividing circuit, a D / D
An A-converter circuit, an operational amplifier circuit, a gamma correction circuit, and a signal processing circuit (also referred to as a logic circuit) such as a memory circuit or a microprocessor circuit can be formed over the same substrate.

As described above, according to the present invention, a semiconductor device including at least a pixel portion and a driving circuit for driving the pixel portion over the same substrate, for example, a signal processing circuit, a driving circuit, and a pixel portion over the same substrate. A semiconductor device having the same can be realized.

[Embodiment 3] In this embodiment, a case where a TFT is manufactured in a step different from that of Embodiment 1 will be described with reference to FIGS. Since the other steps are the same as those of the first embodiment except for the steps in the middle, the same reference numerals are used for the same steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, according to the steps of Embodiment 1, FIG.
Form up to. FIG. 8 corresponding to FIG.
(A).

Next, the resist masks 131 to 135, 1
After removing 40 to 142, the gate wirings 121 and 128 are removed.
To 130 and the wiring 122 were subjected to a nitriding treatment.

Here, the nitriding treatment means thermal nitriding (heat treatment in ammonia or an atmosphere containing active nitrogen atoms) or plasma nitriding (ammonia gas or nitrogen gas is introduced into a reaction chamber in a high vacuum state, (A process of generating plasma by applying high frequency power).

In this embodiment, plasma nitridation using ammonia gas was performed to form nitride films 506 to 510 on the surfaces of the gate wiring and the wiring. (FIG. 8B) The occurrence of pinholes can be suppressed by performing this plasma nitridation. Note that the nitride of tungsten has sufficient conductivity and thus functions as a wiring.

Next, heat treatment was performed in the same manner as in Example 1,
Activation of impurity elements and reduction of catalytic elements were performed.
(FIG. 8C) Before this heat treatment, a protective film made of a thin silicon nitride film may be formed as in the first embodiment.

Also, by increasing the temperature in the step of FIG.
The activation of the impurity element and the reduction of the catalyst element may be performed at the same time as the formation of the nitride film of the gate electrode, and the process of FIG. 8C may be omitted to improve the throughput.

In this manner, the oxidation resistance of the wiring was improved, and the low electrical resistivity of the wiring was maintained.

Thereafter, the steps of the first embodiment may be followed.
(FIG. 8D) Note that the structure of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured.

[Embodiment 4] In this embodiment, a case in which a TFT is manufactured in a different process order from that of Embodiment 1 will be described. The other steps are the same as those of the first embodiment, except for the intermediate steps. In addition, the impurity element to be added is also the same as in Example 1.
The same impurity element as described above is taken as an example.

First, the protective film 10 is formed according to the steps of the first embodiment.
Form up to 4. Then, a resist mask is formed thereon, and an n-type impurity element is added under the same conditions as those in FIG. Thus, an n-type impurity region (b) is formed.

Next, the resist mask is removed, and a new resist mask is formed. Then, a channel doping step is performed under the same conditions as those in FIG. Thus, a p-type impurity region (b) is formed.

Thereafter, according to the steps of Embodiment 1, FIG.
(E) The subsequent steps may be performed. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

[Embodiment 5] In this embodiment, a case where TFTs are manufactured in a different process order from that of Embodiment 1 will be described with reference to FIGS. Since the other steps are the same as those of the first embodiment except for the steps in the middle, the same reference numerals are used for the same steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, according to the steps of Embodiment 1, FIG.
Up to the step. Then, the formed crystalline silicon film 103 is patterned to form active layers 901 to 904, on which a protective film 905 made of an insulating film containing silicon (a silicon oxide film in this embodiment) is formed to a thickness of 120 to 150 nm. Form. (FIG. 9A)

Although the present embodiment shows an example in which the crystalline silicon film is patterned after the laser annealing step (first annealing condition), the order can be reversed.

Next, resist masks 906 to 909 are formed, and an n-type impurity element is added under the same conditions as in FIG. Thus, n-type impurity regions (b) 910 to 912 are formed. (FIG. 9 (B))

Next, the resist masks 906 to 909 are removed, and a new resist mask 913 is formed. Then, a channel doping step is performed under the same conditions as those in FIG. Thus, p-type impurity regions (b) 914 to 916 are formed. (FIG. 9 (C))

Then, the resist mask 913 is removed,
The laser annealing step (second
Annealing conditions). This effectively activates the added n-type or p-type impurity element. (FIG. 9
(D))

Thereafter, the process of FIG.
(A) The subsequent steps may be performed. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

[Embodiment 6] In this embodiment, a case in which a TFT is manufactured in a different process order from that of Embodiment 1 will be described. The other steps are the same as those of the first embodiment, except for the intermediate steps. In addition, the impurity element to be added is also the same as in Example 1.
The same impurity element as described above is taken as an example.

First, according to the steps of Embodiment 1, FIG.
9A is obtained in accordance with the steps of the fifth embodiment. In this embodiment, an example is shown in which the crystalline silicon film is patterned after the laser annealing step (first annealing condition), but the order can be reversed.

Then, a resist mask is formed, and FIG.
A channel doping step is performed under the same conditions as in (C). Thus, a p-type impurity region (b) is formed.

Next, the resist mask is removed, and a new resist mask is formed. Then, an n-type impurity element is added under the same conditions as those in FIG. Thus, an n-type impurity region (b) is formed.

Thereafter, FIG. 9D described in the fifth embodiment will be described.
By performing the same laser annealing step (second annealing condition) as described above, the added n-type or p-type impurity element is activated, and then the steps of FIG. good. The configuration of this embodiment is the same as that of the second embodiment.
It can be implemented when manufacturing the active matrix type liquid crystal display device. The present embodiment and the third embodiment
It is also possible to combine

[Embodiment 7] In this embodiment, a case where a TFT is manufactured in a different process order from that of Embodiment 1 will be described. The other steps are the same as those of the first embodiment, except for the intermediate steps. In addition, the impurity element to be added is also the same as in Example 1.
The same impurity element as described above is taken as an example.

First, according to the steps of Embodiment 1, FIG.
Get the state of. Then, the formed crystalline silicon film 1
A protective film having a thickness of 120 to 150 nm is formed on the substrate 02. Further, a resist mask is formed thereon, and FIG.
A channel doping step is performed under the same conditions as in (C). Thus, a p-type impurity region (b) is formed.

Next, the resist mask and the protective film are removed, and a laser annealing step (first annealing condition) is performed under the same conditions as in FIG. In this step, the crystalline silicon film hidden by the resist mask is improved in crystallinity, and in the p-type impurity region (b), the amorphous silicon film is recrystallized and the added p-type The impurity element is activated.

Next, a protective film is formed again to a thickness of 120 to 150 nm, and a resist mask is formed. Then, an n-type impurity element is added under the same conditions as those in FIG. Thus, an n-type impurity region (b) is formed. )

Next, the resist mask and the protective film are removed, and a laser annealing step (second annealing condition) is performed under the same conditions as in FIG. The added n
The p-type or p-type impurity element is effectively activated.

The laser annealing step (first annealing condition) can be performed with the protective film left. In that case, the step of newly forming a protective film can be reduced, but since laser light is attenuated through the protective film, it is necessary to set a higher laser energy density. Further, the protective film can be left during the laser annealing step (second annealing condition). Also in this case, the laser energy density is set in consideration of the protective film.

Thereafter, the process of FIG.
(F) Subsequent steps may be performed. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

Further, in this embodiment, the laser annealing step is performed in two steps, but may be performed once. In this case, the laser annealing step needs to be the first annealing condition, but this makes it possible to reduce the number of steps.

[Embodiment 8] In this embodiment, a case where a TFT is manufactured in a different process order from that of Embodiment 1 is shown in FIG.
This will be described with reference to FIG. Since the other steps are the same as those of the first embodiment except for the steps in the middle, the same reference numerals are used for the same steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, according to the steps of Embodiment 1, FIG.
Get the state of. Then, the formed crystalline silicon film 1
Then, a protective film 1001 is formed on the substrate 02 with a thickness of 120 to 150 nm. Further, a resist mask 1002 is formed thereon.
Then, an n-type impurity element is added under the same conditions as in FIG. Thus, n-type impurity region (b) 1
006 to 1008 are formed. (FIG. 10A)

Next, resist masks 1002 to 1005
Then, the protective film 1001 is removed, and a laser annealing step (first annealing condition) is performed under the same conditions as those in FIG. In this step, the resist masks 1002 to 1005
The crystalline silicon film hidden by has improved crystallinity,
In the n-type impurity regions (b) 1006 to 1008, the amorphous silicon film is recrystallized and the added n
The type impurity element is activated. (FIG. 10B)

Next, the protective film 1011 is formed again by 120 to 15.
The resist mask 1012 is formed to a thickness of 0 nm. Then, a channel doping step is performed under the same conditions as those in FIG. Thus, p-type impurity region (b) 1013
-1015 are formed. (FIG. 10 (C))

Next, the resist mask 1012 and the protective film 1011 are removed, and a laser annealing step (second annealing condition) is performed under the same conditions as in FIG. This effectively activates the added n-type or p-type impurity element. (FIG. 10 (D))

Note that the process of FIG.
It can be performed with 01 remaining. In this case, the step of newly forming the protective film 1011 can be reduced, but since the laser light is attenuated through the protective film, the laser energy density needs to be set higher. Further, the protective film 1001 can be left at the time of the laser annealing step in FIG.
Also in this case, the laser energy density is set in consideration of the protective film.

Thereafter, the process of FIG.
(F) Subsequent steps may be performed. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

Further, the laser annealing step (first annealing condition) of FIG.
It is characterized in that it also serves in the laser annealing step (D). In this case, it is necessary to change the laser annealing step to the first annealing condition, but this makes it possible to reduce the number of steps.

[Embodiment 9] In this embodiment, a case in which a TFT is manufactured in a different process order from that of Embodiment 1 will be described with reference to FIG.
This will be described with reference to FIG. Since the other steps are the same as those of the first embodiment except for the steps in the middle, the same reference numerals are used for the same steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, according to the process of the first embodiment, the substrate 100
A base film 101 is formed thereover, and a semiconductor film containing an amorphous component is formed thereover. In this embodiment, the amorphous silicon film 1 is used.
101 is formed to a thickness of 30 nm by a plasma CVD method. (FIG. 11A)

Next, a protective film 11 made of an insulating film containing silicon.
02 is formed to a thickness of 120 to 150 nm, and then a resist mask 1103 is formed. Then, a channel doping step is performed under the same conditions as those in FIG. Thus, a p-type impurity region (b) 1104 is formed. (FIG. 11
(B))

Next, the resist mask 1103 is removed,
New resist masks 1106 to 1108 are formed.
Then, an n-type impurity element is added under the same conditions as those in FIG. Thus, n-type impurity regions (b) 1109 to 11
11 is formed. (FIG. 11 (C))

Next, after removing the protective film 1102, according to the technique described in JP-A-7-130652.
The amorphous silicon film to which the n-type or p-type impurity element is added is crystallized to obtain a crystalline silicon film 1112. (FIG. 11D)

When crystallization is performed by using the technique described in Example 2 of JP-A-7-130652, the protective film 1102 can be left as it is. That is, it can be used as a mask film when selectively adding a catalytic element that promotes crystallization.

Next, a laser annealing step (first annealing condition) is performed under the same conditions as in FIG. In this step, the crystallinity of the crystalline silicon film to which the impurity element is not added is improved, and in the region to which the impurity element is added, the amorphous silicon film is recrystallized, and the added n-type or p-type is added. The type impurity element is activated. This step is the same as the step shown in FIG.
It is preferable to perform the process after removing the thermal oxide film formed on the surface of 112. (FIG. 11E)

Thereafter, according to the steps of Embodiment 1, FIG.
(F) Subsequent steps may be performed. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

[Embodiment 10] In this embodiment, a case in which a TFT is manufactured in a different process order from that of Embodiment 1 will be described. The other steps are the same as those of the first embodiment, except for the intermediate steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, according to the steps of the ninth embodiment, FIG.
The state of (A) is obtained. Next, after forming a protective film made of an insulating film containing silicon to a thickness of 120 to 150 nm, a resist mask is formed. Then, an n-type impurity element is added under the same conditions as those in FIG. Thus, an n-type impurity region (b) is formed.

Next, the resist mask is removed, and a new resist mask is formed. Then, a channel doping step is performed under the same conditions as those in FIG. Thus, a p-type impurity region (b) is formed.

Next, after the protective film was removed,
According to the technique described in Japanese Patent No. 30652, an amorphous silicon film to which an n-type or p-type impurity element is added is crystallized to obtain a crystalline silicon film.

Thereafter, the process of FIG.
(E) The subsequent steps may be performed. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

[Embodiment 11] In this embodiment, a case where a TFT is manufactured in a different process order from that of Embodiment 1 is shown in FIG.
2 will be described. Since the other steps are the same as those of the first embodiment except for the steps in the middle, the same reference numerals are used for the same steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, according to the steps of the first embodiment, FIG.
The state of (C) is obtained (FIGS. 12A to 12C). Here, the laser annealing step (second
(Annealing condition) may be performed to activate the p-type impurity element added in the channel doping step.

Next, the crystalline silicon film is patterned to form active layers 1201 to 1204. Then, a gate insulating film 1205 of 80 to 150 nm (110 nm in this embodiment) is formed thereon. Gate insulating film 1205
Can be used as an insulating film containing silicon, but in this embodiment, a silicon oxynitride film is used. (FIG. 12 (D))

Next, resist masks 1206 to 1209 are used.
To form Then, an n-type impurity element is added in the same manner as in FIG. Note that when an impurity element is added through an insulating film having a different thickness, a different acceleration voltage from that in FIG. 1D needs to be set. Thus, n-type impurity regions (b) 1210 to 1212 are formed. (FIG. 12
(E))

Next, resist masks 1206-1209
And a laser annealing step (second annealing condition)
I do. This effectively activates the added n-type or p-type impurity element. At the same time, the interface between the active layer and the gate insulating film is improved. In the case of this embodiment,
Since it is necessary to irradiate a laser beam through a gate insulating film having a thickness of 110 nm, laser annealing conditions must be set based on this. (FIG. 12 (F))

Thereafter, the process shown in FIG.
(B) The subsequent steps may be performed. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

[Embodiment 12] In this embodiment, a case where a TFT is manufactured in a different process order from that of Embodiment 1 will be described. The other steps are the same as those of the first embodiment, except for the intermediate steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, according to the steps of Embodiment 1, FIG.
9A is obtained in accordance with the steps of the fifth embodiment. In this embodiment, an example is shown in which the crystalline silicon film is patterned after the laser annealing step (first annealing condition), but the order can be reversed. Next, after forming a mask, a channel doping step is performed. In this embodiment, an example in which the channel doping step is performed after the active layer forming step is described. However, the order can be reversed.

Thereafter, FIG.
The steps (E) to (F) are performed, and then the subsequent steps may be performed according to the steps of the first embodiment.

The structure of this embodiment can be implemented when the active matrix type liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

[Embodiment 13] In this embodiment, a case in which a TFT is manufactured in a different process order from that of Embodiment 1 will be described. The other steps are the same as those of the first embodiment, except for the intermediate steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, according to the steps of Embodiment 1, FIG.
, And up to the laser annealing step (first annealing condition) according to the step of the seventh embodiment. Next, an active layer is formed by patterning the crystalline silicon film after the laser annealing step (first annealing condition).

Although the present embodiment shows an example in which the crystalline silicon film is patterned after the laser annealing step (first annealing condition), the order can be reversed.

Next, FIG. 12D described in Embodiment 11
A gate insulating film is formed in the same manner as in the step. Thereafter, the steps of FIGS. 12D to 12F are performed according to the eleventh embodiment.
After that, the steps after FIG. 2B may be performed according to the steps of the first embodiment. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

The laser annealing step (first annealing condition) may be omitted, and the step may be combined with a laser annealing step performed after forming the n-type impurity region (b). In this case, it is necessary to change the conditions of the laser annealing step to the first annealing conditions, but this makes it possible to reduce the number of steps. However, in the case of this embodiment, it is necessary to irradiate a laser beam through a 110-nm-thick gate insulating film, so that the laser annealing conditions must be set based on this.

[Embodiment 14] In this embodiment, a case where a TFT is manufactured in a different process order from that of Embodiment 1 will be described. The other steps are the same as those of the first embodiment, except for the intermediate steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, FIG.
The state shown in FIG. 11B is obtained (FIGS. 11A and 11B). next,
The resist mask 1103 is removed.
According to the technique described in Japanese Patent Publication No. 52-52, an amorphous silicon film to which an n-type or p-type impurity element is added is crystallized,
Obtain a crystalline silicon film.

When crystallization is performed using the technique described in Example 2 of JP-A-7-130652, the protective film 1102 can be left as it is. That is, it can be used as a mask film when selectively adding a catalytic element that promotes crystallization.

Next, a laser annealing step (first annealing condition) is performed under the same conditions as in FIG. In this step, the crystallinity of the crystalline silicon film to which the impurity element is not added is improved, and in the region to which the impurity element is added, the amorphous silicon film is recrystallized and the added n-type Alternatively, the p-type impurity element is activated.

Thereafter, according to the eleventh embodiment, FIG.
The steps of (D) to (F) are performed, and then the steps of FIG. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

Further, in place of the channel doping step in this embodiment, a configuration may be adopted in which doping for forming the n-type impurity region (b) is performed.

[Embodiment 15] In this embodiment, a case where a TFT is manufactured in a different process order from that of Embodiment 1 is shown in FIG.
3 will be described. Since the other steps are the same as those of the first embodiment except for the steps in the middle, the same reference numerals are used for the same steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, according to the steps of the first embodiment, FIG.
The state shown in FIG. 13B is obtained (FIGS. 13A and 13B). Further, the state of FIG. 13C is obtained according to the steps of the fourth embodiment. Here, the laser annealing step (second annealing condition) may be performed under the same conditions as in FIG. 1E to activate the n-type impurity element added in the step of FIG.

Next, active layers 1301 to 1304 are formed by patterning the crystalline silicon film. Then, a gate insulating film 1305 having a thickness of 80 to 150 nm (110 nm in this embodiment) is formed thereon. Gate insulating film 1305
Can be used as an insulating film containing silicon, but in this embodiment, a silicon oxynitride film is used. (FIG. 13D)

Next, a resist mask 1306 is formed. Then, a p-type impurity element is added as in FIG. Note that when an impurity element is added through an insulating film having a different thickness, a different acceleration voltage from that in the case of FIG. 1C needs to be set. Thus, the p-type impurity region (b) 1
307 to 1309 are formed. (FIG. 13E)

Next, the resist mask 1306 is removed,
A laser annealing step (second annealing condition) is performed. This effectively activates the added n-type or p-type impurity element. At the same time, the interface between the active layer and the gate insulating film is improved. In the case of the present embodiment, 110 nm
Since it is necessary to irradiate a laser beam through a thick gate insulating film, laser annealing conditions must be set based on this. (FIG. 13 (F))

Thereafter, the process of FIG.
(B) The subsequent steps may be performed. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

[Embodiment 16] In this embodiment, a case where a TFT is manufactured in a different process order from that of Embodiment 1 will be described. The other steps are the same as those of the first embodiment, except for the intermediate steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, according to the steps of Embodiment 1, FIG.
Then, the state of FIG. 9B is obtained according to the fifth embodiment. In this embodiment, an example is shown in which the crystalline silicon film is patterned after the laser annealing step (first annealing condition), but the order can be reversed. In this embodiment, the n-type impurity region (b) is formed after the active layer is formed. However, the order can be reversed.

Thereafter, according to the fifteenth embodiment, FIG.
The steps of (D) to (F) are performed, and then the steps of FIG. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

[Embodiment 17] In this embodiment, a case where a TFT is manufactured in a different process order from that of Embodiment 1 will be described. The other steps are the same as those of the first embodiment, except for the intermediate steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, according to the steps of Embodiment 1, FIG.
10B, and then according to Example 8, FIG.
Get the state of. In this embodiment, an example is shown in which the crystalline silicon film is patterned after the laser annealing step (first annealing condition), but the order can be reversed.

Thereafter, according to the fifteenth embodiment, FIG.
The steps of (D) to (F) are performed, and then the steps of FIG. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

Further, the laser annealing step (first annealing condition) may be omitted, and the laser annealing step performed after forming the n-type impurity region (b) may be combined with the laser annealing step (first annealing condition). In this case, it is necessary to change the conditions of the laser annealing step to the first annealing conditions, but this makes it possible to reduce the number of steps. However, in the case of this embodiment, it is necessary to irradiate a laser beam through a 110-nm-thick gate insulating film, so that the laser annealing conditions must be set based on this.

[Embodiment 18] In this embodiment, a case in which a TFT is manufactured in a different process order from that of Embodiment 1 will be described. The other steps are the same as those of the first embodiment, except for the intermediate steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, according to the steps of Embodiment 1, FIG.
Next, the crystalline silicon film 103 is patterned to form active layers 901 to 904 in the same manner as in the fifth embodiment. In this embodiment, an example is shown in which the crystalline silicon film is patterned after the laser annealing step (first annealing condition), but the order can be reversed.

Then, a gate insulating film 905 of 80 to 150 nm (110 nm in this embodiment) is formed thereon. Although an insulating film containing silicon can be used as the gate insulating film, a silicon oxynitride film is used in this embodiment.

Next, a resist mask is formed. Then, an n-type impurity element is added in the same manner as in FIG. Note that when an impurity element is added through an insulating film having a different thickness, a different acceleration voltage from that in FIG. 1D needs to be set. Thus, an n-type impurity region (b) is formed.

Next, the resist mask is removed, and a new resist mask is formed. Then, a channel doping step is performed under the same conditions as those in FIG. However, when an impurity element is added through insulating films having different thicknesses, FIG.
It is necessary to set an acceleration voltage different from the case (C).
Thus, a p-type impurity region (b) is formed.

Next, the resist mask is removed, and a laser annealing step (second annealing condition) is performed. This effectively activates the added n-type or p-type impurity element. At the same time, the interface between the active layer and the gate insulating film is improved. In the case of this embodiment, it is necessary to irradiate a laser beam through a gate insulating film having a thickness of 110 nm, and therefore, the laser annealing conditions must be set based on this. (

Thereafter, according to the steps of Embodiment 1, FIG.
(B) The subsequent steps may be performed. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

Further, the laser annealing step (first annealing condition) may be omitted, and the step may be combined with the laser annealing step performed after forming the n-type impurity region (b). In this case, it is necessary to change the conditions of the laser annealing step to the first annealing conditions, but this makes it possible to reduce the number of steps. However, in the case of this embodiment, it is necessary to irradiate a laser beam through a 110-nm-thick gate insulating film, so that the laser annealing conditions must be set based on this.

[Embodiment 19] In this embodiment, a case where a TFT is manufactured in a step different from that of Embodiment 1 will be described with reference to FIGS. Since the other steps are the same as those of the first embodiment except for the steps in the middle, the same reference numerals are used for the same steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, in accordance with the steps of Embodiment 1, FIG.
Form up to. FIG. 14B corresponds to FIG.
(A).

After forming resist masks 816 to 820, first refractory metal film 119 and second refractory metal film 1 are formed.
20 and the gate wirings 821 to 82
4 and wiring were formed. At this time, the gate wirings 822 and 823 formed in the drive circuit are n-type impurity regions (b) 11
1 to 113 were formed so as to overlap with a part of the gate insulating film therebetween. This overlapping portion will later become a Lov region.
(FIG. 14 (B))

Next, an n-type impurity element (phosphorus in this embodiment) was added in a self-aligned manner using the gate wirings 821 to 824 as a mask. At this time, impurities were added while the resist masks 816 to 820 used in the wiring and gate wiring formation process were present. The thus formed impurity regions 825 to 830 have 1/1 / th of the n-type impurity region (b).
Adjustment was made so that phosphorus was added at a concentration of 2 to 1/10 (typically 1/3 to 1/4). (FIG. 14C)

However, strictly speaking, the n-type impurity region (b) 11
The phosphorus concentration of the portion overlapping the gate wiring among 1 to 113 remains at 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ , whereas the portion not overlapping the gate wiring is 1 × 10 ¹⁶
Phosphorus at a concentration of ~ 5 × 10 ¹⁸ atoms / cm ³ is added,
It will contain phosphorus at a slightly higher concentration.

By exposing the active layer in this manner, the acceleration voltage can be reduced when the impurity element is added next time. Therefore, the required dose amount can be reduced, and the throughput is improved. Of course, the impurity region may be formed by etching the gate insulating film to expose the active layer and doping.

Next, resist masks 836 to 838 are formed so as to cover the gate wiring, and an n-type impurity element (phosphorus in this embodiment) is added to add impurity regions 8 containing phosphorus at a high concentration.
39 to 847 were formed. (FIG. 14 (D))

Next, a resist mask 848 is formed so as to cover the n-channel type TFT, a p-type impurity element (boron in this embodiment) is added, and impurity regions 849 and 850 containing boron at a high concentration are formed. .

Note that the masks 816 to 8 used in this embodiment were used.
20, 836 to 838, and 848 use a mask made of a photosensitive resin such as a resist exposed using a photomask, but may be a mask mainly containing silicon patterned using a resist mask or the like. Good. However, similarly, the masks 816 to 820, 836 to 838, and 848
Requires a film thickness capable of preventing implantation of oxygen ions or the like into the gate electrode.

Thereafter, according to the steps of Embodiment 1, FIG.
(C) The subsequent steps may be performed. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

[Embodiment 20] In this embodiment, a case where a TFT is manufactured by a process different from that of Embodiment 1 will be described with reference to FIGS.
17 will be described. Since the other steps are the same as those of the first embodiment except for the steps in the middle, the same reference numerals are used for the same steps. Further, the same impurity element as that of the first embodiment is taken as an example of the impurity element to be added.

First, according to the steps of Embodiment 1, FIG.
Form up to. FIGS. 15A to 15D correspond to FIGS. 1A to 1D, respectively.

Next, resist masks 1501 to 1503
Was formed, and an impurity element imparting p-type (hereinafter, referred to as a p-type impurity element) was added via the protective film 104 to form impurity regions 1504 and 1505 containing boron at a high concentration. (FIG. 15E)

Next, the protective film 104 was removed, and a laser beam irradiation step was performed again. Since the laser light irradiation step is for the purpose of activating the added impurity element,
It is preferable that the irradiation be performed with energy that does not melt the crystalline silicon film. Further, it is possible to perform the laser annealing step with the protective film 104 attached. (Figure 1
6 (A))

Next, unnecessary portions of the crystalline silicon film were removed, and island-like semiconductor films (hereinafter, referred to as active layers) 115 to 117 and 1506 were formed as in Example 1. (FIG. 16 (B))

Next, the active layer 114 is formed in the same manner as in the first embodiment.
To 117, a gate insulating film 118 was formed. (FIG. 16 (C))

Next, in the same manner as in Example 1, a high-melting point metal film serving as a gate wiring was formed. In this embodiment, a 50-nm-thick tungsten nitride (WNx) film is used as the first refractory metal film 119, and a second refractory metal film 120 is used as the second refractory metal film 120.
A 350 nm thick tungsten film was used. (FIG. 16
(D))

Next, resist masks 1507 to 1511 are used.
Was formed, and the first refractory metal film 119 and the second refractory metal film 120 were collectively etched to form gate wirings 1513 to 1516 and a wiring 1512 having a thickness of 400 nm. At this time, the gate wiring 150 formed in the drive circuit
Reference numerals 9 and 1510 are formed so as to overlap a part of the n-type impurity region (b) with a gate insulating film interposed therebetween. (FIG. 16E)

Next, an n-type impurity element (phosphorus in this embodiment) was added in a self-aligned manner using the gate wirings 1513 to 1516 as a mask. The impurity region 15 thus formed
17 to 1522 are に は of the n-type impurity region (b).
Adjustment was made so that phosphorus was added at a concentration of １ ／ 1/10 (typically 〜 to ４). (FIG. 16F)

Next, resist masks 1507 to 1511 are used.
While the resist masks 1523 to 1523
26, and an n-type impurity element (phosphorus in this embodiment) is added to add impurity regions 1527 to 1527 containing phosphorus at a high concentration.
33 were formed. Of course, the impurity region may be formed by etching the gate insulating film to expose the active layer and doping. Also in this case, the ion doping method using phosphine (PH ₃ ) is performed, and the phosphorus concentration in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ (typically, 2 × 1
0 ^{20 to} 5 × 10 ²⁰ atoms / cm ³ ). (FIG. 17
(A))

In the above-described formation of each impurity region, an example has been described in which ion doping is performed while a resist mask is held on the upper surface of the gate electrode. However, instead of the resist mask, silicon patterned by using a mask or the like is used. May be used. However, this mask needs to have a thickness capable of preventing implantation of oxygen ions or the like into the gate electrode. Note that the mask containing silicon as its main component may be formed using a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a stacked film obtained by combining them.

Next, resist masks 1507 to 151 are used.
After removing 1, 1523 to 1526, an insulating film 151 to be a part of the first interlayer insulating film was formed as in Example 1.

Thereafter, as in Example 1, a heat treatment step was performed to activate the n-type or p-type impurity elements added at the respective concentrations. (FIG. 17B)

At this time, the catalytic element (nickel in this embodiment) used for crystallization of the amorphous silicon film in this embodiment.
Moved in the direction indicated by the arrow and was captured (gettered) in the high-concentration phosphorus-containing region formed in the above-described step. This is a phenomenon caused by the gettering effect of the metal element by phosphorus, and as a result, the channel formation region 1
534 and 153 to 156 indicate that the concentration of the catalyst element is 1 × 1
0 ¹⁷ atoms / cm ³ or less (preferably 1 × 10 ¹⁶ atoms / cm ³ or less).

Further, a heat treatment was carried out at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the active layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
May be performed.

After the activation step, the steps after FIG. 3C may be performed according to the steps of the first embodiment. However, in this embodiment, after forming the interlayer insulating film 167, a thin silicon oxide film 174 is formed by sputtering, and the shielding film 16 is formed.
8 and the interlayer insulating film 167 were improved in adhesion. Further, the silicon oxide film 174 may be etched to have the same pattern as the light shielding film 168. Note that the configuration of this embodiment can be implemented when the active matrix liquid crystal display device of Embodiment 2 is manufactured. Further, it is possible to combine the present embodiment and the third embodiment.

[Embodiment 21] In this embodiment, a process of forming a semiconductor film to be an active layer (active layer) of a TFT will be described with reference to FIGS. The crystallization means of the present embodiment is a technique described in Embodiment 1 of Japanese Patent Application Laid-Open No. Hei 7-130652.

First, a substrate (a glass substrate in this embodiment) 1
A base film 1802 made of a 200-nm-thick silicon oxynitride film and a 200-nm-thick amorphous semiconductor film (amorphous silicon film in this embodiment) 1803 are formed on 801. In this step, the base film and the amorphous semiconductor film may be formed continuously without exposing to the atmosphere.

Next, an aqueous solution (aqueous nickel acetate solution) containing 10 ppm by weight of a catalytic element (nickel in this embodiment) is applied by a spin coating method, and a catalytic element containing layer 1804 is formed on the amorphous semiconductor film 1803. Formed over the entire surface.
The catalyst elements usable here are germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), and cobalt (C) in addition to nickel (Ni).
o), platinum (Pt), copper (Cu), and gold (Au). (FIG. 18A)

In this embodiment, a method of adding nickel by spin coating is used. However, a thin film made of a catalytic element (a nickel film in this embodiment) is formed of an amorphous semiconductor by vapor deposition or sputtering. Means for forming on a film may be used.

Next, 400 to 5 prior to the crystallization step.
After performing a heat treatment step at 00 ° C. for about 1 hour to desorb hydrogen from the film, the heat treatment step is performed at 500 to 650 ° C. (preferably 550 ° C.).
To 570 ° C) for 4 to 12 hours (preferably 4 to 6 hours)
Is performed. In this embodiment, a heat treatment is performed at 550 ° C. for 4 hours to form a crystalline semiconductor film (a crystalline silicon film in this embodiment) 1805. (FIG. 18 (B))

Here, the same laser annealing step (first annealing condition) as in FIG. 1E of the first embodiment may be performed to improve the crystallinity of the crystalline semiconductor film 1805.

Next, the nickel used in the crystallization step is bonded.
A gettering step for removing the amorphous silicon film is performed.
First, the mask insulating film 1 is formed on the surface of the crystalline semiconductor film 1805.
806 is formed to a thickness of 150 nm and is patterned.
An opening 1807 is formed. And the exposed crystalline
For the semiconductor film, an element belonging to Group 15 (in this embodiment,
) Is performed. By this step, 1 × 10¹⁹
~ 1 × 10²⁰atoms / cm ^ThreeGetterin containing phosphorus at a concentration of
Forming region 1808 is formed. (FIG. 18 (C))

Next, at 450 to 650 ° C. in a nitrogen atmosphere.
(Preferably 500 to 550 ° C.) and a heat treatment step for 4 to 24 hours (preferably 6 to 12 hours) are performed. By this heat treatment step, nickel in the crystalline semiconductor film moves in the direction of the arrow, and is captured in the gettering region 1808 by the gettering action of phosphorus. That is, since nickel is removed from the crystalline semiconductor film, the crystalline semiconductor film 1809 is removed.
Is less than 1 × 10 ¹⁷ atms / cm ³ ,
Preferably, it can be reduced to 1 × 10 ¹⁶ atms / cm ³ . (FIG. 18D)

The crystalline semiconductor film 1809 formed as described above is formed of a crystalline semiconductor film having extremely high crystallinity by using a catalytic element (nickel in this case) that promotes crystallization. . After the crystallization, the catalytic element is removed by the gettering action of phosphorus, and the concentration of the catalytic element remaining in the crystalline semiconductor film 1809 (except for the gettering region) is 1 × 10 ¹⁷ atms / c.
m ³ or less, preferably 1 × 10 ¹⁶ atms / cm ³ .

This embodiment is characterized in that after a crystalline semiconductor film crystallized by using a catalytic element is formed, a gettering region (a high concentration of 15%) is formed in a region not used as an active layer.
A region containing an impurity element belonging to group III) is formed, and the catalyst element used for crystallization is gettered by heat treatment.

The structure of this embodiment can be freely combined with any of the structures shown in Embodiments 1 to 20.

[Embodiment 22] In this embodiment, a process of forming a semiconductor film to be an active layer (active layer) of a TFT will be described with reference to FIG. Specifically, Japanese Patent Application Laid-Open No. 10-247
No. 735 (corresponding to U.S. Application No. 09 / 034,041) is used.

First, a substrate (a glass substrate in this embodiment) 1
A base film 1902 made of a 200-nm-thick silicon oxynitride film and a 200-nm-thick amorphous semiconductor film (amorphous silicon film in this embodiment) 1903 are formed on a substrate 901. In this step, the base film and the amorphous semiconductor film may be formed continuously without exposing to the atmosphere.

Next, a mask insulating film 19 made of a silicon oxide film
04 is formed to a thickness of 200 nm, and an opening 1905 is formed.

Next, an aqueous solution (aqueous nickel acetate solution) containing 100 ppm by weight of a catalytic element (nickel in this embodiment) is applied by spin coating to form a catalytic element-containing layer 1906. At this time, the catalyst element-containing layer 1906
Selectively contacts the amorphous semiconductor film 1903 in the region where the opening 1905 is formed. The catalyst elements that can be used here are, in addition to nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), and platinum (P).
t), copper (Cu), and gold (Au).
(FIG. 19A)

In this embodiment, the method of adding nickel by spin coating is used. However, a thin film made of a catalytic element (a nickel film in this embodiment) is formed of an amorphous semiconductor by vapor deposition or sputtering. Means for forming on a film may be used.

Next, 400 to 5 prior to the crystallization step.
After performing a heat treatment step at 00 ° C. for about 1 hour to desorb hydrogen from the film, the heat treatment step is performed at 500 to 650 ° C. (preferably 550 ° C.).
(To 600 ° C.) for 6 to 16 hours (preferably 8 to 14 hours). In this embodiment, the heat treatment is performed at 570 ° C. for 14 hours. As a result, crystallization proceeds from the opening 1905 as a starting point in a direction substantially parallel to the substrate (the direction indicated by the arrow), and the crystalline semiconductor film in which macroscopic crystal growth directions are aligned (the crystalline silicon film in this embodiment). A film 1907 is formed. (FIG. 19B)

Next, a gettering step of removing nickel used in the crystallization step from the crystalline silicon film is performed.
In this embodiment, a step of adding an element belonging to Group 15 (phosphorus in this embodiment) using the previously formed mask insulating film 1904 as a mask is performed, and 1 × 10 ¹⁹ is added to the crystalline semiconductor film exposed in the opening 1905. ~ 1 × 10 ²⁰ atoms / cm
A gettering region 1908 containing phosphorus at a concentration of ³ is formed. (FIG. 19C)

Next, at 450 to 650 ° C. in a nitrogen atmosphere.
(Preferably 500 to 550 ° C.) and a heat treatment step for 4 to 24 hours (preferably 6 to 12 hours) are performed. By this heat treatment step, nickel in the crystalline semiconductor film moves in the direction of the arrow, and is captured in the gettering region 1908 by the gettering action of phosphorus. That is, since nickel is removed from the crystalline semiconductor film, the crystalline semiconductor film 1909 is removed.
Is less than 1 × 10 ¹⁷ atms / cm ³ ,
Preferably, it can be reduced to 1 × 10 ¹⁶ atms / cm ³ . (FIG. 19D)

The crystalline semiconductor film 1909 formed as described above is crystallized by selectively adding a catalytic element (here, nickel) which promotes crystallization.
It is formed of a crystalline semiconductor film having very good crystallinity.
Specifically, it has a crystal structure in which rod-shaped or columnar crystals are arranged with a specific direction. After the crystallization, the catalytic element is removed by the gettering action of phosphorus, and the concentration of the catalytic element remaining in the crystalline semiconductor film 1909 is 1 × 10 ¹⁷ atms / cm ³ or less, preferably 1 × 10 ¹⁷ atms / cm ³ or less. 10
¹⁶ atms / cm ³ .

It should be noted that this embodiment is characterized in that after a crystalline semiconductor film crystallized using a catalytic element is formed, a gettering region (15% high concentration) is formed in a region not used as an active layer.
A region containing an impurity element belonging to group III) is formed, and the catalyst element used for crystallization is gettered by heat treatment.

The structure of this embodiment can be freely combined with any of the structures shown in Embodiments 1 to 21.

[Embodiment 23] FIG. 20 shows an example of various wiring structures formed on an insulating surface using the present invention.
FIG. 20A shows a film (or substrate) 1 having an insulating surface.
A cross-sectional view of a single-layer wiring formed of a material 1701 containing tungsten as a main component is shown on 700. This wiring is
A target having a purity of 4N or more is used as a target, and argon (Ar), krypton (K
r), a film formed using a single gas such as xenon (Xe) or a mixed gas thereof is formed by patterning. The conditions such as sputtering power, gas pressure, and substrate temperature may be appropriately controlled by the practitioner.

The wiring 1701 thus obtained contains almost no impurity element, and particularly has an oxygen content of 3
0 ppm or less, and the electric resistivity is 40 μΩ.
Cm or less, typically 6 μ to 15 μΩ · cm. Further, the stress of the film is −5 × 10 ^{9 to} 5 ×
It can be 10 ⁹ dyn / cm ² .

FIG. 20B shows a two-layer structure similar to that of the first embodiment. In addition, tungsten nitride (WNx)
Is the lower layer, and tungsten is the upper layer. Note that the thickness of the tungsten nitride film 1702 is 10 to 50 nm (preferably, 10 to 30 nm), and the thickness of the tungsten film 1703 is 2 nm.
The thickness may be from 00 to 400 nm (preferably from 250 to 350 nm). In this embodiment, the layers are continuously formed by a sputtering method without exposure to the air.

FIG. 20C shows that the wiring 1704 made of a material containing tungsten as a main component and formed on a film (or substrate) 1700 having an insulating surface is formed on the insulating film 17.
It is an example covered with 05. The insulating film 1705 is a silicon nitride film,
Silicon oxide film, silicon oxynitride film SiOxNy (where 0 <
x, y <1) or a laminated film combining them may be used.

FIG. 20D shows an example in which the surface of a wiring 1706 formed of a material containing tungsten as a main component and formed on a film (or substrate) 1700 having an insulating surface is covered with a tungsten nitride film 1707. is there. Note that FIG.
When the nitriding treatment such as plasma nitridation is performed on the wiring in the state of 0 (A), the structure of FIG. 20 (D) is obtained.

FIG. 20E shows an example in which a wiring 1709 formed of a material containing tungsten as a main component and formed on a film (or substrate) 1700 having an insulating surface is surrounded by tungsten nitride films 1710 and 1708. is there. This structure has the same shape as that shown in the third embodiment. In addition,
When the wiring in the state of FIG. 20B is subjected to nitriding treatment such as plasma nitridation, the structure of FIG. 20E is obtained.

FIG. 20F shows an example in which the state shown in FIG. 20E is formed and then covered with an insulating film 1711. The insulating film 1711 may be formed using a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a stacked film including a combination thereof.

As described above, the present invention can be applied to various wiring structures. The configuration of this embodiment is the same as that of the first and second embodiments.
2 can be freely combined with any of the configurations shown in FIG.

[Embodiment 24] In this embodiment, a case where the present invention is applied to a reflective liquid crystal display device manufactured on a silicon substrate will be described. In the present embodiment, a TFT structure is realized by adding an impurity element that directly imparts n-type or p-type to a silicon substrate (silicon wafer) instead of the active layer made of a crystalline silicon film in the first embodiment. Just do it. In addition, since the pixel electrode is of a reflective type, a metal film with high reflectance (for example, aluminum, silver, or an alloy thereof (Al-Ag alloy)) or the like may be used as a pixel electrode.

That is, an n-channel type TF which includes at least a pixel portion and a driving circuit on the same substrate and forms a driving circuit
The LDD region of T is arranged so that at least a part or all thereof overlaps with the gate wiring, and the pixel T
The LDD region of the FT is arranged so as not to overlap the gate wiring, and the LDD region of the n-channel TFT forming the drive circuit is formed.
The region has a higher concentration of n than the LDD region of the pixel TFT.
Any structure may be used as long as the structure includes an impurity element for imparting a mold.

The structure of this embodiment is similar to that of Embodiments 1 to 23.
Any configuration can be freely combined.

[Embodiment 25] The present invention relates to a conventional MOSFE.
It is also possible to form an interlayer insulating film on T and use it when forming a TFT thereon. That is, it is possible to realize a semiconductor device having a three-dimensional structure. It is also possible to use an SOI substrate such as SIMOX, Smart-Cut (registered trademark of SOITEC), or ELTRAN (registered trademark of Canon Inc.) as the substrate.

The structure of this embodiment is similar to those of Embodiments 1 to 24.
Any configuration can be freely combined.

[Embodiment 26] The present invention can also be applied to an active matrix EL display.
An example is shown in FIG.

FIG. 21 is a circuit diagram of an active matrix EL display. Reference numeral 81 denotes a display area, around which an X-direction drive circuit 82 and a Y-direction drive circuit 83 are provided. Each pixel in the display area 81 has a switching TFT 84, a storage capacitor 85, a current controlling TFT 86, and an organic EL element 87.
An X-direction signal line 88a (or 88b) and a Y-direction signal line 89a (or 89b, 89c) are connected to T84. The power supply lines 90a and 90b are connected to the current control TFT 86.

In the active matrix type EL display of this embodiment, the TFTs used in the X-direction drive circuit 82 and the Y-direction drive circuit 83 are replaced by the p-channel type TFT shown in FIG.
The FT 301 and the n-channel TFT 302 or 303 are formed in combination. Further, the switching TFT 84 and the current control TFT 86 are formed by the n-channel TFT 304 in FIG. 4A.

[Embodiment 27] A liquid crystal display device manufactured according to the present invention can use various liquid crystal materials. Such materials include TN liquid crystal, PDLC (polymer dispersed liquid crystal), FLC (ferroelectric liquid crystal), AFLC
(An anti-strongly inducing electro-liquid crystal), or a mixture of FLC and AFLC.

For example, “H. Furue et al .; Charakteristi
cs and Drivng Scheme of Polymer-Stabilized Monosta
ble FLCD Exhibiting Fast Response Time and High Co
ntrast Ratio with Gray-Scale Capability, SID, 199
8 "," T. Yoshida et al .; A Full-Color Thresholdless "
Antiferroelectric LCD Exhibiting Wide Viewing Ang
le with Fast Response Time, 841, SID97DIGEST, 199
7 ", or the materials disclosed in US Pat. No. 5,594,569.

In particular, a thresholdless antiferroelectric liquid crystal (Thresholdless Antiferroelectric LCD:
TL-AFLC) can be used to reduce the operating voltage of the liquid crystal to about ± 2.5 V.
In some cases, about 8 V may be enough. That is, the driving circuit and the pixel portion can be operated at the same power supply voltage, and the power consumption of the entire liquid crystal display device can be reduced.

Also, the ferroelectric liquid crystal and the antiferroelectric liquid crystal are
There is an advantage that the response speed is faster than that of the N liquid crystal. Since the crystalline TFT used in the above embodiment can realize a TFT having a very high operation speed, a high image response speed utilizing the high response speed of the ferroelectric liquid crystal or the antiferroelectric liquid crystal can be realized. It is possible to realize a liquid crystal display device.

It is needless to say that it is effective to use the liquid crystal display device of this embodiment as a display for electronic equipment such as a personal computer.

The structure of this embodiment is similar to those of Embodiments 1 to 25.
Any configuration can be freely combined.

[Embodiment 28] A CMOS circuit and a pixel portion formed by carrying out the present invention can be implemented in various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC).
Display). That is, the invention of the present application can be applied to all electronic devices in which these electro-optical devices are incorporated in a display unit.

Such electronic devices include a video camera, digital camera, projector (rear or front type), head mounted display (goggle type display), car navigation, car stereo,
Examples include a personal computer and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). Examples of these are shown in FIGS. 22, 26 and 27.

FIG. 22A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other driving circuits.

FIG. 22B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102 and other driver circuits.

FIG. 22C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205 and other driving circuits.

FIG. 22D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on. The present invention can be applied to the display portion 2302 and other driving circuits.

FIG. 22E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other driving circuits.

FIG. 22F shows a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 2502 and other driving circuits.

FIG. 26A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other driving circuits.

FIG. 26B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to a liquid crystal display device 2808 forming a part of the LCD 702 and other driving circuits.

FIG. 26C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 26A and 26B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 26D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 26C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 26D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 26, a case where a transmissive electro-optical device is used is shown, and examples of application to a reflective electro-optical device and an EL display device are not shown.

FIG. 27A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the audio output unit 2902, the audio input unit 2903, the display unit 2904, and other driving circuits.

[0300] FIG. 27B illustrates a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003 and other signal circuits.

FIG. 27C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of Embodiments 1 to 27.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of Embodiments 1 to 27.

[0304]

According to the present invention, the amount of oxygen contained in the wiring material is not more than 30 ppm, the electric resistance is low,
A good wiring having low stress can be formed.

Further, by forming tungsten nitride on the surface of a wiring containing tungsten as a main component, a wiring having low resistance and high reliability can be obtained, and a semiconductor device (specifically, an electro-optical device here) can be obtained. Operation performance and reliability can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 2 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 3 is a view showing a manufacturing process of an AM-LCD.

FIG. 4 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 5 is a sectional structural view of an n-channel TFT.

FIG. 6 is a perspective view of an active matrix liquid crystal display device.

FIG. 7 illustrates a structure of a pixel portion and a driver circuit.

FIG. 8 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 9 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 10 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 11 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 12 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 13 is a view showing a manufacturing process of an AM-LCD.

FIG. 14 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 15 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 16 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 17 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 18 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor film.

FIG. 19 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor film.

FIG. 20 is a cross-sectional view illustrating a wiring structure.

FIG. 21 illustrates a structure of an active matrix EL display device.

FIG. 22 illustrates an example of an electronic device.

FIG. 23 is a diagram showing a relationship between a sputtering pressure and a stress.

FIG. 24 is a graph showing a relationship between sputtering pressure and electric resistivity.

FIG. 25 is a diagram showing the number of pinholes after heat treatment.

FIG 26 illustrates an example of an electronic device.

FIG. 27 illustrates an example of an electronic device.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/3205 H01L 21/88 R 29/43 29/46 R 29/78 612B 617M

Claims (19)

[Claims] 1. A wiring material containing tungsten as a main component, wherein the content of oxygen in the wiring material is 30 pp.
m or less, and the wiring material contains argon. 2. The wiring material according to claim 1, wherein said wiring material has an electric resistivity of 40 μΩ · cm or less. 3. A semiconductor device comprising a wiring having a stacked structure including a tungsten film and a tungsten nitride film on an insulating surface. 4. A tungsten nitride film on an insulating surface;
A semiconductor device, comprising: a wiring laminated with a tungsten film, wherein a surface of the tungsten film is covered with a tungsten nitride film. 5. The semiconductor device according to claim 3, wherein the wiring contains argon and the amount of oxygen is 30 ppm or less. 6. The method according to claim 3, wherein the stress of the tungsten film is −5 × 10 ⁹ or more and 5 × 1
A semiconductor device characterized by being at most ⁹ dyn / cm ² . 7. The semiconductor device according to claim 3, wherein said wiring has a line width of 5 μm or less. 8. The semiconductor device according to claim 3, wherein said wiring has a thickness of 0.1 to 0.7 μm. 9. The semiconductor device according to claim 3, wherein said wiring is used as a gate wiring of a TFT. 10. A semiconductor device including at least a pixel portion and a driving circuit on the same substrate, wherein at least a part or the entirety of an LDD region of an n-channel TFT forming the driving circuit is an n-channel TF.
The LDD region of the n-channel TFT forming the driving circuit is arranged so as to overlap with the gate wiring of T and has a higher concentration of n than the LDD region of the pixel TFT.
An impurity element for imparting a mold is included, wherein the gate wiring is formed in contact with the first gate wiring and the first gate wiring formed in contact with an insulating film, and is formed inside the first gate wiring. A second gate wiring, and a third gate wiring formed in contact with the first gate wiring and the second gate wiring. 11. A semiconductor device including at least a pixel portion and a driving circuit on the same substrate, wherein at least a part or all of an LDD region of the n-channel TFT forming the driving circuit has a gate of the n-channel TFT. The LDD region of the pixel TFT forming the pixel portion is arranged so as to overlap with the wiring, and the LDD region of the n-channel TFT forming the driving circuit is arranged so as not to overlap with the gate wiring of the pixel TFT. Contains an impurity element that imparts n-type at a higher concentration than the LDD region of the pixel TFT,
A first gate wiring formed in contact with an insulating film; a second gate wiring formed in contact with the first gate wiring and formed inside the first gate wiring; A semiconductor device comprising: one gate wiring; and a third gate wiring formed in contact with the second gate wiring. 12. The method according to claim 10, wherein
The first gate line is made of a material mainly containing a nitride layer of tungsten, the second gate line is made of a material mainly containing tungsten, and the third gate line is made of the second material. A semiconductor device comprising a material mainly containing a nitride layer formed by nitriding a gate wiring. 13. The semiconductor device according to claim 3, wherein the semiconductor device is an active matrix type liquid crystal display, an active matrix type EL display, or an active matrix type EC display. 14. The semiconductor device according to claim 3, which is a video camera, a digital camera, a projector, a goggle type display, a car navigation, a personal computer, and a portable information terminal. 15. A method for manufacturing a semiconductor device including at least a pixel portion and a driver circuit on the same substrate, comprising: forming an active layer on the substrate; and forming a gate insulating film in contact with the active layer. Forming a gate wiring having tungsten as a main component on the gate insulating film; and forming an impurity region by adding an impurity element in a self-aligned manner using the gate wiring as a mask. Forming a mask using a gate wiring provided with a mask on at least an upper surface thereof as a mask. 16. A method for manufacturing a semiconductor device including at least a pixel portion and a driver circuit on the same substrate, comprising: forming an active layer on the substrate; and forming a gate insulating film in contact with the active layer. Forming a gate wiring mainly containing tungsten on the gate insulating film, forming an impurity region by adding an impurity element in a self-aligned manner using the gate wiring as a mask, and nitriding the gate wiring. Performing a process to form a nitride film on the surface of the gate wiring. 17. The method for manufacturing a semiconductor device according to claim 16, wherein said nitriding treatment is performed by generating plasma in an ammonium gas atmosphere. 18. The method for manufacturing a semiconductor device according to claim 15, wherein the gate wiring has a stacked structure including a tungsten film and a tungsten nitride film. 19. The method for manufacturing a semiconductor device according to claim 15, wherein the gate wiring is formed by a sputtering method.