KR100242990B1 - Polysilicon etching method - Google Patents
Polysilicon etching method Download PDFInfo
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- KR100242990B1 KR100242990B1 KR1019960061764A KR19960061764A KR100242990B1 KR 100242990 B1 KR100242990 B1 KR 100242990B1 KR 1019960061764 A KR1019960061764 A KR 1019960061764A KR 19960061764 A KR19960061764 A KR 19960061764A KR 100242990 B1 KR100242990 B1 KR 100242990B1
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- polysilicon
- polysilicon layer
- photoresist pattern
- etching
- etching method
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
Abstract
본 발명은 폴리실리콘층의 식각 프로파일(Etch profile) 각도가 수직에 가깝게 되도록 조절할 수 있는 폴리실리콘 식각방법에 관한 것으로, 소정의 하지막 위에 폴리실리콘을 증착한 후, 그 위에 포토레지스트패턴을 형성하는 단계와; 그 포토레지스패턴에 따라 개방된 상기 폴리실리콘층의 식각영역에 아르곤이온을 주입하는 단계와; 상기 폴리실리콘을 선택적으로 건식각한 후, 상기 포토레지스트패턴을 제거하는 단계로 이루어진 폴리실리콘 패터닝 공정에 있어서, 상기 아르곤이온의 주입량은 1.0E13-2.0E15의 범위에서 이루어지고, 폴리실리콘층에 대한 건식각은 공정가스가 CF2+ 8O2로 이루어지거나 CH4+ O2+ SF6로 이루어지는 것을 특징으로 한다. 이와 같은 본 발명에 따른 폴리실리콘층의 식각 프로파일 각도는 55-75° 정도가 된다.The present invention relates to a polysilicon etching method that can be adjusted so that the etch profile angle of the polysilicon layer is close to the vertical, and after depositing polysilicon on a predetermined base film, to form a photoresist pattern thereon Steps; Implanting argon ions into an etching region of the polysilicon layer opened according to the photoresist pattern; In the polysilicon patterning process comprising the step of selectively dry etching the polysilicon, and removing the photoresist pattern, the amount of the argon ion implantation is made in the range of 1.0E13-2.0E15, to the polysilicon layer dry etching is characterized in that the process gas is made or a CF 2 + 8O 2 consisting of CH 4 + O 2 + SF 6 . The etch profile angle of the polysilicon layer according to the present invention is about 55-75 °.
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 폴리실리콘층의 식각 프로파일(Etch profile) 각도가 수직에 가깝게 되도록 조절할 수 있는 폴리실리콘 식각방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a polysilicon etching method which can be adjusted so that an etching profile angle of a polysilicon layer is close to a vertical.
소정의 하지막 위에 증착된 폴리실리콘층을 패터닝하기 위한 포토리소그래피 및 식각공정에 있어서, 상기 폴리실리콘층의 식각 프로파일 각도를 조절하는 방법에 대한 일실시예로, 그 폴리실리콘층 위에 형성된 소정의 마스크패턴에 따라 그의 식각 영역이 개방된 상기 폴리실리콘층에 아르곤이온을 주입한 후, 그 폴리실리콘층을 식각하는 방법이 있다. 이에 대해서 첨부된 제1도와 제2도를 참조하여 설명하면 다음과 같다.In a photolithography and etching process for patterning a polysilicon layer deposited on a predetermined base layer, an embodiment of a method of controlling an etch profile angle of the polysilicon layer, the predetermined mask formed on the polysilicon layer After argon ion is injected into the polysilicon layer whose etching region is opened according to the pattern, there is a method of etching the polysilicon layer. This will be described with reference to FIGS. 1 and 2.
우선, 제1도는 포토레지스트패턴에 따라 개방된 식각영역에 아르콘이온(Ar+)이 1.0E12 -5.0E12 범위의 농도로 주입된 폴리실리콘층을 상기 포토레지스트패턴에 따라 식각한 경우에 형성되는 프로파일 단면도로서, 이에 도시된 바와 같이 폴리실리콘층의 식각면이 하부로 갈수록 증가하는 곡면구조의 보울형(Bowl type)으로 형성되었다.First, FIG. 1 is a profile formed when a polysilicon layer in which arcon ion (Ar + ) is implanted in a concentration range of 1.0E12 -5.0E12 is etched according to the photoresist pattern in an open etching region according to a photoresist pattern. As a cross-sectional view, the etching surface of the polysilicon layer is formed in a bowl type of curved structure that increases toward the bottom as shown in the figure.
그리고, 제2도는 식각영역에 아르곤이온(Ar+)이 1.0E13-2.0E15 범위의 농도로 주입된 폴리실리콘층을 식각한 경우에 형성되는 프로파일 단면도로서, 이에 도시된 바와 같이 폴리실리콘층의 식각면이 45-55° 정도로 경사진 평면구조의 평행사변형으로 형성되었다.FIG. 2 is a cross-sectional view of a profile formed when the polysilicon layer in which argon ions (Ar + ) are implanted in a concentration range of 1.0E13-2.0E15 is etched. The plane was formed as a parallelogram with a planar inclined plane of about 45-55 °.
그러나, 상기와 같은 종래 기술은 위에서 설명한 바와 같이 식각된 폴리실리콘층이 보울형으로 형성되거나 식가면의 경사각이 44-55° 정도인 평형사변형으로 형성되는 단점이 있다.However, the prior art as described above has a disadvantage in that the etched polysilicon layer is formed in a bowl shape or an equilibrium quadrangle having an inclination angle of the edible surface of about 44-55 ° as described above.
이에 본 발명은 폴리실리콘층의 식각면이 수직에 가까운 경사각이 될 수 있도록 하는데 적당한 폴리실리콘 식각방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a polysilicon etching method suitable for allowing the etching surface of the polysilicon layer to have an inclination angle close to vertical.
제1도와 제2도는 종래 기술에 따른 폴리실리콘의 식각 프로파일을 나타낸 단면도.1 and 2 are cross-sectional views showing the etching profile of the polysilicon according to the prior art.
제3(a)도 제3(c)도는 본 발명에 따른 폴리실리콘 식각방법을 타나낸 공정 단면도.3 (a) and 3 (c) is a cross-sectional view showing a polysilicon etching method according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 실리콘기판 23, 23a : 폴리실리콘10: silicon substrate 23, 23a: polysilicon
30 : 포토레지스트30: photoresist
상기 목적을 달성하기 위한 본 발명은, 소정의 하지막 위에 폴리실리콘을 증착한 후, 그 위에 포토레지스트패턴을 형성하는 단계와; 그 포토레지스패턴에 따라 개방된 상기 폴리실리콘층의 식각영역에 아르곤이온을 주입하는 단계와; 상기 폴리실리콘을 선택적으로 건식각한 후, 상기 포토레지스트패턴을 제거하는 단계로 이루어진 폴리실리콘 패터닝 공정에 있어서, 상기 아르곤이온의 주입량은 1.0E13-2.0E15의 범위에서 이루어지고, 폴리실리콘층에 대한 건식각은 공정가스가 CF4+ 8O2로 이루어지거나 CF4+ O2+ SF6로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of: depositing polysilicon on a predetermined base film, and then forming a photoresist pattern thereon; Implanting argon ions into an etching region of the polysilicon layer opened according to the photoresist pattern; In the polysilicon patterning process comprising the step of selectively dry etching the polysilicon, and removing the photoresist pattern, the amount of the argon ion implantation is made in the range of 1.0E13-2.0E15, to the polysilicon layer dry etching is characterized in that the process gas is made or a CF 4 + 8O 2 consisting of CF 4 + O 2 + SF 6 .
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해서 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
먼저, 제3(a)도에 도시된 바와 같이 실리콘기판(10) 위에 폴리실리콘(23)을 증착한 후, 그 위에 포토레지스트패턴(30)을 형성하고, 그 포토레지스패턴(30)에 따라 개방된 상기 폴리실리콘층(23)의 식각영역에 아르곤이온(Ar+)을 주입한다. 이때, 상기 폴리실리콘층(23)의 개방영역에 대한 아르곤이온(Ar+)의 주입은, 농도가 1.0E13-2.0E15의 범위이고, 에너지가 30[keV]-50[keV]의 범위인 조건하에서 이루어지는 것이 바람직하다.First, as shown in FIG. 3A, the polysilicon 23 is deposited on the silicon substrate 10, and then the photoresist pattern 30 is formed thereon, and the photoresist pattern 30 is Argon ions (Ar + ) are implanted into the etched region of the open polysilicon layer 23. At this time, the implantation of argon ions (Ar + ) into the open region of the polysilicon layer 23, the concentration is in the range of 1.0E13-2.0E15, the energy is in the range of 30 [keV] -50 [keV] It is preferably made under.
이후, 제3(b)도에 도시된 바와 같이 상기 포토레지스트패턴(30)에 따라 개방된 영역의 폴리실리콘(23)을 선택적으로 건식한 후, 제3(c)도에 도시된 바와 같이 상기 포토레지스트패턴(30)을 제거함으로써 원하는 폴리실리콘층 패턴(23a)를 완성한다. 이때 아르곤이온이 주입된 영역에 대한 상기 폴리실리콘층(23)의 건식각은, 공정가스가 CF4+ 8O2로 이루어지거나 CF4+ O2+ SF6로 이루어지는 것이 바람직하다.Thereafter, as shown in FIG. 3 (b), the polysilicon 23 in the open area is selectively dried according to the photoresist pattern 30, and then, as shown in FIG. The desired polysilicon layer pattern 23a is completed by removing the photoresist pattern 30. The argon ions are dry etching of the polysilicon layer 23 to the injection zone, it is preferable that the process gas is made or a CF 4 + 8O 2 consisting of CF 4 + O 2 + SF 6 .
상술한 바와 같은 본 발명은 아르곤이온의 주입량에 따라 식각 프로파일을 조절할 수 있는데, 상기에서 설명한 공정가스등의 조건에 따라 식각된 경우에는 프로파일 각도가 대략적으로 55-75°가 된다.According to the present invention as described above, the etching profile can be adjusted according to the amount of argon ion implantation. When the etching profile is etched according to the above-described process gas, the profile angle becomes approximately 55-75 °.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960061764A KR100242990B1 (en) | 1996-12-05 | 1996-12-05 | Polysilicon etching method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960061764A KR100242990B1 (en) | 1996-12-05 | 1996-12-05 | Polysilicon etching method |
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| KR100242990B1 true KR100242990B1 (en) | 2000-02-01 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05304119A (en) * | 1991-04-22 | 1993-11-16 | Nec Corp | Etching method for polysilicon film |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05304119A (en) * | 1991-04-22 | 1993-11-16 | Nec Corp | Etching method for polysilicon film |
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