KR100404220B1 - Method for manufacturing semiconductor device using tilt etching process - Google Patents
Method for manufacturing semiconductor device using tilt etching process Download PDFInfo
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- KR100404220B1 KR100404220B1 KR1019960007939A KR19960007939A KR100404220B1 KR 100404220 B1 KR100404220 B1 KR 100404220B1 KR 1019960007939 A KR1019960007939 A KR 1019960007939A KR 19960007939 A KR19960007939 A KR 19960007939A KR 100404220 B1 KR100404220 B1 KR 100404220B1
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- 238000005530 etching Methods 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims abstract description 3
- 239000012535 impurity Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 3
- 238000003754 machining Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히, 패턴을 경사지게 식각할 수 있는 경사 식각을 이용한 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using gradient etching, which can etch a pattern obliquely.
종래의 패턴 식각 기술은 건식 식각의 경우 기판에 수직한 패턴을 형성하는 것이 일반적이며, 접속 구멍(contact hole)을 경사지게 식각하는 방법으로서, 감광막 마스크의 윗 부분을 마모시키거나 마스크 패턴의 측벽에 폴리머(polymer)를 형성함으로써 경사지게 가공한다.Conventional pattern etching technique generally forms a pattern perpendicular to the substrate in the case of dry etching, and is a method of obliquely etching a contact hole. It is processed diagonally by forming a polymer.
일반적으로 건식 식각의 경우 패턴을 기판에 대하여 일정한 경사를 갖도록 가공하는 것이 어려우며 접속 구멍 등을 경사지게 식각하는 경우에 있어서도 감광막의 부식(erosion)이나 폴리머(polymer)의 형성량을 조절하기가 어려우므로 정확한 각도의 설정 및 가공이 어렵다.In general, in the case of dry etching, it is difficult to process the pattern to have a constant inclination with respect to the substrate, and even in the case of etching the connection hole or the like at an angle, it is difficult to control the erosion of the photosensitive film or the amount of polymer formation. Setting and machining of angles is difficult.
이에 본 발명은 상기한 종래의 문제점을 해결하기 위하여 제안된 것으로서, 패턴을 기판에 대하여 임의의 각도로 경사지게 가공할 수 있는 경사 식각 방법을 제공하는데 있다.Accordingly, the present invention has been proposed to solve the above-mentioned conventional problems, and to provide an inclined etching method capable of processing a pattern at an angle with respect to a substrate.
상기한 목적을 달성하기 위한 본 발명에 따른 경사 식각을 이용한 반도체 소자의 제조 방법은 반도체 기판상에 게이트 절연막, 폴리실리콘층을 차례로 형성하는 단계;상기 폴리실리콘층, 게이트 절연막을 선택적으로 식각하여 게이트 전극을 형성하는 단계;상기 게이트 전극을 마스크로 이온 주입 공정을 진행하여 반도체 기판의 표면내에 소오스/드레인 영역을 형성하는 단계;에칭 가스의 흐름에 대하여 상기 반도체 기판을 소정의 각도로 경사지게 조절하여 식각을 실시하여 게이트 전극의 양측면을 네가티브 슬로우프를 갖도록 패터닝하는 단계;상기 게이트 전극의 경사 식각되어진 부분의 기판 표면내에 불순물 이온을 주입하여 LDD 영역을 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device using gradient etching, the method including sequentially forming a gate insulating film and a polysilicon layer on a semiconductor substrate; selectively etching the polysilicon layer and the gate insulating film to form a gate Forming a source / drain region in the surface of the semiconductor substrate by performing an ion implantation process using the gate electrode as a mask; etching by adjusting the semiconductor substrate to be inclined at a predetermined angle with respect to the flow of etching gas And patterning both sides of the gate electrode to have a negative slow loop; implanting impurity ions into the substrate surface of the obliquely etched portion of the gate electrode to form an LDD region.
상기 식각을 실시하는 단계는 에칭 가스의 흐름의 방향성을 기판에 대하여 소정의 각도로 조절할 수도 있다.In performing the etching, the direction of the flow of the etching gas may be adjusted at a predetermined angle with respect to the substrate.
이하 첨부한 도면을 참조하여 본 발명을 더욱 상세하게 설명하면 다음과 같다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
제 1 도는 본 발명에 의한 경사 식각 방법을 개략적으로 도시한 단면도이다.1 is a cross-sectional view schematically showing a gradient etching method according to the present invention.
제 1 도에 도시된 바와 같이, 기준면(A)에 대해 수직으로 식각하는 식각방향에 대하여 실리콘기판을 기준면(A)과 θ의 기울기를 주어 설치하면 원하는 목표물(T)은 실리콘 기판에 대하여 90° ∼ θ의 각도로 패턴을 형성할 수 있다.As shown in FIG. 1, when the silicon substrate is provided with the inclination of the reference plane A and θ with respect to the etching direction perpendicular to the reference plane A, the desired target T is 90 ° with respect to the silicon substrate. The pattern can be formed at an angle of θ.
제 2 도(a) 내지 (f)는 본 발명에 따른 경사 식각 방법을 적용한 제 1 실시예를 나타낸 공정 단면도이고, 제 3 도(a) 내지 (f)는 본 발명에 따른 경사 식각방법을 적용한 제 2 실시예를 나타낸 공정 단면도이다.2 (a) to (f) is a cross-sectional view showing a first embodiment to which the gradient etching method according to the present invention is applied, and FIGS. 3 (a) to (f) illustrate the gradient etching method according to the present invention. It is process sectional drawing which showed 2nd Example.
제 2 도(a)내지 (f)는 본 발명에 따른 경사 식각 방법을 적용한 LDD 제조방법을 나타낸 공정 단면도이다.2 (a) to 2 (f) are cross-sectional views illustrating an LDD manufacturing method to which a gradient etching method according to the present invention is applied.
우선, 제 2 도(a)에 도시된 바와 같이 P형 실리콘 기판(10)을 마련하고 상기 실리콘 기판상에 게이트 절연막(11)과 폴리실리콘막(12)을 형성한다.First, as shown in FIG. 2A, a P-type silicon substrate 10 is provided, and a gate insulating film 11 and a polysilicon film 12 are formed on the silicon substrate.
이어서, 제2도(b)와 같이 상기 폴리실리콘막(12) 전면에 포토레지스트를 도포하고 게이트 패턴을 형성한 후, 상기 폴리실리콘막(12)을 건식 식각을 실시하여 게이트 전극(12a)을 형성한다.Subsequently, as shown in FIG. 2B, after the photoresist is applied to the entire surface of the polysilicon film 12 to form a gate pattern, the polysilicon film 12 is dry-etched to form the gate electrode 12a. Form.
그 다음, 제 2 도(c)에 나타낸 것과 같이, 상기 실리콘 기판상에 P 또는 As 이온등의 고농도 이온 주입을 실시하여 소오스와 드레인(13)을 형성한다.Then, as shown in FIG. 2 (c), a high concentration of ions such as P or As ions are implanted on the silicon substrate to form a source and a drain 13.
제 2 도 (d)와 같이 경사진 게이트 전극 패턴(12b)을 형성하기 위하여 에칭가스의 흐름에 대하여 상기 실리콘 기판(10)을 소정의 각도로 조절하여 경사지게가공될 수 있도록 제 1 차 식각을 실시한다.In order to form the inclined gate electrode pattern 12b as shown in FIG. 2 (d), the first etching is performed so that the silicon substrate 10 may be processed to be inclined with respect to the flow of the etching gas at a predetermined angle. do.
상기 1 차 식각 단계는 상기 기판에 대하여 에칭 가스의 흐름 방향을 소정의 각도로 경사지게 조절하여 진행할 수도 있다.The first etching step may be performed by adjusting the flow direction of the etching gas inclined at a predetermined angle with respect to the substrate.
이어서, 제 2 도(e)에서와 같이 상기 게이트 전극(12a)에 대하여 제 2 차 식각하는 단계를 도시한 것으로서, 상기 제 2 도(d)의 식각 방향과는 반대 방향으로 실시한다.Subsequently, as shown in FIG. 2E, the second etching process is performed on the gate electrode 12a, and the etching process is performed in a direction opposite to the etching direction of the second diagram d.
구체적으로 상기 식각 단계는 상기 제 2 도(d)의 식각 방법과 동일하고 식각 방향은 반대 방향으로 실시하여 네가티브 슬로프(negative slope)의 형태가 되도록 실시한다.Specifically, the etching step is the same as the etching method of the second (d) and the etching direction is carried out in the opposite direction to be carried out in the form of a negative slope (negative slope).
제 2 도(f)에 도시된 바와 같이, P 또는 As 이온등을 상기 실리콘 기판에 주입하여 LDD(Lightly Doped Drain) 영역을 설정한다.As shown in FIG. 2 (f), P or As ions are implanted into the silicon substrate to set a lightly doped drain (LDD) region.
상기 제 1 실시예에 따르면, 임의의 각도로 경사지게 가공함으로써, 정확한 각도의 설정 및 가공이 용이하다.According to the first embodiment, by machining inclined at an arbitrary angle, setting and processing of an accurate angle are easy.
제 3 도(a)내지 (e)는 본 발명의 제 2 실시예로서, 개선된 리프트 오프(lift-off) 제조 방법을 나타낸 공정 단면도이다.3 (a) to 3 (e) are process sectional views showing an improved lift-off manufacturing method as a second embodiment of the present invention.
먼저, 제 3 도(a)와 같이, 실리콘 기판(20)을 마련하고 상기 실리콘 기판(20)상에 절연막(21)을 형성한다.First, as shown in FIG. 3A, a silicon substrate 20 is provided and an insulating film 21 is formed on the silicon substrate 20.
이어서, 제 3 도(b)에 나타난 바와 같이, 상기 절연막(21)을 사진/식각 공정으로 소정의 영역을 패터닝한다. 이때, 식각 공정은 일반적인 건식 식각법에 의하여 실시한다.Subsequently, as shown in FIG. 3B, a predetermined region is patterned on the insulating film 21 by a photo / etch process. At this time, the etching process is performed by a general dry etching method.
그 다음, 제 3 도(c)와 같이, 상기 절연막(21)에 대하여 경사 식각(tilt etch)을 실시하여 경사진 트렌치를 형성한다.Next, as illustrated in FIG. 3C, the inclined trench is formed by tilting the insulating layer 21 to form an inclined trench.
상기 식각 단계는 에칭 가스의 흐름에 대하여 상기 기판(20)을 소정의 각도로 조절하여 경사지게 가공될 수 있도록 실시한다.The etching step is performed so that the substrate 20 can be processed to be inclined by adjusting a predetermined angle with respect to the flow of the etching gas.
또한, 상기 식각 단계는 에칭 가스의 흐름의 방향성을 상기 기판(20)에 대하여 소정의 각도로 조절하여 경사지게 가공할 수도 있다.In addition, the etching step may be processed to be inclined by adjusting the direction of the flow of the etching gas to a predetermined angle with respect to the substrate 20.
이어서, 제 3 도(d)에 도시된 바와 같이, 상기 절연막(21)에 대하여 제 2 차 경사 식각을 실시한다. 이때, 상기 제 3 도(c)의 식각 방향과는 반대 방향으로 실시한다.Subsequently, as shown in FIG. 3D, the second inclined etching is performed on the insulating layer 21. In this case, the etching is performed in a direction opposite to the etching direction of FIG.
구체적으로 상기 식각 단계는 상기 제 3 도(c)의 식각 방법과 동일하고 식각 방향은 반대 방향으로 실시하여 네가티브 슬로프(negative slope)의 형태가 되도록 실시한다.Specifically, the etching step is the same as the etching method of the third (c) and the etching direction is carried out in the opposite direction to be carried out in the form of a negative slope (negative slope).
결과적으로 상기 절연막(21)은 네가티브 슬로프의 트렌치로서 가공된다.As a result, the insulating film 21 is processed as a trench of a negative slope.
이어서, 제 3 도(e)에 나타난 바와 같이, 기존의 스퍼터링(sputtering) 등의 방법에 의하여 금속층을 형성한다.Subsequently, as shown in FIG. 3E, the metal layer is formed by a conventional method such as sputtering.
이때 트렌치가 네가티브 슬로프를 가지므로 트렌치의 내부와 외부의 패턴막이 단절되기 쉬운 형태로 형성된다.At this time, since the trench has a negative slope, the inner and outer pattern layers of the trench are easily formed to be disconnected.
마지막으로, 제 3 도(f)에 도시된 바와 같이, 절연막(23)을 제거하여 원하는 금속층을 형성한다.Finally, as shown in FIG. 3 (f), the insulating film 23 is removed to form a desired metal layer.
이상 상술한 본 발명에 의하면 임의의 패턴을 반도체 기판에 대하여 정확하게 경사 가공할 수 있고, 경사 식각을 중복 실시하면 네가티브 슬로프의 패턴을 형성할 수 있다.According to the present invention described above, any pattern can be accurately inclined with respect to the semiconductor substrate, and the pattern of the negative slope can be formed by performing oblique etching repeatedly.
본 발명이 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당 분야의 통상의 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.
제 1 도는 본 발명에 의한 경사 식각 방법을 개략적으로 도시한 단면도1 is a cross-sectional view schematically showing a gradient etching method according to the present invention
제 2 도(a)~(f)는 본 발명의 제 1 실시예에 따른 반도체 소자 제조방법을 나타낸 공정 단면도2 (a) to 2 (f) are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
제 3 도(a)∼(f)는 본 발명의 제 2 실시예에 따른 반도체 소자 제조방법을 나타낸 공정 단면도3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
10,20 : 반도체 기판 11,21,21a,21b : 제 1 물질층10,20: semiconductor substrate 11,21,21a, 21b: first material layer
12,12a,12b : 제 2 물질층 13 : 제 1 도전형 제 1 불순물층12, 12a, 12b: second material layer 13: first conductivity type first impurity layer
14 : 제 1 도전형 제 2 불순물층14: first conductivity type second impurity layer
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| KR1019960007939A KR100404220B1 (en) | 1996-03-22 | 1996-03-22 | Method for manufacturing semiconductor device using tilt etching process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960007939A KR100404220B1 (en) | 1996-03-22 | 1996-03-22 | Method for manufacturing semiconductor device using tilt etching process |
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| Publication Number | Publication Date |
|---|---|
| KR970067686A KR970067686A (en) | 1997-10-13 |
| KR100404220B1 true KR100404220B1 (en) | 2004-01-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960007939A Expired - Fee Related KR100404220B1 (en) | 1996-03-22 | 1996-03-22 | Method for manufacturing semiconductor device using tilt etching process |
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| Country | Link |
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| KR (1) | KR100404220B1 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56126919A (en) * | 1980-03-11 | 1981-10-05 | Semiconductor Res Found | Three-dimensional semiconductor device |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56126919A (en) * | 1980-03-11 | 1981-10-05 | Semiconductor Res Found | Three-dimensional semiconductor device |
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| KR970067686A (en) | 1997-10-13 |
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