KR20020056147A - Method of forming a dummy pattern in semiconductor device - Google Patents

Method of forming a dummy pattern in semiconductor device Download PDF

Info

Publication number
KR20020056147A
KR20020056147A KR1020000085456A KR20000085456A KR20020056147A KR 20020056147 A KR20020056147 A KR 20020056147A KR 1020000085456 A KR1020000085456 A KR 1020000085456A KR 20000085456 A KR20000085456 A KR 20000085456A KR 20020056147 A KR20020056147 A KR 20020056147A
Authority
KR
South Korea
Prior art keywords
dummy pattern
density
metal
pattern
forming
Prior art date
Application number
KR1020000085456A
Other languages
Korean (ko)
Inventor
윤일영
Original Assignee
박종섭
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박종섭, 주식회사 하이닉스반도체 filed Critical 박종섭
Priority to KR1020000085456A priority Critical patent/KR20020056147A/en
Publication of KR20020056147A publication Critical patent/KR20020056147A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating a dummy pattern of a semiconductor device is provided to form a semiconductor device having uniform density of metal, by selectively forming a real dummy pattern according to the density of metal formed on a semiconductor substrate. CONSTITUTION: The dummy pattern is selectively formed according to the density of a metal line formed on the semiconductor substrate(11), wherein the overall density of the meal line and the dummy pattern is uniformly maintained on the entire surface of the semiconductor substrate. The density of the dummy pattern is determined by the interval between the dummy pattern and the metal line.

Description

반도체 소자의 더미패턴 형성방법{Method of forming a dummy pattern in semiconductor device}Method of forming a dummy pattern in semiconductor device

본 발명은 반도체 소자의 더미패턴 형성방법에 관한 것으로서, 특히 반도체 기판 상부에 형성된 메탈의 밀도에 따라 선택적으로 리얼 더미패턴을 형성함으로써, 메탈의 밀도가 작은 지역은 리얼 더미패턴을 많이 형성하고, 메탈의 밀도가 큰 지역은 리얼 더미패턴을 적게 형성하여 전체적으로 밀도가 동일한 반도체 소자를 형성할 수 있는 반도체 소자의 더미패턴 형성방법에 관한 것이다.The present invention relates to a method of forming a dummy pattern of a semiconductor device, and in particular, by forming a real dummy pattern selectively according to the density of a metal formed on the semiconductor substrate, the area of the metal having a low density forms a lot of real dummy patterns, and the metal The high density region of the present invention relates to a method of forming a dummy pattern of a semiconductor device capable of forming a small number of real dummy patterns to form a semiconductor device having the same overall density.

통상, 소정의 구조가 형성된 반도체 기판 어레이는 소정 부위에 따라 그 높이가 다르게 형성된다. 즉, 메탈라인이 형성된 부위와 메탈라인이 형성되지 않은 산화막층 사이에는 단차가 발생한다. 이 단차에 의해 CMP공정시 반도체 기판 어레이의 소정 부위에 단차가 발생하여 유니포미티(uniformity)한 어레이를 형성하는데 많은 문제가 발생한다. 이런 문제를 해결하기 위해 메탈라인이 형성되지 않은 부위에 리얼 더미패턴(real dummy pattern)을 형성하여 이러한 단차를 줄이기 위한 기술 개발이 활발히 진행중에 있다.In general, a semiconductor substrate array having a predetermined structure has a different height depending on a predetermined portion. That is, a step occurs between the portion where the metal line is formed and the oxide layer on which the metal line is not formed. Due to this step, a step occurs in a predetermined portion of the semiconductor substrate array during the CMP process, and thus, many problems occur in forming a uniform array. In order to solve this problem, the development of a technology to reduce the step by forming a real dummy pattern (real dummy pattern) on the portion where the metal line is not active is actively in progress.

이와 같이, 소정의 구조가 형성된 반도체 기판 상부에 리얼 더미패턴을 형성하기 위한 마스크패턴은 소정의 틀내에 어레이(array)형태로 더미패턴을 나열한 후, 제너레이션 룰(generation rule)에 의해 액티브패턴(active pattern) 또는 메탈패턴(metal pattern)으로부터 일정한 거리에 있는 더미패턴을 제거시키는 방법으로 형성한다.As described above, a mask pattern for forming a real dummy pattern on a semiconductor substrate having a predetermined structure is arranged in an array form within a predetermined frame, and then an active pattern is generated by a generation rule. It is formed by removing the dummy pattern at a certain distance from the pattern or a metal pattern (metal pattern).

즉, 도 1에 도시된 바와 같이, 우선 소정의 구조가 형성된 반도체 기판 상부에 형성하고자 하는 액티브(또는 메탈)를 패터닝하기 위한 액티브패턴(또는 메탈패턴)(2)이 소정의 마스크패턴 틀(1)내에 형성된다.That is, as shown in FIG. 1, first, an active pattern (or metal pattern) 2 for patterning an active (or metal) to be formed on a semiconductor substrate having a predetermined structure is provided with a predetermined mask pattern frame 1. Is formed in the

이어서, 마스크패턴 틀(1)내에 어레이 형태로 더미패턴(3)을 나열한후, 제너레이션 룰에 의해 액티브패턴(또는 메탈패턴)(2)으로부터 일정한 거리에 있는 더미패턴을 제거시켜 마스크 패턴을 형성한다.Subsequently, the dummy patterns 3 are arranged in an array form in the mask pattern frame 1, and then a dummy pattern at a predetermined distance from the active pattern (or metal pattern) 2 is removed by a generation rule to form a mask pattern. .

이런, 마스크 패턴을 이용한 소정의 식각공정에 의해 형성된 리얼 더미패턴을 어레이중 일정한 메탈 밀도를 갖는 부위에 삽입시킴으로써, 높은 메탈 밀도를 갖는 지역은 밀도가 조금 증가하고, 낮은 메탈 밀도를 갖는 지역은 밀도가 많이 증가하여 전체적인 메탈 밀도 편차를 감소시키게 된다.By inserting a real dummy pattern formed by a predetermined etching process using a mask pattern into a portion having a constant metal density in the array, the region having a high metal density slightly increases in density and the region having a low metal density has a density. Increases significantly to reduce the overall metal density variation.

그러나, 이와 같은 방법은 전체적인 메탈 밀도의 편차를 줄이는데 한계가 있다.However, this method is limited in reducing the variation of the overall metal density.

따라서, 본 발명의 목적은 소정의 구조가 형성된 반도체 기판 상부에 전체적인 더미 패턴의 밀도 편차를 감소시킬 수 있는 마스크패턴 제조 방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a mask pattern manufacturing method capable of reducing the density variation of an entire dummy pattern on a semiconductor substrate on which a predetermined structure is formed.

본 발명의 또 다른 목적은 반도체 기판 상부에 형성된 리얼 메탈패턴의 밀도에 따라 선택적으로 리얼 더미패턴을 형성함으로써, 리얼 메탈패턴의 밀도가 작은지역은 리얼 더미패턴을 많이 형성하고, 리얼 메탈패턴의 밀도가 큰 지역은 리얼 더미패턴을 적게 형성하여 전체적으로 밀도가 동일한 반도체 소자를 형성할 수 있는 반도체 소자의 더미패턴 형성방법을 제공함에 있다.Another object of the present invention is to selectively form a real dummy pattern according to the density of the real metal pattern formed on the semiconductor substrate, where a small density of the real metal pattern forms a lot of real dummy pattern, the density of the real metal pattern The larger area provides a method of forming a dummy pattern of a semiconductor device capable of forming fewer real dummy patterns to form a semiconductor device having the same overall density.

도 1은 종래 기술에 따른 반도체 소자의 더미패턴을 형성하기 위한 마스크패턴 형성방법을 설명하기 위해 도시한 마스크패턴의 평면도.1 is a plan view of a mask pattern shown for explaining a mask pattern forming method for forming a dummy pattern of a semiconductor device according to the prior art.

도 2는 본 발명의 일 실시예에 따른 반도체 소자의 더미패턴 형성방법을 설명하기 위해 도시한 반도체 소자의 평면도.FIG. 2 is a plan view of a semiconductor device for explaining a method of forming a dummy pattern of a semiconductor device according to an embodiment of the present disclosure; FIG.

도 3은 본 발명의 반도체 소자의 더미패턴 형성방법을 적용한 예를 도시한 어레이 각 부위의 메탈밀도를 도시한 특성표.3 is a characteristic table showing metal densities of respective portions of an array showing an example of applying a method of forming a dummy pattern of a semiconductor device of the present invention.

도 4는 본 발명의 반도체 소자의 더미패턴 형성방법을 적용한 예를 도시한 반도체 소자의 평면도.4 is a plan view of a semiconductor device, showing an example in which the method for forming a dummy pattern of the semiconductor device of the present invention is applied.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1 : 마스크패턴 틀 2,13 : 메탈패턴1: mask pattern frame 2,13: metal pattern

3 : 더미패턴 11 : 반도체 기판3: dummy pattern 11: semiconductor substrate

12 : 리얼 더미패턴12: Real dummy pattern

본 발명은 반도체 기판 상부에 형성된 메탈라인의 밀도에 따라 선택적으로 더미패턴을 형성하여 상기 반도체 기판 상부의 모든 부위에서 상기 메탈라인과 더미패턴을 포함한 전체 밀도가 동일하게 유지되도록 상기 더미패턴을 형성하는 단계를 포함한다.According to the present invention, the dummy pattern is selectively formed according to the density of the metal line formed on the semiconductor substrate, thereby forming the dummy pattern such that the overall density including the metal line and the dummy pattern is kept the same in all portions of the semiconductor substrate. Steps.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2는 본 발명의 일 실시예에 따른 반도체 소자의 더미패턴 형성방법을 설명하기 위해 도시한 반도체 소자의 더미패턴의 평면도이다. 단지, 더미패턴과 메탈패턴은 마스크패턴에 형성되는 패턴을 의미하고, 리얼 더미패턴과 메탈은 실제 반도체 기판 상부에 형성되는 패턴을 의미한다.2 is a plan view illustrating a dummy pattern of a semiconductor device in order to explain a method of forming a dummy pattern of a semiconductor device according to an embodiment of the present invention. However, the dummy pattern and the metal pattern mean a pattern formed on the mask pattern, and the real dummy pattern and the metal mean a pattern formed on the actual semiconductor substrate.

도 2를 참조하면, 우선 소정의 구조가 형성된 반도체 기판(11) 상부의 메탈(13) 밀도에 따라 밀도가 다르게 리얼 더미패턴(12)을 형성하기 위한 더미패턴과, 리얼 더미패턴(12) 사이에 메탈(13)을 형성하기 위한 메탈패턴이 형성된 마스크패턴이 마련된다.Referring to FIG. 2, first, a dummy pattern for forming a real dummy pattern 12 having a different structure according to the density of the metal 13 on the upper portion of the semiconductor substrate 11 on which a predetermined structure is formed and between the real dummy pattern 12 and the dummy pattern 12. A mask pattern on which a metal pattern for forming the metal 13 is formed is provided.

예를 들면, 도 3에 도시된 바와 같이, 마스크패턴은 메탈패턴 밀도가 0%인 어레이지역에 55%의 더미패턴을 삽입시켜 그 부위 밀도를 55%로 형성하고, 메탈패턴 밀도가 55%와 60% 어레이지역에는 더미패턴을 삽입하지 않고 밀도를 55%와 60%로 유지한다. 또한, 메탈패턴 밀도가 20%, 30% 및 45%인 어레이지역에는 55%의 더미패턴을 삽입시켜 그 부위 밀도를 55%로 형성함과 아울러 메탈패턴과의 거리를 달리하여 더미패턴을 삽입하여 형성한다.For example, as shown in FIG. 3, the mask pattern inserts 55% of the dummy pattern into the array region where the metal pattern density is 0% to form the site density of 55%, and the metal pattern density is 55%. In the 60% array area, the density is maintained at 55% and 60% without inserting a dummy pattern. In addition, by inserting a dummy pattern of 55% in the array area where the metal pattern density is 20%, 30% and 45%, the area density is 55% and the dummy pattern is inserted by varying the distance from the metal pattern. Form.

이와 같이, 형성된 마스크패턴을 마스크로 이용한 소정의 식각공정에 의해 반도체 기판 상부에 리얼 더미패턴(12)이 형성된다.As described above, the real dummy pattern 12 is formed on the semiconductor substrate by a predetermined etching process using the formed mask pattern as a mask.

즉, 도 4에 도시된 바와 같이, 소정의 반도체 기판 상부에 10%이하인 메탈(13)이 형성된 지역에는 약 50%정도의 밀도로 리얼 더미패턴(12)이 형성되어 그 지역의 전체 밀도를 약 55%로 유지하고, 40%정도의 밀도로 메탈(13)이 형성된 지역에는 약 20%정도의 밀도로 리얼 더미패턴(12)이 형성되어 그 지역의 전체 밀도를 약 55%로 유지하여 반도체 기판(11) 상부의 전체 밀도가 모두 동일하게 유지된다.That is, as shown in FIG. 4, the real dummy pattern 12 is formed at a density of about 50% in a region where the metal 13, which is 10% or less, is formed on a predetermined semiconductor substrate, thereby reducing the overall density of the region. In the area where the metal 13 is formed at a density of about 40% and the metal 13 is maintained at 55%, the real dummy pattern 12 is formed at a density of about 20% to maintain the total density of the area at about 55%. (11) The overall density at the top remains the same.

전술한 바와 같이, 본 발명은 반도체 기판 상부에 형성된 메탈의 밀도에 따라 선택적으로 리얼 더미패턴을 형성한다. 즉, 메탈의 밀도가 작은 지역은 리얼 더미패턴을 많이 형성하고, 메탈의 밀도가 큰 지역은 리얼 더미패턴을 적게 형성하여 전체적으로 밀도가 동일하도록 반도체 소자를 형성하게 된다.As described above, the present invention selectively forms the real dummy pattern according to the density of the metal formed on the semiconductor substrate. That is, the region where the density of the metal is small forms a lot of real dummy patterns, and the region where the density of the metal is high forms fewer real dummy patterns, thereby forming semiconductor devices to have the same overall density.

상술한 바와 같이, 본 발명은 반도체 기판 상부에 형성된 메탈의 밀도에 따라 선택적으로 리얼 더미패턴을 형성함으로써, 메탈의 밀도가 작은 지역은 리얼 더미패턴을 많이 형성하고, 메탈의 밀도가 큰 지역은 리얼 더미패턴을 적게 형성하여 전체적으로 밀도가 동일한 반도체 소자를 형성할 수 있다.As described above, the present invention selectively forms a real dummy pattern according to the density of the metal formed on the semiconductor substrate, so that the area of the metal having a low density forms a lot of the real dummy pattern, and the area of the metal having a high density of the real By forming a few dummy patterns, a semiconductor device having the same density as a whole can be formed.

따라서, 소정의 CMP공정시 발생하는 소정의 부위간의 단차를 줄일 수있어 유니포미티한 반도체 소자를 제조할 수 있다.Therefore, it is possible to reduce the step difference between the predetermined portions generated during the predetermined CMP process, thereby manufacturing a uniform semiconductor device.

Claims (3)

반도체 기판 상부에 형성된 메탈라인의 밀도에 따라 선택적으로 더미패턴을 형성하여 상기 반도체 기판 상부의 모든 부위에서 상기 메탈라인과 더미패턴을 포함한 전체 밀도가 동일하게 유지되도록 상기 더미패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 더미패턴 형성방법.Selectively forming a dummy pattern according to the density of the metal line formed on the semiconductor substrate to form the dummy pattern such that the overall density including the metal line and the dummy pattern is kept the same at all portions of the semiconductor substrate. A dummy pattern forming method of a semiconductor device, characterized in that. 제 1 항에 있어서,The method of claim 1, 상기 더미패턴은 소정의 마스크를 이용한 증착공정에 의해 상기 메탈라인의 밀도가 작은 지역에는 많이 형성되고, 상기 메탈라인의 밀도가 큰 지역에는 작게 형성되는 것을 특징으로 하는 반도체 소자의 더미패턴 형성방법.The dummy pattern is formed in a region where the density of the metal line is small by a deposition process using a predetermined mask, and the dummy pattern is formed in a small region where the density of the metal line is large. 제 1 항에 있어서,The method of claim 1, 상기 더미패턴의 밀도는 상기 메탈라인과의 거리에 의해 결정되어지는 것을 특징으로 하는 반도체 소자의 더미패턴 형성방법.The density of the dummy pattern is determined by the distance from the metal line.
KR1020000085456A 2000-12-29 2000-12-29 Method of forming a dummy pattern in semiconductor device KR20020056147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020000085456A KR20020056147A (en) 2000-12-29 2000-12-29 Method of forming a dummy pattern in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020000085456A KR20020056147A (en) 2000-12-29 2000-12-29 Method of forming a dummy pattern in semiconductor device

Publications (1)

Publication Number Publication Date
KR20020056147A true KR20020056147A (en) 2002-07-10

Family

ID=27688653

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000085456A KR20020056147A (en) 2000-12-29 2000-12-29 Method of forming a dummy pattern in semiconductor device

Country Status (1)

Country Link
KR (1) KR20020056147A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100837567B1 (en) * 2007-05-10 2008-06-11 동부일렉트로닉스 주식회사 A layout method for mask
KR100849359B1 (en) * 2007-05-02 2008-07-29 동부일렉트로닉스 주식회사 A layout method for mask
KR100862851B1 (en) * 2006-11-16 2008-10-09 동부일렉트로닉스 주식회사 The inserting Method of dummy pattern

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5618757A (en) * 1996-01-30 1997-04-08 Vlsi Technology, Inc. Method for improving the manufacturability of the spin-on glass etchback process
US5639697A (en) * 1996-01-30 1997-06-17 Vlsi Technology, Inc. Dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5618757A (en) * 1996-01-30 1997-04-08 Vlsi Technology, Inc. Method for improving the manufacturability of the spin-on glass etchback process
US5639697A (en) * 1996-01-30 1997-06-17 Vlsi Technology, Inc. Dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100862851B1 (en) * 2006-11-16 2008-10-09 동부일렉트로닉스 주식회사 The inserting Method of dummy pattern
KR100849359B1 (en) * 2007-05-02 2008-07-29 동부일렉트로닉스 주식회사 A layout method for mask
KR100837567B1 (en) * 2007-05-10 2008-06-11 동부일렉트로닉스 주식회사 A layout method for mask

Similar Documents

Publication Publication Date Title
JP3734954B2 (en) Method for forming dummy pattern of semiconductor device
CN100429743C (en) Method of making a semiconductor device
US6339251B2 (en) Wafer grooves for reducing semiconductor wafer warping
KR20020056147A (en) Method of forming a dummy pattern in semiconductor device
JP3581628B2 (en) Method for manufacturing semiconductor device
US6340631B1 (en) Method for laying out wide metal lines with embedded contacts/vias
US6150678A (en) Method and pattern for avoiding micro-loading effect in an etching process
JP2000150407A (en) Manufacture of semiconductor device
KR100676606B1 (en) Method for forming dummy pattern for cmp process
JP3923927B2 (en) Manufacturing method of semiconductor device
JPH0620903A (en) Manufacture of semiconductor device
KR20000004534A (en) Method for manufacturing a cell projection mask of semiconductor devices
KR20050059908A (en) A masking blade of a wafer level
KR100370137B1 (en) A array of flat rom cell method for fabricating the same
JPH02189922A (en) Manufacture of semiconductor device
KR20000066421A (en) Method of forming micro patterns for semiconductor devices
KR100370159B1 (en) Method for Fabricating Semiconductor Device
CN116230506A (en) Method for forming semiconductor structure
JPH01246834A (en) Manufacture of semiconductor device
KR20030049025A (en) Formation method of trench in semiconductor device
KR20010037889A (en) Method of design for high integrated MML device
KR20020052739A (en) Method for fabricating fine conducting lines of semiconductor memory device
JPH02174121A (en) Method for improving etching selectivity in semiconductor manufacturing process
TW337039B (en) Process for producing IC capacitor by an oxygen ion implantation technique
KR20040040804A (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
N231 Notification of change of applicant
E902 Notification of reason for refusal
E601 Decision to refuse application