KR20030049025A - Formation method of trench in semiconductor device - Google Patents

Formation method of trench in semiconductor device Download PDF

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Publication number
KR20030049025A
KR20030049025A KR1020010079095A KR20010079095A KR20030049025A KR 20030049025 A KR20030049025 A KR 20030049025A KR 1020010079095 A KR1020010079095 A KR 1020010079095A KR 20010079095 A KR20010079095 A KR 20010079095A KR 20030049025 A KR20030049025 A KR 20030049025A
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trench
semiconductor substrate
ion implantation
trenches
damaged
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KR1020010079095A
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Korean (ko)
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서영훈
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아남반도체 주식회사
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Priority to KR1020010079095A priority Critical patent/KR20030049025A/en
Publication of KR20030049025A publication Critical patent/KR20030049025A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A method for forming a trench of a semiconductor device is provided to be capable of forming trenches having the same depth in a substrate regardless of the widths of the trenches by carrying out an ion implantation before etching the substrate. CONSTITUTION: After sequentially forming an oxide layer(12) and a nitride layer(13) on a semiconductor substrate(11), a photoresist pattern(14) is formed on the resultant structure. The predetermined portions of the semiconductor substrate are exposed by sequentially etching the oxide and nitride layer using an end point detecting apparatus. Damaged regions having the same depth are formed in the semiconductor substrate by carrying out an ion implantation using the photoresist pattern as a mask. At this time, the depths of the damaged regions are controlled by implantation conditions, respectively. Then, the damaged portions are selectively etched for forming trenches(15) having the same depth regardless of the widths of the trenches.

Description

반도체 소자의 트렌치 형성 방법 {Formation method of trench in semiconductor device}Formation method of trench in semiconductor device

본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 반도체 기판에 소자 분리 영역인 트렌치를 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a trench as an isolation region in a semiconductor substrate.

일반적으로 반도체 소자를 제조하기 위해서는 첫 단계로서 반도체 기판을 활성영역 및 필드영역으로 구분하는 격리공정을 수행하고, 그 다음, 격리공정을 통해 활성영역으로 정의된 반도체 기판 상에 각 개별 소자를 제조한다.In general, in order to manufacture a semiconductor device, an isolation process for dividing a semiconductor substrate into an active region and a field region is performed as a first step, and then each individual device is manufactured on a semiconductor substrate defined as an active region through an isolation process. .

최근 주로 사용되는 반도체 소자의 격리공정으로는 트렌치 격리(STI : shallow trench isolation) 공정이 있다. 트렌치 격리공정에서는 반도체 기판 내에 트렌치를 형성하고 트렌치 내부를 절연물질로 매입시킴으로써 필드영역의 크기를 목적한 트렌치의 크기로 제한한다.Recently, a isolation process of a semiconductor device mainly used includes a trench trench (STI) process. In the trench isolation process, a trench is formed in a semiconductor substrate and the inside of the trench is filled with an insulating material to limit the size of the field region to the desired trench size.

트렌치는 반도체 소자가 밀집되는 영역과 상대적으로 덜 밀집되는 영역에서 그 폭에 차이가 있는데, 폭에 상관없이 모든 트렌치가 동일한 깊이로 식각되어 트렌치 깊이의 균일도(uniformity)가 높은 것이 중요하다. 그런데, 반도체 소자가 고집적화되어 갈수록 트렌치 깊이의 균일도 유지는 요구되나 이를 만족시키기가 어려워진다.Trenchs differ in their widths in areas where semiconductor devices are densely populated and areas that are relatively less dense. It is important that all trenches are etched to the same depth, regardless of the width, so that the uniformity of the trench depth is high. However, as semiconductor devices become more integrated, it is required to maintain uniformity of trench depths, but it is difficult to satisfy them.

그러면, 종래 트렌치 형성 방법에 대해 첨부된 도면을 참조하여 설명한다.Next, a conventional trench forming method will be described with reference to the accompanying drawings.

도 1은 종래 방법에 따라 형성된 트렌치를 도시한 단면도이다.1 is a cross-sectional view showing a trench formed according to a conventional method.

먼저, 반도체 기판(1) 상에 산화막(2) 및 질화막(3)을 차례로 형성한 후, 목적하는 트렌치를 제외한 활성영역 상에 감광막 패턴(4)을 형성한다. 이어서, 감광막 패턴(4)을 마스크로 하여 노출된 질화막(3) 및 그 하부의 산화막(2)을 종점검출(endpoint detection : EPD) 장비를 이용하여 식각한 다음, 반도체 기판(1)을 목적하는 깊이까지 식각하여 트렌치(5)를 형성한다.First, the oxide film 2 and the nitride film 3 are sequentially formed on the semiconductor substrate 1, and then the photosensitive film pattern 4 is formed on the active region except for the desired trench. Subsequently, the nitride film 3 exposed below and the oxide film 2 below it using the photosensitive film pattern 4 as a mask are etched using endpoint detection (EPD) equipment, and then the semiconductor substrate 1 Etch to depth to form trench 5.

이 때, 반도체 기판(1)을 식각할 때에는 시간을 변수로 하여 깊이를 조절하며, 실험을 통해 정해진 시간동안 식각하여 목적하는 깊이의 트렌치(5)를 형성한다.At this time, when the semiconductor substrate 1 is etched, the depth is adjusted by using time as a variable, and through the experiment, the depth is etched for a predetermined time to form the trench 5 having a desired depth.

그러나, 상기한 바와 같은 종래 방법에서는 폭이 좁은 트렌치와 넓은 트렌치가 동일한 깊이로 식각되지 않는 문제점이 있었으며, 이러한 현상은 소자가 고집적화되어 갈수록 더욱 심해지며, 이와 같이 트렌치 깊이의 균일도가 낮아지면 누설전류 발생의 원인이 되는 문제점이 있다.However, in the conventional method as described above, there is a problem that the narrow trench and the wide trench are not etched to the same depth, and this phenomenon becomes more severe as the device becomes highly integrated, and thus the uniformity of the trench depth decreases the leakage current. There is a problem that causes occurrence.

본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 폭에 상관없이 트렌치를 동일한 깊이로 식각하여 트렌치 깊이의 균일도를 향상시키는 데 있다.The present invention is to solve the above problems, the object is to improve the uniformity of the trench depth by etching the trench to the same depth, regardless of the width.

도 1은 종래 방법에 따라 형성된 트렌치를 도시한 단면도이다.1 is a cross-sectional view showing a trench formed according to a conventional method.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 트렌치 형성 방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a trench forming method of a semiconductor device according to the present invention.

상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 반도체 기판의 식각 전에, 감광막 패턴을 마스크로 하여 노출된 반도체 기판 내에 이온주입을 수행하여 이온주입에 의해 손상된 영역을 형성한 후, 노출된 반도체 기판을 식각하여 트렌치를 형성하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, before the etching of the semiconductor substrate, after performing ion implantation in the exposed semiconductor substrate using the photosensitive film pattern as a mask to form a region damaged by ion implantation, the exposed semiconductor substrate Etching to form a trench.

이 때, 이온주입에 의해 손상된 영역의 깊이는, 이온주입 조건에 따라 결정되며, 손상되지 않은 영역에 비해 식각율이 빠른 것이 바람직하다.At this time, the depth of the region damaged by ion implantation is determined by the ion implantation conditions, and it is preferable that the etching rate is faster than that of the region not damaged.

또한, 이온주입 조건은, 주입 에너지 및 주입 시간 중의 하나 이상인 것이 바람직하다.Further, the ion implantation conditions are preferably at least one of implantation energy and implantation time.

형성된 트렌치는 폭에 상관없이 동일한 깊이를 가지는 것이 바람직하다.The trenches formed preferably have the same depth regardless of the width.

이하, 본 발명에 따른 반도체 소자의 트렌치 형성 방법에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a trench in a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 트렌치 형성 방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a trench forming method of a semiconductor device according to the present invention.

먼저, 도 2a에 도시된 바와 같이, 반도체 기판(11) 상에 산화막(12) 및 질화막(13)을 차례로 형성한 후, 목적하는 트렌치를 제외한 활성영역 상에 감광막 패턴(14)을 형성한다.First, as shown in FIG. 2A, the oxide film 12 and the nitride film 13 are sequentially formed on the semiconductor substrate 11, and then the photosensitive film pattern 14 is formed on the active region except for the desired trench.

다음, 도 2b에 도시된 바와 같이, 감광막 패턴(14)을 마스크로 하여 노출된 질화막(13) 및 그 하부의 산화막(12)을 종점검출 장비를 이용하여 식각하여, 그 하부의 반도체 기판(11)을 노출시킨다. 이 때, 반도체 기판(11)의 노출된 영역은 트렌치가 형성될 영역에 해당된다.Next, as shown in FIG. 2B, the exposed nitride film 13 and the oxide film 12 below the photosensitive film pattern 14 as a mask are etched using the endpoint detection equipment, and the semiconductor substrate 11 below the semiconductor substrate 11 is etched. ). In this case, the exposed region of the semiconductor substrate 11 corresponds to the region where the trench is to be formed.

다음, 도 2c에 도시된 바와 같이, 감광막 패턴(14)을 마스크로 하여 반도체 기판(11)의 상부 전면에 이온주입을 수행하여, 노출된 반도체 기판(11) 내에 이온주입에 의해 손상된 영역을 형성한다. 이 때, 주입 에너지 또는 주입 시간과 같은 주입 조건을 달리하여 손상된 영역의 깊이를 조절하며, 이로써 목적하는 트렌치의 깊이만큼 손상된 영역이 형성되도록 한다. 또한, 노출된 기판의 폭, 즉 트렌치의 폭에 상관없이 이온주입에 의해 손상된 영역의 깊이는 동일하며, 이온주입에 의해 손상된 영역은 그렇지 않은 영역에 비해 식각율이 빨라지게 된다.Next, as shown in FIG. 2C, ion implantation is performed on the entire upper surface of the semiconductor substrate 11 using the photoresist pattern 14 as a mask to form a region damaged by ion implantation in the exposed semiconductor substrate 11. do. At this time, the depth of the damaged region is adjusted by varying the implantation conditions such as the implantation energy or the implantation time, so that the damaged region is formed by the depth of the desired trench. In addition, regardless of the width of the exposed substrate, that is, the width of the trench, the depths of the regions damaged by the ion implantation are the same, and the regions damaged by the ion implantation have faster etching rates than those of the regions not damaged.

다음, 도 2d에 도시된 바와 같이, 감광막 패턴(14)을 마스크로 하여 반도체 기판(11)을 식각하여 트렌치를 형성한다. 이 때, 기판 식각시, 식각율이 빨라서 선택성(selectivity)이 높은, 이온주입에 의해 손상된 영역이 먼저 식각되므로, 오버에치(overetch)를 충분히 수행하면 손상된 영역만을 식각할 수 있으며, 따라서, 트렌치(15)가 폭에 상관없이 동일한 깊이로 형성된다.Next, as shown in FIG. 2D, the semiconductor substrate 11 is etched using the photoresist pattern 14 as a mask to form a trench. In this case, when the substrate is etched, the region damaged by ion implantation, which has a high etch rate and has high selectivity, is etched first. Therefore, if the overetch is sufficiently performed, only the damaged region can be etched. 15 is formed to the same depth regardless of the width.

이로써, 본 발명에 따른 트렌치 형성공정을 완료한다.This completes the trench forming process according to the present invention.

상술한 바와 같이, 본 발명에서는 기판 식각 전에 이온 주입을 수행하여 이온주입에 의해 손상된 영역을 트렌치가 형성될 영역에 동일한 깊이로 형성시키는데, 이로써, 기판 식각시 손상된 영역이 선택적으로 식각되어 트렌치가 폭에 상관없이 동일한 깊이로 형성되는 효과가 있다.As described above, in the present invention, ion implantation is performed before etching the substrate to form a region damaged by ion implantation at the same depth in the region where the trench is to be formed, whereby the region damaged during the etching of the substrate is selectively etched so that the trench is wide. Regardless, there is an effect formed to the same depth.

이와 같은 트렌치 깊이의 균일도 향상으로 인해, 누설전류 발생의 문제점을 개선하는 효과가 있다.Due to the improved uniformity of the trench depth, there is an effect of improving the problem of leakage current generation.

Claims (4)

반도체 기판 상에 형성된 감광막 패턴을 마스크로 하여 노출된 반도체 기판을 식각하여 트렌치를 형성하는 방법에 있어서,In the method of forming a trench by etching the exposed semiconductor substrate using a photosensitive film pattern formed on the semiconductor substrate as a mask, 상기 식각 전에, 상기 감광막 패턴을 마스크로 하여 상기 노출된 반도체 기판 내에 이온주입을 수행하여 이온주입에 의해 손상된 영역을 형성한 후, 상기 노출된 반도체 기판을 식각하여 트렌치를 형성하는 것을 특징으로 하는 반도체 소자의 트렌치 형성 방법.Before the etching, using the photosensitive film pattern as a mask to perform ion implantation in the exposed semiconductor substrate to form a region damaged by ion implantation, the semiconductor substrate characterized in that the trench is formed by etching the exposed semiconductor substrate Method for forming trenches in the device. 제 1 항에 있어서,The method of claim 1, 상기 이온주입에 의해 손상된 영역의 깊이는, 상기 이온주입 조건에 따라 결정되며, 손상되지 않은 영역에 비해 식각율이 빠른 것을 특징으로 하는 반도체 소자의 트렌치 형성 방법.The depth of a region damaged by the ion implantation is determined according to the ion implantation conditions, and the etching rate is faster than the intact region. 제 2 항에 있어서,The method of claim 2, 상기 이온주입 조건은, 주입 에너지 및 주입 시간 중의 하나 이상인 것을 특징으로 하는 반도체 소자의 트렌치 형성 방법.And ion implantation conditions are at least one of implantation energy and implantation time. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 트렌치는 폭에 상관없이 동일한 깊이를 가지는 것을 특징으로 하는 반도체 소자의 트렌치 형성 방법.And the trenches have the same depth regardless of the width.
KR1020010079095A 2001-12-13 2001-12-13 Formation method of trench in semiconductor device KR20030049025A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331636A (en) * 2017-07-17 2017-11-07 上海华力微电子有限公司 A kind of method of imaging sensor 3D grids silicon hole etching

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331636A (en) * 2017-07-17 2017-11-07 上海华力微电子有限公司 A kind of method of imaging sensor 3D grids silicon hole etching

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