CA1287556C - Procedure for fabricating devices involving dry etching - Google Patents
Procedure for fabricating devices involving dry etchingInfo
- Publication number
- CA1287556C CA1287556C CA000512190A CA512190A CA1287556C CA 1287556 C CA1287556 C CA 1287556C CA 000512190 A CA000512190 A CA 000512190A CA 512190 A CA512190 A CA 512190A CA 1287556 C CA1287556 C CA 1287556C
- Authority
- CA
- Canada
- Prior art keywords
- substrate
- redeposition
- etching
- etch
- resist mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000001312 dry etching Methods 0.000 title abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 55
- 239000000463 material Substances 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 230000008569 process Effects 0.000 claims abstract description 15
- 230000000694 effects Effects 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 238000006243 chemical reaction Methods 0.000 claims abstract description 4
- 230000000670 limiting effect Effects 0.000 claims abstract description 4
- 230000001939 inductive effect Effects 0.000 claims abstract description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 241000894007 species Species 0.000 description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 238000000151 deposition Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- ZWEHNKRNPOVVGH-UHFFFAOYSA-N 2-Butanone Chemical compound CCC(C)=O ZWEHNKRNPOVVGH-UHFFFAOYSA-N 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 3
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- 230000002547 anomalous effect Effects 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 210000003414 extremity Anatomy 0.000 description 3
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- 150000002500 ions Chemical class 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
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- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
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- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- RKJWJAQVTBECFT-UHFFFAOYSA-N 3,3-dichloropropyl prop-2-enoate Chemical compound ClC(Cl)CCOC(=O)C=C RKJWJAQVTBECFT-UHFFFAOYSA-N 0.000 description 1
- WTQZSMDDRMKJRI-UHFFFAOYSA-N 4-diazoniophenolate Chemical compound [O-]C1=CC=C([N+]#N)C=C1 WTQZSMDDRMKJRI-UHFFFAOYSA-N 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 241000950638 Symphysodon discus Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
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- 230000001010 compromised effect Effects 0.000 description 1
- 229920001577 copolymer Polymers 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- HOQADATXFBOEGG-UHFFFAOYSA-N isofenphos Chemical compound CCOP(=S)(NC(C)C)OC1=CC=CC=C1C(=O)OC(C)C HOQADATXFBOEGG-UHFFFAOYSA-N 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001230 polyarylate Polymers 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
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- 229910000077 silane Inorganic materials 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
PROCEDURE FOR FABRICATING DEVICES
INVOLVING DRY ETCHING
Abstract The present invention relates to a process for fabricating a device comprising the steps of forming a resist mask on a substrate, etching the substrate to form a plurality of etch pits defining a plurality of features by inducing reaction of the substrate with energetic species and completing the device. The redeposition of material on the side walls of the etch pit ocours during the etching. The process includes at least one step chosen from the group of steps consisting of, 1) locally compensating for the effect of the redeposition on the conformation of the sidewall, 2) when the redeposition material presents a barrier to isotropic etching in the sukstrate, contacting the etching species with the resist mask so that the angle formed between a) a tangent to the resist mask at the point the resist mask intercepts the substrate and (b) a perpendicular to the substrate at the point is less than arctan (X/Y), where X is the horizontal rate of the redeposition at the point and Y is the etchant rate of the substrate, and (3) limiting, when the redeposited material presents a barrier to isotropic etching in the subatrate, the contact angle between the momentum direction of the etchant species and a tangent to the redeposition material at all points on the resistant redeposition material serving to mask the sidewalls so that the contact angle is less than arctan (X/Z), where X is as defined in step 2), where Z is the etchant rate of the redeposited material in a direction parallel to the etchant species momentum direction.
INVOLVING DRY ETCHING
Abstract The present invention relates to a process for fabricating a device comprising the steps of forming a resist mask on a substrate, etching the substrate to form a plurality of etch pits defining a plurality of features by inducing reaction of the substrate with energetic species and completing the device. The redeposition of material on the side walls of the etch pit ocours during the etching. The process includes at least one step chosen from the group of steps consisting of, 1) locally compensating for the effect of the redeposition on the conformation of the sidewall, 2) when the redeposition material presents a barrier to isotropic etching in the sukstrate, contacting the etching species with the resist mask so that the angle formed between a) a tangent to the resist mask at the point the resist mask intercepts the substrate and (b) a perpendicular to the substrate at the point is less than arctan (X/Y), where X is the horizontal rate of the redeposition at the point and Y is the etchant rate of the substrate, and (3) limiting, when the redeposited material presents a barrier to isotropic etching in the subatrate, the contact angle between the momentum direction of the etchant species and a tangent to the redeposition material at all points on the resistant redeposition material serving to mask the sidewalls so that the contact angle is less than arctan (X/Z), where X is as defined in step 2), where Z is the etchant rate of the redeposited material in a direction parallel to the etchant species momentum direction.
Description
~87~
-- 1 , PROCEDURE FOR FABRICATING DEVICES
INVOLVING DRY ETCHING
.
Backqround of the Invention 1. Field o~ the Invention This invention relates to semiconductor device processing involving dry etching.
The backgxound of the present invention will be discussed in detail hereinbelow.
In accordance with one aspect of the invention there is provided a process for fabricating a device comprising the steps of forming a resist mask on a substrate, etching said substrate to form a plurality of etch pits defining a plurality of features by inducing reaction of said substrate with energetic species, and completing said device, wherein redeposition of material on the sidewalls of said etch pit occurs during said etching characterized in that said process includes at least one step chosen from the group consisting of l) locally compensating for the effect of said redeposition on ~ 20 the conformation of sald sidewall, 2) when said redeposited ;~
- material presents a barrier to isotropic etching in said -~
substrate,~ contacting said etchant species with said resist mask so that the angle formed between a) a tangent to said resist mask at the~point said resist mask intersects the ` 25 substrate and b) a~perpendicular to said substrate at said oint is~less than arctan (XjY),~where x is the horizontal rate of sa~id redeposition~at said point and~v is the etch rate ~ -~
of said substrate, and 3) limiting, when said redeposited `
material presents a barrier to isotropic etching in said substrate,~the contact~angle between~the momentum direction of said etchant~species~and a tangent to said redeposited materiàl~at all~p~oints on~said resistan~ redeposited material serving~to~masX~said sidewalls so that said contact angle is ;less~than~arctan~(X/Z),~ where z is the~etch rate of said resistant~redeposited material in a direction parallel to said etchant~species~momentum direction.
~ " , .: ~ ~ , Brief Description of the Drawinq FIGS. 1-3 illustrate sidewall configura~ions sometimes obtained after etching;
FIGS. 4 and 5 illustrate possible configurations of redeposition;
FIGS. 6 and 7 illustrate the effect of configuration on redeposition; and FIGS. 8-11 illustrate the effect of mask angle.
Semiconductor devices are generally fabricated on a substrate through a series of processing steps including deposition of semiconductor materials, metals, insulators, and the etching of these materials in selected patterns. In one common etching method, a reactive etchant species is generated in a plasma and directed at a high velocity by an electric field towards the material to be etched. Generally during etching, the material being etched is masked in selected regions from this reactive species by a composition such as a polymer (typically denominated a resist) that has been delineated in a desired pattern~ Thus, the pattern of the resist is transferred during the etching process to the underlying etched material. As a result, the device configurations desired in semiconductor, insulator, and/or metal regions are produced.
Accelerated reactive species are advantageously utilized in etching because they typically produce anisotropic etching, i.e., etching where the etch rate at any point along the etch pit wall in the direction of etchant species momentum is at least ten times greater than the etch rate in the direction normal to this velocity vector. Two effects generally contribute to the attainment of anisotropic etching. In one circumstance, a material to be etched, such as silicon, reacts with certain species, e.g., Cl~, only when the species has significantly higher momentum than that associated with room temperature. Thus, when such a species is accelerated essentially perpendicularly to the substrate surface, etching preferentially occurs in this direction rather than the remaining random directions associated with etchant species which are only thermally activated. In a second circumstance, '~
! - ' ~: ', ~8~S~i6 such as in the etching of aluminum by species generated in a Cl2/C2F6 plasma, material which is resis~ant to isotropic etching is produced during the etching process, is redeposited on the sidewalls of the etch void, and promotes anisotropic etching. (See U.S. Patent ~,208,241, issued June 17, 1980, where a recombinant species forms such a resistant material.) That is, the redeposited material acts as an etch mask.
The attainment of anisotropic etching through one or both of these mechanisms is significant because it promotes maintenance of the unetched region dimensions (frequently called linewidth control), facilitates subsequent processing, and allows lines to be closely spaced. For example, when isotropic etching, i.e., a lateral etch rate that is at least one-tenth of the etch rate in the etchant momentum direction, rather than anisotropic etching is achieved, etch profiles, 14, such as those shown in FIG. 1 are produced utilizing a resist, 15. Obviously, the attainment of isotropic rather than anisotropic etching reduces linewidth control, i.e., the percentage between 1) the largest deviation of any feature from the corresponding desired feature, 12, defined by the mask at the substrate surface and 2) one-half the linewidth, 12, defined by the mask. (A feature deviation is thus the distance from any point on an etch sidewall measured perpendicularly to a surface extending from the extremities of the mask region defining this feature in a direction perpendicular to the surface at each point along the mask extremity.) Similarly, linewidth control is also compromised, as shown in FIG. 2 where 15 indicates the resist, if the sidewalls slope in the opposite direction. Configurations such as those shown in FIGS. 1 and 2 are undesirable because they interfere with subsequent processing as well as contributing to loss of linewidth control. For example, if the etched line is itself to be used as a mask, e.g., for an ion implantation mask, any linewidth gain or loss augments the associated inaccuracies in subsequent mask use.
Alternatively, if an insulating layer is to be formed on the etch sidewalls by deposition onto all surfaces followed by an ` anisotropic etch to remove the material from lateral surfaces, .` ' `
`'` "
.
:. , - . : .
- . , " ' ., , :, :` ,.' '' - ; ' ' ' ,:: . .-' ~ ' .~ ; - ' .
s~
then the tapered profile in FIGS. 1 and 2 will compromise the insulating layer on the sidewall during the anisotropic etch.
Although sidewall redeposition during etching has been associated in many circumstances with the maintenance of anisotropic etching, it does present some difficulties. As discussed by Kinsbron, Levinstein, and Willenbrock in U.S.
Patent 4,343,677, issued August 10, 1982, it is desirable to remove these sidewall redeposits because 1) they tend to be dislodged during subsequent processing, 2) they often assume undesirable shapes, and 3) they frequently have undesirable electrical or mechanical properties. Sidewall redeposition also does not always ensure anisotropy. Despite the occurrence of sidewall redeposition and the use of energetic reactive species, anomalous etching patterns such as shown at 16 in FIG. 3 (where 15 is the resist) have been observed.
These anomalies are generally undesirable because they degrade feature mechanical stability and conductivity.
The presence of sidewall redeposits has a significant, previously unrecognized effect beyond that of resistance to - the etchant species. In particular, the greater the amount of sidewall redeposition, the greater the slope of the sidewall after the redeposited mas~ material is removed. The inventors have also found that the amount of this redeposition is critically dependent on the local feature geometry surrounding the sidewall. Thus, in circumstances where linewidth control is critical, such as in circumstances where etch features critically control device parameters, e.g., the gate length in a field effect transistor, local compensation should be made for redeposition onto etch sidewalls. For example, the resist mask should be appropriately adjusted in local regions of excess redeposition, or feature geometry should be adjusted in these regions.
Linewidth control is also affected by other previously unrecognized effects. To protect linewidth and ensure acceptable etch rates, a mask material surface (including the surface of redeposited material that contributes to the attainment of anisotropy) should be carefully adjusted. If the configuration of the redeposited material is controlled, , ~; - .
.. .. . . . . . . . . : . .
- .: , . . :: , . . .
: , , , ;
, . , . . :
1~'7556 - 4a -anomalous etching effects, such as shown in Fig. 3, and anomalously slow etch rates are avoided. The profile o the resist mask also affects the configuration of the sidewall, i.e., the etch pit boundary-after the redeposition is removed.
If the portion o the resist defining the etch pattern presents a surface forming an excessive angle with the momentum direction of the reactive species, linewidth control is unacceptably degraded. All these effects become particularly important when linewidth control of 0.1 ~ or better is desired.
. .
. .
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The inventors have found that important etching properties, such as etching speed and linewidth, depend strongly on the redeposition process. A first prime consideration is the extent of redeposition. The greater ~he rate of redeposition onto the sidewall, the greater the slope of this sidewall. (In this context, the etch pit sidewall is the configuration of the surface of the etch pit when the redeposited material, i.e., the material added to the sidewall during etching, is removed.) If redeposition occurs, sidewall slope (deviation from the etchant species momentum direction) occurs and the extent of this slope directly depends on the magnitude of the redeposition onto the etch sidewall at the bottom of the etch pit. The effect of lS redeposition on etching efficacy is illustrated in FIGS. 4 and 5. If a small amount of redeposition, 23, occurs, then sidewall angles such as shown in FIG. 4 at 20 are obtained. In contrast, if a relatively large amount is redeposited, then configurations such as that shown in FIG. 5 are obtained, where the stippled region, 23, indicates the redeposited material, 20 ~-~
indicates the surface of the sidewall, and 41 is the resist. As shown in FIGS. 4 and 5, as the angle of the side~all increases, linewidth control is lost. Thus, compensation for this linewidth loss should be made.
Generally, this compensation is accomplished by -` 1) adjusting the lithographic process, e.g., utilizing - suitably narrow lines to ~compensate for linewidth ~-broadening and thus to yield the desired linewidth, and/or 2) limiting the extent of redeposition. In the second approachj;the redeposition should be limited so that after etching the angle between 1) the linear ~ :
, . .~ .,;, : ~ :
-: :
least-squares-fit to the sidewall and 2) the direction of the etchant species momentum vector surface at the intersection of the least-squares-fit is sufficiently small to produce the desired linewidth control, e.g., an S angle smaller than 12 degrees for a feature deviation of 0.1 ,um with an etch pit depth of 0.5 ~m.
The amount of redeposition, however, is not uniform across a substrate. A predominant source of redeposition is by-product species from the etched material. The angle of the sidewall, except in anomalous cases to be subsequen~ly discussed, depends, to an excellent approximation, on the ratio between 1) the redeposition flux at the interface between the etch pit bottom and the redeposited material and 2) the etch ra~e of the material being etched in the direction of species momentum. The redeposition flux at the -bottom of the etch pit is directly dependent on the area of the etch pit bottom. The relative geometries and config;urations of the features define this area and thus strongly affect sidewall angle. As a result, redeposition depends strongly on the local geometry, and thus compensation should be tailored to this local variance.
Th~ree~geometry types are commonly involved in the formation~o~f devices. The first case involves ~featùr~ès~having proximate sidewalls, i.e., an etch pit which has a characteristic distance and whose depth is at least~as~large as half of its characteristic distance. ~An etched void has~a~characteristic distance 30 ~if the largest and smallest dimensions of the figure ~formed by the~intersection` of the mask with the ~substràte surface~difer by l~ess than 50 percent. (A
dimension of~a figure i5 the inscribed distance of a line~from~one~point~on the figure across the igure 35~th;rough~the center of mass of the figure.) The second situation~ nvolves a~trench configuration, i~e., an etched~-r~egion deflned~by~the mask 1) is bounded by two ~ ~ :
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substantially parallel lines separated by not more than 7 times the etch pit depth and 2~ these parallel lines are longer than 1.5 times this separati~n. The third case involves an open feature, i.e., the closest etch sidewall is at least greater than 7 etch pit depths away from every other sidewall forming the etch pit. (It should be noted that in one etch pit it is possible to have a poLtion falling within one case, e.g., case 2, and a second portion falling within a second case, e.g., case 3. For example, an etch pit with a dumhbell shape has two case 1 regions and one case 2 region.) In the first and second cases, the sidewall redeposition is significantly less than in the third case because of a smaller ~ource of redeposition flux.
In the third case, the area of the etch pit bottom is the greatest, and the amount of redeposition is correspondingly large. Thus, typically, open features such as 62, shown in the plan view of FIG. 6, are preferably avoided. (In FIGS. 6 and 7, 61 is a resist that defines gates and that defines gate conductors which extend over thick field oxide, 80, and into the transistor regions, 84. Additionally, transistor regions repeating the configuration of regions, 84, have been omitted for clarity~) For example, in one embodiment, non-functional features are formed to convert case (3) situations on a substrate to case (2) ; configurations. In~a second embodiment, this conversion is accomplished by changing one or more functional features,~e.g., conductors are rerouted so they pass within a rela~tively~short distance of the open sidewall (72 and 73~in~F~IG. 7). Thus, a feature is relocated from a~path of least meander, i.e., the shortest distance~consistent with device design between points to be~electr~ically contacted, so that it limits the area of 35; ~;an :etch~ pit bo~ttom. ~The objectional local confi~uration i~s, ~in~this way, transformed from an open configuration ~ to a configuration within case (2). Thus, compensation - : : :~ :
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is accomplished locally in regions where linewidth control is required to maintain device properties.
(Locally, in this context, is compensation in at least one region, but not all regions of a plurality of S regions which are designed to have the same linewidth.) third embodiment involves locally compensating the resist mask. In this embodiment, instead of converting from one case to another, the resist mask in a localized area is modified to compensate for the sidewall variations occurring with different geonetric cases.
For example, in FIG. 6, the resist feature defining gate 61, over region 62, is decreased sufficiently from ; that of regions, 8~, to compensate for the local linewidth broadening occurring in this case 3 region.
This embodiment is generally less desirable since, as previously discussed, the sidewall is tapered.
As previously noted, the angle of the sidewall also depends on the substrate etch rate. Thus, an auxiliary approach to local co~pensation for sidewall angle is the control, irrespective of source, of the reactant species composition in the plasma. For example, silicon trenches are typically etched utilizing a C12 based etchant gas with an organic polymeriSiO2 mask. By the slimination of the polymer mask layer, the amount of~redeposition is reduced, and thus the amount of sidewall~ angle undergoes a concomitant reduction.
Thus,~it is possible to atilize a change in ~ configuration, as previously discus ed, in conjunction i with an appropriate modification of the etching gas chemistry~to~urther reduce the amount of redeposikion.
Anomalou~s~situations, e.g., catastrophic iso~ropi;c;~etching;, linewidth loss, and/or unaccep~ably ~slow etch~;rate, also ocaur. These situ~tion~ are pr;oduced~when material functioning as a mask ~i.e., either 1;)~`~redeposited ma~terial that is acting as a barrier~o lateral etching or 2) the feature-de~ining edge~of~a~re~ist material) during etching is ' ' ' '' . .. '. : ' : ,: ', . ' ~, " : ,. .. , , . . ' ~8~5~
9 _ substantially s~bjected to non-glancing i~pact by the etchant species. (A redeposited material is considered a barrier to etching when the redeposited material does not etch isotropically.) Such undesirable contact depends upon the configuration of the mask surf~ce. To avoid disadvantageous loss of linewidth by violating the angle criterion for the resist mask, at the inception of etching the angle fon~ed between a tangent to the mask at the point it intersects the substrate and a perpendicular to the substrate at this point should be less than arctan (y), where x is the horizontal redeposition rate at this point, and y is the etch rate of the substrate. To avoid the consequences of unduly subjecting the redeposited mask material to etching, an angle should be avoided at any point on redepcsited material serving to mask the sidewalls that is greater than arctan (Xz) where z is the etch rate of the redeposited material in a direction parallel to the etchant species momentum direction. (The angle of the redeposited mask at a point is the angle fonmed between the direction of species momentum and a tangent to the mask at this point.) The consequence of violating the angle criterion for the resist mask iB loss of linewidth controI. Surprisingly, this loss occurs despite the formation of barrier redeposited material underlying the eature-defining edge of the resist mask. Thus, even in an etchant system that induces production of barrier redeposition, the resist angle criterion should be satisfied. The consequence in many circumstances of violating the angle criterion for the redeposited ~aterial is often even more severe. For example, when -the angle criterion is violated at a point on the redepocited surface, a portion of the underlying sidewalI is exposed. If the etchant species has a significant lateral etch rate for this exposed material, such lateral etching guickly propagates, and ,. -. ~ .. : . , . . . . :
-- lZ8~S56 configurations such as those shown in FIG. 3 are obtained. If there is not a significant l~teral etch rate, severe consequences are s~ill possible. For exanple, the dynamic proce~ses involved in redeposition lead, upon further etching, to curvature of an exposed sidewall, such as shown in FIG. 8, where 81 i5 the material being etched, 80 is the resist, and 82 is the redeposited ~aterial. Continued redeposition on this curved surface presents slowly etched materials at the etch pit bottom and thus concomitantly decrea~es the rate of etch pit depth propagation. This etch rate decrease correspondinqly increases cost and increases the possibility of unacceptable resist mask erosion before the feature is totally delineated. Alternately, upon intersection of the etch pit with an underlying material, 85, undesirable etching of this underlying material will often continue for an unacceptable time while the slowly etched extremitie~ of the protected etch pit bottom are removed.
To avoid these consequencesl the angle of the redeposited material is controlled by controlling the amount of redeposited material formed at the bottom of the etch pit as compared to the top. Generally, to avoid a violation of the redeposited mask angle criterion, the rate of redeposition at the bottom of the etch pit should be no ~ore than 10 times the redeposition at the top of the etch pit. unifonmities are typically attained by expedients such as changing the geometry and thus changing the redeposition rate at the bottom of the etch pit relative to the top.
Violation of the resist ~ask angle criterion - also results in unacceptable conseque~ces such as loss of linewidth control. When the resist ~ask angle criterion i~ violated, erosion occurs in a pro~ressive ser~ies~shown in FIGS. 9-11. A9 can be seen, material is eroded from under the ma~k, resulting in feature .~
dimensi~ons~ signiicantly s~aller from tho~e desired. An , . :~ . . .. . :
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exemplary expedient for producing an essentially vertical resist wall and the desired resist mask angle control is use of a trilevel mask, such as described in U.S. Patent 4,2~4,799, issued January 13, 19~1.
The following examples are illustrative of the invention.
Example 1 A 7.6 cm (3 inch) in diameter silicon substrate having its major surface in the (100) plane was cleaned by conventional methods. The substrate was placed on the sample holder of a tube furnace. The furnace was heated to a temperature of 700 degrees C.
Tetraethylorthosilicate was introduced into the furnace at a flow rate of ~0 sccm to yield a pressure of approximately 33.34 Pa (0.25 Torr). The tetraethylorthosilicate flow was continued for a sufficient time to produce a layer thickness of 3 ~m.
The substrate was removed from the furnace, and a 1.8 ~m layer of HPR 206 resist ta proprietary product of Hunt Chemical Company, which is basically a novolak resin with a quinone diazide sensitizer) was applied utilizing spin coating at 4000 rpm. The substrate was baked at 200 degrees C for 1 hour and was then~placed, with the baked HPR layer exposed, on the grounded electrode of a radial flow parallel plate plasma apparatus. The apparatus was evacuated, and 5 percent silane in argon and nitrous oxide were introduced at a flow rate of 1.44 l/min and 1.56 1/min, respectively. The pumping speed was then adjusted to give a total pressure of 133.3 Pa (1.0 Torrj. An rf discharge was struck utilizing a frequency of 13.56 MHz at a power density of approximately O.OlO W/cm2. The plasma was extinguished after a silicon oxide layer of approximately 120 nm was deposited~. The remaining gases were evacuated from the chamber;and the substrate removed. A 700 nm thick layer of dichloropropylacrylate mixed with a copolymer was . ,:
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formed by spinning at a speed of 2200 rpm. The substrate was placed on the sample holder of an X-ray exposure apparatus with a palladium L~ source. The exposure mask had a boron nitride membrane with an S overlying gold pattern. This gold pattern had uniformly spaced holes varying in diameter from 0.3 ,um to 2.0 ,um.
The X-ray exposure was continued until a total dose of 15 mjoules/cm2 was provided. The exposed resist was then developed by immersion in a mixture of isopropyl alcohol and methyl ethyl ketone to uncover a portion of underlying silicon oxide in the desired pattern. The substrate was transferred to the powered cathode of a hexagonal cathode etching apparatus. The chamber was evacuated, and CHF3 was introduced at a flow rate of lS 60 sccm yi~elding a pressure of 1.33 Pa (lO mTorr). A
plasma was struck utilizing an rf frequency of 13.56 MHz and a power density o~ approximately 0.03 W/cm2~ The etching was continued until the uncovered silicon oxide material was removed to uncover corresponding portions of underlying HPR. The CHF3 was evacuated, and oxygen at a flow rate of 70 sccm was introduced to yield a pressure of 0.4 Pa (3 mTorr)~. Again, a plasma was struck at a power density of 0.08 W/cm2. This etching ~was~continued unt~il the uncovered HPR 206 resist was removed.~ The chamber was evacuated, back-filled with nitrogen,~and the~ substrate removed.
The substrate~was placed on the powered cathode~of~a~secood;hexagonal reactor. This reactor included silicon-coated trays which surrounded the substrates that occupled areas of~the hexagonal cathode ~f~acets not~occupied by the substrates.~ The chamber was evacuated;,~ and CHF3 was introduced at a flow rate of 30'sc'cm~to~;~produce;a pressure of 9.33 Pa (70 mTorr).
~; The~plasma~was struck utilizing an rf frequency of 35~13~.~56~MHz~and a power density of 0.16 W/cm2. The plasma was~extl~ngoi5hed~after a measured period oE time. The ' chamber was again evacuated, back-filled with nitrogen, ,:
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and the substrate removed. The time period utilized was sufficiently short so that etching did not proceed through the entire thickness of the silicon oxide layer underlying the HPR. The substrate was observed utilizing a scanning electron microscope. This observation was done by cleaving and polishing the substrate and ~easuring the etch depth associated with different diameter mask holes. It was found that there was a large variation in etch rates, depending on the mask opening. For example, etch rates of 7.5 nm/minute were obtained for a 0.3 ~m opening, etch rates of 20 nm/minute were obtained for a 0.6 ,um opening, and etch rates of 25 nm/minute were obtained for openings of 1 um and larger. Each etch pit additionally exhibited a rounded bottom, such as that illustrated by FIG. 8. The curvature of this bottom was significantly greater for the smaller-sized mask openings.
; Example 2 A 10.2 cm (4 inch) in diameter silicon substrate having its major surface in the (100) plane was cleaned by conventional techniques. The substrate was placed in a furnace at 950 degrees C in an atmosphere of dry oxygen plus 2 percent HCl. The substrate was maintained under these conditions for 22 minutes to produce a 25 nm thick thermal oxide layer.
- A region~of silicon, 400 nm thick, was deposited on the thèrmal oxide. This deposition was accomplished by low pressure chemical vapor deposition as described in Example~l for the silicon oxi~de~deposition, e~cept that undiluted~sllane was atil~ized at a pressure ~of 33.34 Pa (0.25 Torr). The;substrate was immersed in ~100:1 H2o/HF~rinaed in~deionized water, and dried.
~; Arsenic~ions were implanted into the substrate by ~exposure~t~o arsenic ions~accelerated through a potential 35~;~of~60~KeV~for a period sufficient to yield a total dose o~~ x~1015 arsenic/cm2. The substrate was placed, with the æ~ilicon layer exposed~, on the sample holder of co-. .; : ., , ;
. ' .. ,, ~, : :. . . .. . .
~LX8755i6 silicon and tantalum were utilized. These sources were controlled to yield a filn whose composition ha~ a ratio of approxi~ately 2:1 silicon-to-tantalum. The co-deposition was continued until a layer thickness of S approximately 250 nm was achieved. The su~strate was removed from the co-depositing apparatus and placed in an argon ambient at 650 degrees C for 30 minutes.
The trilevel re~ist, as described in Example 1, was forned utilizing a bottom layer of HPR, an intermediate layer of silicon oxide, but utilizing a 700 nm thick upper photoresist layer of Microposit 1400, manufactured by Shipley Company Inc. of Newton, Massachusetts, which was deposited by spin coating. The upper photoresist was exposed by projection printing (projection ratio of approximately 5:1) utilizing a reticle having a pattern corresponding to the gate level of an NMOS integrated circuit. Thus, this pattern contained a series of lines that were, in so~e regions, closely spaced~ The exposing source was a 350 watt mercury arc bulb using the 405 nm line. ~he exposed photo-sensitive layer was developed by immersion for 0.5 minute in Microposit 453 developer ~manufactured by Shipley Company Inc.). The underIying uncovered silicon ox~de and HPR layers were developed as described in Example 1.
The substrate with thé delineated pa~tern was placed on a~hexagonal reactor having polyarylate trays.
The chamber was evacuated, and Ccl3F was introduced at a --flow rate of 30 sccm to yield a partial pressure of 0.93 Pa t7 mTorr). A plasma was struck utilizing an rf~frequency o~ 13.56 MHz and a powèr density of .03~W/om2. The;pla~ma was e~tinguished after the etching~had proce~eded through the tantalum/silicon ~reg~ion and~partially into the underlying silicon region.
The chamber was again evacuated, and molecular chlorine ~gas~was introduced at a flow rate of 60 sccm to yield a pa~rtial pressure of 5.33 Pa (40 mTorr). A plasma was : . - .~ : . . . ..
~ ~37556 again struck and extinguished after a time p~riod 1.5 tii~es greater than that necessary to remove the entire remaining silicon layer.
The substrate after cleaving was observe3d in a scanning electron microscope. Where sidewalls were in close proximity (case 2), cross-sectional views, as illustrated in ~IG. 3, were obtained. Profiles illustrated in FIG. 5 were obtained where features were not in close proximity (case 3).
- - - . ,, : .. , , . . .. ,, ,.............. , :
-- 1 , PROCEDURE FOR FABRICATING DEVICES
INVOLVING DRY ETCHING
.
Backqround of the Invention 1. Field o~ the Invention This invention relates to semiconductor device processing involving dry etching.
The backgxound of the present invention will be discussed in detail hereinbelow.
In accordance with one aspect of the invention there is provided a process for fabricating a device comprising the steps of forming a resist mask on a substrate, etching said substrate to form a plurality of etch pits defining a plurality of features by inducing reaction of said substrate with energetic species, and completing said device, wherein redeposition of material on the sidewalls of said etch pit occurs during said etching characterized in that said process includes at least one step chosen from the group consisting of l) locally compensating for the effect of said redeposition on ~ 20 the conformation of sald sidewall, 2) when said redeposited ;~
- material presents a barrier to isotropic etching in said -~
substrate,~ contacting said etchant species with said resist mask so that the angle formed between a) a tangent to said resist mask at the~point said resist mask intersects the ` 25 substrate and b) a~perpendicular to said substrate at said oint is~less than arctan (XjY),~where x is the horizontal rate of sa~id redeposition~at said point and~v is the etch rate ~ -~
of said substrate, and 3) limiting, when said redeposited `
material presents a barrier to isotropic etching in said substrate,~the contact~angle between~the momentum direction of said etchant~species~and a tangent to said redeposited materiàl~at all~p~oints on~said resistan~ redeposited material serving~to~masX~said sidewalls so that said contact angle is ;less~than~arctan~(X/Z),~ where z is the~etch rate of said resistant~redeposited material in a direction parallel to said etchant~species~momentum direction.
~ " , .: ~ ~ , Brief Description of the Drawinq FIGS. 1-3 illustrate sidewall configura~ions sometimes obtained after etching;
FIGS. 4 and 5 illustrate possible configurations of redeposition;
FIGS. 6 and 7 illustrate the effect of configuration on redeposition; and FIGS. 8-11 illustrate the effect of mask angle.
Semiconductor devices are generally fabricated on a substrate through a series of processing steps including deposition of semiconductor materials, metals, insulators, and the etching of these materials in selected patterns. In one common etching method, a reactive etchant species is generated in a plasma and directed at a high velocity by an electric field towards the material to be etched. Generally during etching, the material being etched is masked in selected regions from this reactive species by a composition such as a polymer (typically denominated a resist) that has been delineated in a desired pattern~ Thus, the pattern of the resist is transferred during the etching process to the underlying etched material. As a result, the device configurations desired in semiconductor, insulator, and/or metal regions are produced.
Accelerated reactive species are advantageously utilized in etching because they typically produce anisotropic etching, i.e., etching where the etch rate at any point along the etch pit wall in the direction of etchant species momentum is at least ten times greater than the etch rate in the direction normal to this velocity vector. Two effects generally contribute to the attainment of anisotropic etching. In one circumstance, a material to be etched, such as silicon, reacts with certain species, e.g., Cl~, only when the species has significantly higher momentum than that associated with room temperature. Thus, when such a species is accelerated essentially perpendicularly to the substrate surface, etching preferentially occurs in this direction rather than the remaining random directions associated with etchant species which are only thermally activated. In a second circumstance, '~
! - ' ~: ', ~8~S~i6 such as in the etching of aluminum by species generated in a Cl2/C2F6 plasma, material which is resis~ant to isotropic etching is produced during the etching process, is redeposited on the sidewalls of the etch void, and promotes anisotropic etching. (See U.S. Patent ~,208,241, issued June 17, 1980, where a recombinant species forms such a resistant material.) That is, the redeposited material acts as an etch mask.
The attainment of anisotropic etching through one or both of these mechanisms is significant because it promotes maintenance of the unetched region dimensions (frequently called linewidth control), facilitates subsequent processing, and allows lines to be closely spaced. For example, when isotropic etching, i.e., a lateral etch rate that is at least one-tenth of the etch rate in the etchant momentum direction, rather than anisotropic etching is achieved, etch profiles, 14, such as those shown in FIG. 1 are produced utilizing a resist, 15. Obviously, the attainment of isotropic rather than anisotropic etching reduces linewidth control, i.e., the percentage between 1) the largest deviation of any feature from the corresponding desired feature, 12, defined by the mask at the substrate surface and 2) one-half the linewidth, 12, defined by the mask. (A feature deviation is thus the distance from any point on an etch sidewall measured perpendicularly to a surface extending from the extremities of the mask region defining this feature in a direction perpendicular to the surface at each point along the mask extremity.) Similarly, linewidth control is also compromised, as shown in FIG. 2 where 15 indicates the resist, if the sidewalls slope in the opposite direction. Configurations such as those shown in FIGS. 1 and 2 are undesirable because they interfere with subsequent processing as well as contributing to loss of linewidth control. For example, if the etched line is itself to be used as a mask, e.g., for an ion implantation mask, any linewidth gain or loss augments the associated inaccuracies in subsequent mask use.
Alternatively, if an insulating layer is to be formed on the etch sidewalls by deposition onto all surfaces followed by an ` anisotropic etch to remove the material from lateral surfaces, .` ' `
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then the tapered profile in FIGS. 1 and 2 will compromise the insulating layer on the sidewall during the anisotropic etch.
Although sidewall redeposition during etching has been associated in many circumstances with the maintenance of anisotropic etching, it does present some difficulties. As discussed by Kinsbron, Levinstein, and Willenbrock in U.S.
Patent 4,343,677, issued August 10, 1982, it is desirable to remove these sidewall redeposits because 1) they tend to be dislodged during subsequent processing, 2) they often assume undesirable shapes, and 3) they frequently have undesirable electrical or mechanical properties. Sidewall redeposition also does not always ensure anisotropy. Despite the occurrence of sidewall redeposition and the use of energetic reactive species, anomalous etching patterns such as shown at 16 in FIG. 3 (where 15 is the resist) have been observed.
These anomalies are generally undesirable because they degrade feature mechanical stability and conductivity.
The presence of sidewall redeposits has a significant, previously unrecognized effect beyond that of resistance to - the etchant species. In particular, the greater the amount of sidewall redeposition, the greater the slope of the sidewall after the redeposited mas~ material is removed. The inventors have also found that the amount of this redeposition is critically dependent on the local feature geometry surrounding the sidewall. Thus, in circumstances where linewidth control is critical, such as in circumstances where etch features critically control device parameters, e.g., the gate length in a field effect transistor, local compensation should be made for redeposition onto etch sidewalls. For example, the resist mask should be appropriately adjusted in local regions of excess redeposition, or feature geometry should be adjusted in these regions.
Linewidth control is also affected by other previously unrecognized effects. To protect linewidth and ensure acceptable etch rates, a mask material surface (including the surface of redeposited material that contributes to the attainment of anisotropy) should be carefully adjusted. If the configuration of the redeposited material is controlled, , ~; - .
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1~'7556 - 4a -anomalous etching effects, such as shown in Fig. 3, and anomalously slow etch rates are avoided. The profile o the resist mask also affects the configuration of the sidewall, i.e., the etch pit boundary-after the redeposition is removed.
If the portion o the resist defining the etch pattern presents a surface forming an excessive angle with the momentum direction of the reactive species, linewidth control is unacceptably degraded. All these effects become particularly important when linewidth control of 0.1 ~ or better is desired.
. .
. .
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The inventors have found that important etching properties, such as etching speed and linewidth, depend strongly on the redeposition process. A first prime consideration is the extent of redeposition. The greater ~he rate of redeposition onto the sidewall, the greater the slope of this sidewall. (In this context, the etch pit sidewall is the configuration of the surface of the etch pit when the redeposited material, i.e., the material added to the sidewall during etching, is removed.) If redeposition occurs, sidewall slope (deviation from the etchant species momentum direction) occurs and the extent of this slope directly depends on the magnitude of the redeposition onto the etch sidewall at the bottom of the etch pit. The effect of lS redeposition on etching efficacy is illustrated in FIGS. 4 and 5. If a small amount of redeposition, 23, occurs, then sidewall angles such as shown in FIG. 4 at 20 are obtained. In contrast, if a relatively large amount is redeposited, then configurations such as that shown in FIG. 5 are obtained, where the stippled region, 23, indicates the redeposited material, 20 ~-~
indicates the surface of the sidewall, and 41 is the resist. As shown in FIGS. 4 and 5, as the angle of the side~all increases, linewidth control is lost. Thus, compensation for this linewidth loss should be made.
Generally, this compensation is accomplished by -` 1) adjusting the lithographic process, e.g., utilizing - suitably narrow lines to ~compensate for linewidth ~-broadening and thus to yield the desired linewidth, and/or 2) limiting the extent of redeposition. In the second approachj;the redeposition should be limited so that after etching the angle between 1) the linear ~ :
, . .~ .,;, : ~ :
-: :
least-squares-fit to the sidewall and 2) the direction of the etchant species momentum vector surface at the intersection of the least-squares-fit is sufficiently small to produce the desired linewidth control, e.g., an S angle smaller than 12 degrees for a feature deviation of 0.1 ,um with an etch pit depth of 0.5 ~m.
The amount of redeposition, however, is not uniform across a substrate. A predominant source of redeposition is by-product species from the etched material. The angle of the sidewall, except in anomalous cases to be subsequen~ly discussed, depends, to an excellent approximation, on the ratio between 1) the redeposition flux at the interface between the etch pit bottom and the redeposited material and 2) the etch ra~e of the material being etched in the direction of species momentum. The redeposition flux at the -bottom of the etch pit is directly dependent on the area of the etch pit bottom. The relative geometries and config;urations of the features define this area and thus strongly affect sidewall angle. As a result, redeposition depends strongly on the local geometry, and thus compensation should be tailored to this local variance.
Th~ree~geometry types are commonly involved in the formation~o~f devices. The first case involves ~featùr~ès~having proximate sidewalls, i.e., an etch pit which has a characteristic distance and whose depth is at least~as~large as half of its characteristic distance. ~An etched void has~a~characteristic distance 30 ~if the largest and smallest dimensions of the figure ~formed by the~intersection` of the mask with the ~substràte surface~difer by l~ess than 50 percent. (A
dimension of~a figure i5 the inscribed distance of a line~from~one~point~on the figure across the igure 35~th;rough~the center of mass of the figure.) The second situation~ nvolves a~trench configuration, i~e., an etched~-r~egion deflned~by~the mask 1) is bounded by two ~ ~ :
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- . . .. . . . . -. ' . . : ,~ . ,:. . . . . .
~2~55~
substantially parallel lines separated by not more than 7 times the etch pit depth and 2~ these parallel lines are longer than 1.5 times this separati~n. The third case involves an open feature, i.e., the closest etch sidewall is at least greater than 7 etch pit depths away from every other sidewall forming the etch pit. (It should be noted that in one etch pit it is possible to have a poLtion falling within one case, e.g., case 2, and a second portion falling within a second case, e.g., case 3. For example, an etch pit with a dumhbell shape has two case 1 regions and one case 2 region.) In the first and second cases, the sidewall redeposition is significantly less than in the third case because of a smaller ~ource of redeposition flux.
In the third case, the area of the etch pit bottom is the greatest, and the amount of redeposition is correspondingly large. Thus, typically, open features such as 62, shown in the plan view of FIG. 6, are preferably avoided. (In FIGS. 6 and 7, 61 is a resist that defines gates and that defines gate conductors which extend over thick field oxide, 80, and into the transistor regions, 84. Additionally, transistor regions repeating the configuration of regions, 84, have been omitted for clarity~) For example, in one embodiment, non-functional features are formed to convert case (3) situations on a substrate to case (2) ; configurations. In~a second embodiment, this conversion is accomplished by changing one or more functional features,~e.g., conductors are rerouted so they pass within a rela~tively~short distance of the open sidewall (72 and 73~in~F~IG. 7). Thus, a feature is relocated from a~path of least meander, i.e., the shortest distance~consistent with device design between points to be~electr~ically contacted, so that it limits the area of 35; ~;an :etch~ pit bo~ttom. ~The objectional local confi~uration i~s, ~in~this way, transformed from an open configuration ~ to a configuration within case (2). Thus, compensation - : : :~ :
: ~ , :... .. , , , , : .
.: . ~- , : , 55~;
is accomplished locally in regions where linewidth control is required to maintain device properties.
(Locally, in this context, is compensation in at least one region, but not all regions of a plurality of S regions which are designed to have the same linewidth.) third embodiment involves locally compensating the resist mask. In this embodiment, instead of converting from one case to another, the resist mask in a localized area is modified to compensate for the sidewall variations occurring with different geonetric cases.
For example, in FIG. 6, the resist feature defining gate 61, over region 62, is decreased sufficiently from ; that of regions, 8~, to compensate for the local linewidth broadening occurring in this case 3 region.
This embodiment is generally less desirable since, as previously discussed, the sidewall is tapered.
As previously noted, the angle of the sidewall also depends on the substrate etch rate. Thus, an auxiliary approach to local co~pensation for sidewall angle is the control, irrespective of source, of the reactant species composition in the plasma. For example, silicon trenches are typically etched utilizing a C12 based etchant gas with an organic polymeriSiO2 mask. By the slimination of the polymer mask layer, the amount of~redeposition is reduced, and thus the amount of sidewall~ angle undergoes a concomitant reduction.
Thus,~it is possible to atilize a change in ~ configuration, as previously discus ed, in conjunction i with an appropriate modification of the etching gas chemistry~to~urther reduce the amount of redeposikion.
Anomalou~s~situations, e.g., catastrophic iso~ropi;c;~etching;, linewidth loss, and/or unaccep~ably ~slow etch~;rate, also ocaur. These situ~tion~ are pr;oduced~when material functioning as a mask ~i.e., either 1;)~`~redeposited ma~terial that is acting as a barrier~o lateral etching or 2) the feature-de~ining edge~of~a~re~ist material) during etching is ' ' ' '' . .. '. : ' : ,: ', . ' ~, " : ,. .. , , . . ' ~8~5~
9 _ substantially s~bjected to non-glancing i~pact by the etchant species. (A redeposited material is considered a barrier to etching when the redeposited material does not etch isotropically.) Such undesirable contact depends upon the configuration of the mask surf~ce. To avoid disadvantageous loss of linewidth by violating the angle criterion for the resist mask, at the inception of etching the angle fon~ed between a tangent to the mask at the point it intersects the substrate and a perpendicular to the substrate at this point should be less than arctan (y), where x is the horizontal redeposition rate at this point, and y is the etch rate of the substrate. To avoid the consequences of unduly subjecting the redeposited mask material to etching, an angle should be avoided at any point on redepcsited material serving to mask the sidewalls that is greater than arctan (Xz) where z is the etch rate of the redeposited material in a direction parallel to the etchant species momentum direction. (The angle of the redeposited mask at a point is the angle fonmed between the direction of species momentum and a tangent to the mask at this point.) The consequence of violating the angle criterion for the resist mask iB loss of linewidth controI. Surprisingly, this loss occurs despite the formation of barrier redeposited material underlying the eature-defining edge of the resist mask. Thus, even in an etchant system that induces production of barrier redeposition, the resist angle criterion should be satisfied. The consequence in many circumstances of violating the angle criterion for the redeposited ~aterial is often even more severe. For example, when -the angle criterion is violated at a point on the redepocited surface, a portion of the underlying sidewalI is exposed. If the etchant species has a significant lateral etch rate for this exposed material, such lateral etching guickly propagates, and ,. -. ~ .. : . , . . . . :
-- lZ8~S56 configurations such as those shown in FIG. 3 are obtained. If there is not a significant l~teral etch rate, severe consequences are s~ill possible. For exanple, the dynamic proce~ses involved in redeposition lead, upon further etching, to curvature of an exposed sidewall, such as shown in FIG. 8, where 81 i5 the material being etched, 80 is the resist, and 82 is the redeposited ~aterial. Continued redeposition on this curved surface presents slowly etched materials at the etch pit bottom and thus concomitantly decrea~es the rate of etch pit depth propagation. This etch rate decrease correspondinqly increases cost and increases the possibility of unacceptable resist mask erosion before the feature is totally delineated. Alternately, upon intersection of the etch pit with an underlying material, 85, undesirable etching of this underlying material will often continue for an unacceptable time while the slowly etched extremitie~ of the protected etch pit bottom are removed.
To avoid these consequencesl the angle of the redeposited material is controlled by controlling the amount of redeposited material formed at the bottom of the etch pit as compared to the top. Generally, to avoid a violation of the redeposited mask angle criterion, the rate of redeposition at the bottom of the etch pit should be no ~ore than 10 times the redeposition at the top of the etch pit. unifonmities are typically attained by expedients such as changing the geometry and thus changing the redeposition rate at the bottom of the etch pit relative to the top.
Violation of the resist ~ask angle criterion - also results in unacceptable conseque~ces such as loss of linewidth control. When the resist ~ask angle criterion i~ violated, erosion occurs in a pro~ressive ser~ies~shown in FIGS. 9-11. A9 can be seen, material is eroded from under the ma~k, resulting in feature .~
dimensi~ons~ signiicantly s~aller from tho~e desired. An , . :~ . . .. . :
... , .: -. , ~
. . ~ . ! , . , " ,'" ' ~. '. ,. . ' '' ' ' . ` ' `"'`, ~ ' ''.,' , ~ . , ', , ~2~7S~
exemplary expedient for producing an essentially vertical resist wall and the desired resist mask angle control is use of a trilevel mask, such as described in U.S. Patent 4,2~4,799, issued January 13, 19~1.
The following examples are illustrative of the invention.
Example 1 A 7.6 cm (3 inch) in diameter silicon substrate having its major surface in the (100) plane was cleaned by conventional methods. The substrate was placed on the sample holder of a tube furnace. The furnace was heated to a temperature of 700 degrees C.
Tetraethylorthosilicate was introduced into the furnace at a flow rate of ~0 sccm to yield a pressure of approximately 33.34 Pa (0.25 Torr). The tetraethylorthosilicate flow was continued for a sufficient time to produce a layer thickness of 3 ~m.
The substrate was removed from the furnace, and a 1.8 ~m layer of HPR 206 resist ta proprietary product of Hunt Chemical Company, which is basically a novolak resin with a quinone diazide sensitizer) was applied utilizing spin coating at 4000 rpm. The substrate was baked at 200 degrees C for 1 hour and was then~placed, with the baked HPR layer exposed, on the grounded electrode of a radial flow parallel plate plasma apparatus. The apparatus was evacuated, and 5 percent silane in argon and nitrous oxide were introduced at a flow rate of 1.44 l/min and 1.56 1/min, respectively. The pumping speed was then adjusted to give a total pressure of 133.3 Pa (1.0 Torrj. An rf discharge was struck utilizing a frequency of 13.56 MHz at a power density of approximately O.OlO W/cm2. The plasma was extinguished after a silicon oxide layer of approximately 120 nm was deposited~. The remaining gases were evacuated from the chamber;and the substrate removed. A 700 nm thick layer of dichloropropylacrylate mixed with a copolymer was . ,:
.. , - . . .- : . ., : , . -~:- .. .,: : ' ' . ~ . . ' : ' ~X~375~i~
formed by spinning at a speed of 2200 rpm. The substrate was placed on the sample holder of an X-ray exposure apparatus with a palladium L~ source. The exposure mask had a boron nitride membrane with an S overlying gold pattern. This gold pattern had uniformly spaced holes varying in diameter from 0.3 ,um to 2.0 ,um.
The X-ray exposure was continued until a total dose of 15 mjoules/cm2 was provided. The exposed resist was then developed by immersion in a mixture of isopropyl alcohol and methyl ethyl ketone to uncover a portion of underlying silicon oxide in the desired pattern. The substrate was transferred to the powered cathode of a hexagonal cathode etching apparatus. The chamber was evacuated, and CHF3 was introduced at a flow rate of lS 60 sccm yi~elding a pressure of 1.33 Pa (lO mTorr). A
plasma was struck utilizing an rf frequency of 13.56 MHz and a power density o~ approximately 0.03 W/cm2~ The etching was continued until the uncovered silicon oxide material was removed to uncover corresponding portions of underlying HPR. The CHF3 was evacuated, and oxygen at a flow rate of 70 sccm was introduced to yield a pressure of 0.4 Pa (3 mTorr)~. Again, a plasma was struck at a power density of 0.08 W/cm2. This etching ~was~continued unt~il the uncovered HPR 206 resist was removed.~ The chamber was evacuated, back-filled with nitrogen,~and the~ substrate removed.
The substrate~was placed on the powered cathode~of~a~secood;hexagonal reactor. This reactor included silicon-coated trays which surrounded the substrates that occupled areas of~the hexagonal cathode ~f~acets not~occupied by the substrates.~ The chamber was evacuated;,~ and CHF3 was introduced at a flow rate of 30'sc'cm~to~;~produce;a pressure of 9.33 Pa (70 mTorr).
~; The~plasma~was struck utilizing an rf frequency of 35~13~.~56~MHz~and a power density of 0.16 W/cm2. The plasma was~extl~ngoi5hed~after a measured period oE time. The ' chamber was again evacuated, back-filled with nitrogen, ,:
~: i , ~ ;- - -:; ,: . . . , . , :: , . ~ . - . , ~, . . . . . .. . .
,, , ~ . ~ ", : : : , .. . . . .
~L~87~
and the substrate removed. The time period utilized was sufficiently short so that etching did not proceed through the entire thickness of the silicon oxide layer underlying the HPR. The substrate was observed utilizing a scanning electron microscope. This observation was done by cleaving and polishing the substrate and ~easuring the etch depth associated with different diameter mask holes. It was found that there was a large variation in etch rates, depending on the mask opening. For example, etch rates of 7.5 nm/minute were obtained for a 0.3 ~m opening, etch rates of 20 nm/minute were obtained for a 0.6 ,um opening, and etch rates of 25 nm/minute were obtained for openings of 1 um and larger. Each etch pit additionally exhibited a rounded bottom, such as that illustrated by FIG. 8. The curvature of this bottom was significantly greater for the smaller-sized mask openings.
; Example 2 A 10.2 cm (4 inch) in diameter silicon substrate having its major surface in the (100) plane was cleaned by conventional techniques. The substrate was placed in a furnace at 950 degrees C in an atmosphere of dry oxygen plus 2 percent HCl. The substrate was maintained under these conditions for 22 minutes to produce a 25 nm thick thermal oxide layer.
- A region~of silicon, 400 nm thick, was deposited on the thèrmal oxide. This deposition was accomplished by low pressure chemical vapor deposition as described in Example~l for the silicon oxi~de~deposition, e~cept that undiluted~sllane was atil~ized at a pressure ~of 33.34 Pa (0.25 Torr). The;substrate was immersed in ~100:1 H2o/HF~rinaed in~deionized water, and dried.
~; Arsenic~ions were implanted into the substrate by ~exposure~t~o arsenic ions~accelerated through a potential 35~;~of~60~KeV~for a period sufficient to yield a total dose o~~ x~1015 arsenic/cm2. The substrate was placed, with the æ~ilicon layer exposed~, on the sample holder of co-. .; : ., , ;
. ' .. ,, ~, : :. . . .. . .
~LX8755i6 silicon and tantalum were utilized. These sources were controlled to yield a filn whose composition ha~ a ratio of approxi~ately 2:1 silicon-to-tantalum. The co-deposition was continued until a layer thickness of S approximately 250 nm was achieved. The su~strate was removed from the co-depositing apparatus and placed in an argon ambient at 650 degrees C for 30 minutes.
The trilevel re~ist, as described in Example 1, was forned utilizing a bottom layer of HPR, an intermediate layer of silicon oxide, but utilizing a 700 nm thick upper photoresist layer of Microposit 1400, manufactured by Shipley Company Inc. of Newton, Massachusetts, which was deposited by spin coating. The upper photoresist was exposed by projection printing (projection ratio of approximately 5:1) utilizing a reticle having a pattern corresponding to the gate level of an NMOS integrated circuit. Thus, this pattern contained a series of lines that were, in so~e regions, closely spaced~ The exposing source was a 350 watt mercury arc bulb using the 405 nm line. ~he exposed photo-sensitive layer was developed by immersion for 0.5 minute in Microposit 453 developer ~manufactured by Shipley Company Inc.). The underIying uncovered silicon ox~de and HPR layers were developed as described in Example 1.
The substrate with thé delineated pa~tern was placed on a~hexagonal reactor having polyarylate trays.
The chamber was evacuated, and Ccl3F was introduced at a --flow rate of 30 sccm to yield a partial pressure of 0.93 Pa t7 mTorr). A plasma was struck utilizing an rf~frequency o~ 13.56 MHz and a powèr density of .03~W/om2. The;pla~ma was e~tinguished after the etching~had proce~eded through the tantalum/silicon ~reg~ion and~partially into the underlying silicon region.
The chamber was again evacuated, and molecular chlorine ~gas~was introduced at a flow rate of 60 sccm to yield a pa~rtial pressure of 5.33 Pa (40 mTorr). A plasma was : . - .~ : . . . ..
~ ~37556 again struck and extinguished after a time p~riod 1.5 tii~es greater than that necessary to remove the entire remaining silicon layer.
The substrate after cleaving was observe3d in a scanning electron microscope. Where sidewalls were in close proximity (case 2), cross-sectional views, as illustrated in ~IG. 3, were obtained. Profiles illustrated in FIG. 5 were obtained where features were not in close proximity (case 3).
- - - . ,, : .. , , . . .. ,, ,.............. , :
Claims (6)
1. A process for fabricating a device comprising the steps of forming a resist mask on a substrate, etching said substrate to form a plurality of etch pits defining a plurality of features by inducing reaction of said substrate with energetic species, and completing said device, wherein redeposition of material on the sidewalls of said etch pit occurs during said etching CHARACTERIZED IN THAT said process includes at least one step chosen from the group consisting of 1) locally compensating for the effect of said redeposition on the conformation of said sidewall, 2) when said redeposited material presents a barrier to isotropic etching in said substrate, contacting said etchant species with said resist mask so that the angle formed between a) a tangent to said resist mask at the point said resist mask intersects the substrate and b) a perpendicular to said substrate at said point is less than arctan (x/y), where x is the horizontal rate of said redeposition at said point and y is the etch rate of said substrate, and 3) limiting, when said redeposited material presents a barrier to isotropic etching in said substrate, the contact angle between the momentum direction of said etchant species and a tangent to said redeposited material at all points on said resistant redeposited material serving to mask said sidewalls so that said contact angle is less than arctan (x/z), where x is as defined in step
2), where z is the etch rate of said resistant redeposited material in a direction parallel to said etchant species momentum direction.
2. The process of claim 1 wherein said feature comprises a gate of a transistor.
2. The process of claim 1 wherein said feature comprises a gate of a transistor.
3. The process of claim 1 wherein said compensation comprises adjusting the local dimension of said resist mask.
4. The process of claim 1 wherein said compensation comprises forming a non-functional feature in proximity to at least one of said features.
5. The process of claim 1 wherein said compensation comprises diverting one of said features from a route of least meander to be in proximity with a second of said features.
6. The process of claim 1 wherein said substrate comprises silicon.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US75008485A | 1985-06-28 | 1985-06-28 | |
US750,084 | 1985-06-28 |
Publications (1)
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CA1287556C true CA1287556C (en) | 1991-08-13 |
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Application Number | Title | Priority Date | Filing Date |
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CA000512190A Expired - Fee Related CA1287556C (en) | 1985-06-28 | 1986-06-23 | Procedure for fabricating devices involving dry etching |
Country Status (6)
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EP (1) | EP0229104A1 (en) |
JP (2) | JPS62503204A (en) |
KR (1) | KR930006526B1 (en) |
CA (1) | CA1287556C (en) |
ES (1) | ES8800511A1 (en) |
WO (1) | WO1987000345A1 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS6289331A (en) * | 1985-10-16 | 1987-04-23 | Toshiba Corp | Processing fine pattern |
EP0416809A3 (en) * | 1989-09-08 | 1991-08-07 | American Telephone And Telegraph Company | Reduced size etching method for integrated circuits |
US5492552A (en) * | 1994-03-03 | 1996-02-20 | Minnesota Mining And Manufacturing Company | Holder for annealing fiber optic coils |
US5463312A (en) * | 1994-03-03 | 1995-10-31 | Minnesota Mining And Manufacturing Company | Faraday-effect sensing coil with stable birefringence |
JP2924723B2 (en) * | 1995-08-16 | 1999-07-26 | 日本電気株式会社 | Dry etching method |
EP1844495B1 (en) * | 2005-01-24 | 2011-07-27 | Panasonic Corporation | Manufacturing method for semiconductor chips |
KR102164381B1 (en) * | 2018-12-10 | 2020-10-12 | 연세대학교 산학협력단 | Method for manufacturing nanostructure and nanostructure manufactured by using the same |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US4208241A (en) * | 1978-07-31 | 1980-06-17 | Bell Telephone Laboratories, Incorporated | Device fabrication by plasma etching |
JPS5713180A (en) * | 1980-06-25 | 1982-01-23 | Fujitsu Ltd | Etching method |
CA1202597A (en) * | 1981-05-22 | 1986-04-01 | Jean S. Deslauriers | Reactive ion layers containing tantalum and silicon |
US4436584A (en) * | 1983-03-21 | 1984-03-13 | Sperry Corporation | Anisotropic plasma etching of semiconductors |
-
1986
- 1986-05-27 KR KR1019870700161A patent/KR930006526B1/en not_active IP Right Cessation
- 1986-05-27 JP JP61503237A patent/JPS62503204A/en active Pending
- 1986-05-27 EP EP86903910A patent/EP0229104A1/en not_active Ceased
- 1986-05-27 WO PCT/US1986/001155 patent/WO1987000345A1/en not_active Application Discontinuation
- 1986-06-23 ES ES556460A patent/ES8800511A1/en not_active Expired
- 1986-06-23 CA CA000512190A patent/CA1287556C/en not_active Expired - Fee Related
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2000
- 2000-01-27 JP JP2000018691A patent/JP2000216148A/en active Pending
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KR930006526B1 (en) | 1993-07-16 |
ES8800511A1 (en) | 1987-11-16 |
ES556460A0 (en) | 1987-11-16 |
WO1987000345A1 (en) | 1987-01-15 |
KR880700459A (en) | 1988-03-15 |
JP2000216148A (en) | 2000-08-04 |
EP0229104A1 (en) | 1987-07-22 |
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