KR100205669B1 - 메모리 셀 회로 및 어레이 - Google Patents

메모리 셀 회로 및 어레이 Download PDF

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Publication number
KR100205669B1
KR100205669B1 KR1019910025486A KR910025486A KR100205669B1 KR 100205669 B1 KR100205669 B1 KR 100205669B1 KR 1019910025486 A KR1019910025486 A KR 1019910025486A KR 910025486 A KR910025486 A KR 910025486A KR 100205669 B1 KR100205669 B1 KR 100205669B1
Authority
KR
South Korea
Prior art keywords
transistor
forming
cells
transistors
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019910025486A
Other languages
English (en)
Korean (ko)
Other versions
KR920013465A (ko
Inventor
마크지.하워드
쉬발링에스.마한트-쉐티
하워드티겔라르
Original Assignee
윌리엄 비. 켐플러
텍사스 인스트루먼츠 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윌리엄 비. 켐플러, 텍사스 인스트루먼츠 인코포레이티드 filed Critical 윌리엄 비. 켐플러
Publication of KR920013465A publication Critical patent/KR920013465A/ko
Application granted granted Critical
Publication of KR100205669B1 publication Critical patent/KR100205669B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G11C11/4023—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh using field effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
KR1019910025486A 1990-12-31 1991-12-30 메모리 셀 회로 및 어레이 Expired - Fee Related KR100205669B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/636,518 US5287304A (en) 1990-12-31 1990-12-31 Memory cell circuit and array
US636,518 1990-12-31

Publications (2)

Publication Number Publication Date
KR920013465A KR920013465A (ko) 1992-07-29
KR100205669B1 true KR100205669B1 (ko) 1999-07-01

Family

ID=24552248

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910025486A Expired - Fee Related KR100205669B1 (ko) 1990-12-31 1991-12-30 메모리 셀 회로 및 어레이

Country Status (6)

Country Link
US (1) US5287304A (enExample)
EP (1) EP0493830B1 (enExample)
JP (1) JPH04340762A (enExample)
KR (1) KR100205669B1 (enExample)
DE (1) DE69129404T2 (enExample)
TW (1) TW222705B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012178590A (ja) * 1998-05-01 2012-09-13 Sony Corp 半導体記憶装置

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4501164B2 (ja) * 1998-05-01 2010-07-14 ソニー株式会社 半導体記憶装置
US6418490B1 (en) * 1998-12-30 2002-07-09 International Business Machines Corporation Electronic circuit interconnection system using a virtual mirror cross over package
US7209383B2 (en) * 2004-06-16 2007-04-24 Stmicroelectronics, Inc. Magnetic random access memory array having bit/word lines for shared write select and read operations
US7372728B2 (en) * 2004-06-16 2008-05-13 Stmicroelectronics, Inc. Magnetic random access memory array having bit/word lines for shared write select and read operations
FR2871921A1 (fr) * 2004-06-16 2005-12-23 St Microelectronics Sa Architecture de memoire a lignes d'ecriture segmentees
US7136298B2 (en) * 2004-06-30 2006-11-14 Stmicroelectronics, Inc. Magnetic random access memory array with global write lines
US7301800B2 (en) * 2004-06-30 2007-11-27 Stmicroelectronics, Inc. Multi-bit magnetic random access memory element
US7079415B2 (en) * 2004-06-30 2006-07-18 Stmicroelectronics, Inc. Magnetic random access memory element
US7106621B2 (en) * 2004-06-30 2006-09-12 Stmicroelectronics, Inc. Random access memory array with parity bit structure
US7465973B2 (en) * 2004-12-03 2008-12-16 International Business Machines Corporation Integrated circuit having gates and active regions forming a regular grating
US10109637B1 (en) * 2017-12-28 2018-10-23 Globalfoundries Inc. Cross couple structure for vertical transistors

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611317A (en) * 1970-02-02 1971-10-05 Bell Telephone Labor Inc Nested chip arrangement for integrated circuit memories
US3638202A (en) * 1970-03-19 1972-01-25 Bell Telephone Labor Inc Access circuit arrangement for equalized loading in integrated circuit arrays
US4184208A (en) * 1978-07-19 1980-01-15 Texas Instruments Incorporated Pseudo-static semiconductor memory cell
JPS60136097A (ja) * 1983-12-23 1985-07-19 Hitachi Ltd 連想メモリ装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012178590A (ja) * 1998-05-01 2012-09-13 Sony Corp 半導体記憶装置

Also Published As

Publication number Publication date
EP0493830B1 (en) 1998-05-13
DE69129404D1 (de) 1998-06-18
KR920013465A (ko) 1992-07-29
JPH04340762A (ja) 1992-11-27
DE69129404T2 (de) 1998-10-29
US5287304A (en) 1994-02-15
EP0493830A3 (en) 1993-01-27
TW222705B (enExample) 1994-04-21
EP0493830A2 (en) 1992-07-08

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