KR100199829B1 - Lead frame - Google Patents

Lead frame Download PDF

Info

Publication number
KR100199829B1
KR100199829B1 KR1019960077919A KR19960077919A KR100199829B1 KR 100199829 B1 KR100199829 B1 KR 100199829B1 KR 1019960077919 A KR1019960077919 A KR 1019960077919A KR 19960077919 A KR19960077919 A KR 19960077919A KR 100199829 B1 KR100199829 B1 KR 100199829B1
Authority
KR
South Korea
Prior art keywords
lead
mounting plate
lead frame
package
semiconductor package
Prior art date
Application number
KR1019960077919A
Other languages
Korean (ko)
Other versions
KR19980058591A (en
Inventor
조중호
정영석
최경숙
Original Assignee
김규현
아남반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김규현, 아남반도체주식회사 filed Critical 김규현
Priority to KR1019960077919A priority Critical patent/KR100199829B1/en
Priority to JP9368625A priority patent/JP3047174B2/en
Publication of KR19980058591A publication Critical patent/KR19980058591A/en
Application granted granted Critical
Publication of KR100199829B1 publication Critical patent/KR100199829B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4801—Structure
    • H01L2224/48011—Length
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 반도체패키지용 리드프레임에 관한 것으로서, 반도체패키지(10)의 리드프레임(F)에 구비된 탑재판(CD)이 다수의 타이바에 연결되고, 탑재판(CD)외부에는 다수의 리드(L)가 형성된 것에 있어서, 상기 타이바중 패키지(P) 성형시 컴파운드재가 공급되는 측의 타이바(T1)와 이 반대측 타이바(T2)의 주변 리드(L) 선단을 탑재판(CD)과의 거리(2)가 크게 유지된 상태로 구비되고, 상기 타이바(T1)의 교차부분에 구비된 타이바(T3)(T4)주변의 리드(L)의 선단은 탑재판(CD)과의 거리(2)를 짧게 유지시켜 리드(L)의 선단 전체 형상이 타원형 형상의 영역(A)을 갖도록 한 것으로 패키지 성형시 컴파운드재의 충진공급 압력에 의한 와이어 스위핑 불량과 숏트 불량을 방지하여 제품의 품질 신뢰도를 높이고, 패키지성형 작업성을 용이하게 할 수 있는 효과가 있다.The present invention relates to a lead frame for a semiconductor package, wherein a mounting plate (CD) provided in the lead frame (F) of the semiconductor package 10 is connected to a plurality of tie bars, and a plurality of leads outside the mounting plate (CD). L) is formed, wherein the tip of the tie bar T1 on the side where the compound material is supplied during the molding of the package P among the tie bars and the peripheral lead L on the opposite side of the tie bar T2 are mounted on the mounting plate CD. Distance ( 2) is largely maintained, and the tip of the lead L around the tie bars T3 and T4 provided at the intersection of the tie bars T1 has a distance from the mounting plate CD. 2) is kept short so that the entire shape of the tip of the lead (L) has an elliptical area (A). There is an effect that can increase, and facilitate the package forming workability.

Description

반도체패키지용 리드프레임Leadframe for Semiconductor Package

본 발명은 반도체패키지용 리드프레임에 관한 것으로서, 특히 반도체패키지의 리드프레임에 형성된 탑재판과 이 외부에 다수의 리드가 형성되고, 탑재판과 대응하는 각 리드의 선단부는 패키지성형시 컴파운드재가 공급되는 측에서 반대측으로 소정형상의 타원형을 이룰 수 있도록 형성하여 리드의 불량을 방지한 반도체패키지용 리드프레임에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a semiconductor package. In particular, a mounting plate formed on a lead frame of a semiconductor package and a plurality of leads are formed outside the lead plate, and a tip of each lead corresponding to the mounting plate is supplied with a compound material during package molding. The present invention relates to a lead-frame for a semiconductor package which is formed to have an elliptical shape of a predetermined shape from a side to an opposite side, thereby preventing a defect of a lead.

일반적으로 리드프레임이 적용된 반도체패키지는 웨이퍼(Wafer)를 소잉(Sawing)공정에서 절단시켜 반도체칩을 다이 어태치(Die Attach)고정에서 리드프레임(Lead Frame)의 탑재판에 에폭시(Epoxy)를 이용하여 부착시킨다.In general, a semiconductor package to which a lead frame is applied cuts a wafer in a sawing process, and uses an epoxy in a mounting plate of a lead frame in fixing a die attach of the semiconductor chip. Attach it.

반도체칩이 부착된 리드프레임 자재는 와이어본딩(Wire Bonding)공정에서 반도체칩의 내부회로와 리드프레임의 각 리드전에 전기적 회로를 연결시키기 위해 금(Au) 또는 알루미늄(Al)으로 된 가는 선을 와이어본딩시키고, 외부에 노출된 와이어와 반도체칩과 각 리드가 외적인 힘과 부식 및 열 등에 의해 발생되는 손상과 전기적인 특성보호와 기계적인 안정성을 도모하기 위하여 컴파운드(Compound)재로 몰딩(Molding)공정에서 소정형태로 패키지(Package) 성형한다.Lead frame material with semiconductor chip is attached with thin wire made of gold (Au) or aluminum (Al) to connect the electrical circuit before each lead of the lead frame and the internal circuit of the semiconductor chip in the wire bonding process. In order to bond the wires, semiconductor chips, and leads exposed to the outside, damages caused by external force, corrosion, heat, etc., and to protect electrical characteristics and mechanical stability, in molding process with compound materials Package molding is carried out in a predetermined form.

패키지 성형이 완료된 자재는 몰딩시 발생하는 플래쉬(Flash)와 리드프레임의 리드와 리드사이에 형성한 댐바(Dambar)를 제거하는 트리밍(Trimming)공정을 거친 리드프레임 자재의 싱귤레이션영역을 컷팅시켜 리드프레임과 각 리드를 분리시킨 다음 각각의 도금과 크리닝과 마킹과 포밍을 거쳐 완성된 반도체패키지를 구할 수 있게 한 것이다.Package molding is completed by cutting the singulation area of the lead frame material that has been trimmed to remove the flash generated during molding and the dam bar formed between the lead and the lead of the lead frame. After separating the frame and each lead, each plating, cleaning, marking, and forming can be used to obtain a completed semiconductor package.

상기한 리드프레임은 단수개의 스트립상에 다수의 반도체패키지를 구할 수 있도록 다수부위에 탑재판이 타이바에 의해 리드프레임 상에 연결형성되고, 탑재판의 외부에는 다수의 리드가 소정간격을 유지한 채 형성되어 있다.The lead frame is formed by connecting the mounting plate on the lead frame by tie bars at a plurality of portions so that a plurality of semiconductor packages can be obtained on a single strip, and the plurality of leads are formed at a predetermined interval outside the mounting plate. It is.

이러한 리드프레임은 반도체 기술의 발달로 집적회로가 보다 많이 실장된 초소형의 반도체칩이 개발되고, 이에 초소형의 반도체칩을 부착되는 탑재판의 크기가 축소된 상태로 구비된다.Such a lead frame has been developed by the development of semiconductor technology to develop a miniature semiconductor chip in which more integrated circuits are mounted, and the size of the mounting plate to which the microminiature semiconductor chip is attached is provided in a reduced state.

따라서, 반도체칩의 회로를 외부로 출력시킬 수 있도록 확장된 집적회로에 대응하여 많은 수의 리드를 형성하였으나 한정된 면적에서 리드와 리드 사이의 피치 때문에 무한정 리드의 수를 늘릴 수 없었다.Therefore, although a large number of leads are formed in correspondence with the integrated circuit expanded to output the circuit of the semiconductor chip to the outside, the number of leads indefinitely cannot be increased due to the pitch between the leads and the leads in a limited area.

이와 같이된 종래의 리드프레임(LF)을 설명하면 제9도에서 보는 바와 같이 리드프레임(LF)의 다수부위 중앙에 탑재판(CD)이 형성되고, 탑재판(CD)의 4방향 모서리에는 각각 타이바(T1T4)가 리드프레임(LF)과 연결 형성된다.Referring to the conventional lead frame LF as described above, as shown in FIG. 9, a mounting plate CD is formed in the center of a plurality of portions of the lead frame LF, and each of the four direction edges of the mounting plate CD is formed. Tie Bar (T1) T4) is connected to the lead frame LF.

상기한 탑재판(CD)은 크기가 축소된 반도체칩(C)과 대응하여 면적(W)이 최소형으로 구비되고, 탑재판(CD)의 외부에 다수 구비된 각 리드(L)의 선단에 구비된 와이어본딩부(WB)는 피치간격(PG)을 유지하기 위해 탑재판(CD)의 외부에서 적정거리()를 유지한 상태로 형성되어 그 거리()가 상당히 크게 형성된다.The mounting plate CD is provided with the smallest area W in correspondence with the reduced size of the semiconductor chip C, and is provided at the tip of each lead L provided in the outside of the mounting plate CD. Wire bonding portion (WB) is a suitable distance from the outside of the mounting plate (CD) to maintain the pitch interval (PG) Is formed while maintaining the distance ( ) Is quite large.

이러한 리드프레임(LF)은 반도체패키지(10)의 제조공정으로 투입되어 다이어태치공정에서 탑재판(CD) 상부에 반도체칩(C)을 부착시키고, 와아이(W)를 연결시키며, 패키지성형공정에서 반도체칩(C)과 와이어(W)와 리드(L)의 패키지성형영역(PA)까지 컴파운드재를 충진공급시켜 소정형태의 패키지(P)를 성형시킨 후 제1도와 같이 완성된 반도체패키지(10)를 얻을 수 있게 한 것이다.The lead frame LF is introduced into the manufacturing process of the semiconductor package 10 to attach the semiconductor chip C to the upper portion of the mounting plate CD in the die attach process, and to connect the wafers W in the package forming process. After filling and supplying the compound material to the package forming region PA of the semiconductor chip C, the wire W, and the lead L, a predetermined shape of the package P is formed, and then the semiconductor package 10 as shown in FIG. ).

그러나, 패키지성형공정에서 패키지(P)가 성형될 때 제10도에서 보는 바와 같이 반도체칩(C)과 각 리드(L)사이에 연결본딩된 와이어(W)의 길이가 길게 형성되어 있어 일측의 타이바(T1)에서 공급되는 컴파운드재의 충진공급압력에 대하여 교차되는 타이바(T3)(T4)의 주변에 리드(L)에 연결된 와이어(W)가 컴파운드재의 흐름저항을 크게 받게 된다.However, when the package P is molded in the package forming process, as shown in FIG. 10, the length of the wire W connected and bonded between the semiconductor chip C and each lead L is long. The wire W connected to the lead L around the tie bars T3 and T4 intersecting with the filling supply pressure of the compound material supplied from the tie bar T1 receives a large flow resistance of the compound material.

따라서 각 와이어(W)의 변형이 심화되어 상호 접촉됨에 따라 숏트불량이 발생되어 패키지(P) 성형작업을 저하시켰고, 제품의 품질을 약화시키는 문제점이 있었다.Therefore, as the deformation of each wire (W) is intensified and contacted with each other, short defects occur, thereby reducing the package (P) molding work, and there is a problem of weakening the quality of the product.

또한 다른 실시예에 있어서는 BGA반도체패키지에 리드프레임(LF)으로 적용되는 PCB(SS)상부에 구비된 회로패턴(PC)이 탑재판(CD)과의 거리()가 일정한 상태를 유지하고, 있어 탑재판(CD)에 부착된 반도체칩(C)의 회로와 각 회로패턴(PC)의 와이어본딩부(WB)에 일정한 길이를 갖고 연결본딩된다.In another embodiment, the circuit pattern PC provided on the PCB SS applied to the BGA semiconductor package as the lead frame LF has a distance from the mounting plate CD. Is maintained in a constant state, and is bonded and bonded to the circuit of the semiconductor chip C attached to the mounting plate CD and the wire bonding portion WB of each circuit pattern PC.

이러한 PCB(SS)는 패키지(P) 성형시 컴파운드재가 공급되는 런너(R)측에서 교차되는 양측 방향의 리드(L)에 연결된 와이어(W)가 컴파운드재의 충진공급압력에 심하게 영향을 받게 제11도와 같이 와이어 스위핑(Wire Sweeping) 불량이 발생되어 패키지(P)의 성형작업성 저하와 제품의 품질을 약화시키는 문제점이 있었다.The PCB (SS) is the 11th wire (W) connected to the lead (L) in both directions intersecting at the runner (R) side where the compound material is supplied when forming the package (P) is severely affected by the filling supply pressure of the compound material As shown in the drawing, a poor wire sweeping problem occurs, thereby deteriorating the formability of the package P and reducing the quality of the product.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 발명한 것으로서, 보다 많은 집적회로를 가진 초소형의 반도체칩이 부착되는 리드프레임의 타이바 외부에 구비된 각 리드의 와이어본딩부가 패키지 성형시 컴파운드재가 공급되는 측의 일측의 타이바와 이 반대 방향의 타이바까지 소정의 타원형 형태의 영역을 형성하며 패키지의 성형시 발생하는 컴파운드재의 충진공급압력에 의한 와이어의 변형을 방지하여 숏트불량을 방지할 수 있게한 것을 목적으로 한다.The present invention has been invented to solve the conventional problems as described above, the compound of the wire bonding portion of each lead provided on the outside of the tie bar of the lead frame is attached to a small semiconductor chip having more integrated circuits It forms a region of a predetermined elliptical shape to the tie bar on one side of the supply side and the tie bar in the opposite direction, and prevents the short defect by preventing the deformation of the wire due to the filling supply pressure of the compound material generated during molding of the package. It is aimed at one thing.

제1도는 본 발명의 적용상태도.1 is an application state of the present invention.

제2도는 본 발명의 리드프레임 평면도.2 is a plan view of a leadframe of the present invention.

제3도는 본 발명의 A-A선 단면도.3 is a cross-sectional view taken along the line A-A of the present invention.

제4도는 본 발명의 B-B선 단면도.4 is a cross-sectional view taken along the line B-B of the present invention.

제5도는 본 발명의 리드프레임을 이용하여 패키지성형시의 작용상태도.5 is an operational state diagram during package molding using the lead frame of the present invention.

제6도는 본 발명의 반도체패키지중 리드프레임에 해당하는 BGA 반도체패키지에 적용된 PCB의 다른 실시예 평면도.Figure 6 is a plan view of another embodiment of a PCB applied to the BGA semiconductor package corresponding to the lead frame of the semiconductor package of the present invention.

제7도는 본 발명의 다른 실시예의 패키지성형시 작용상태도.Figure 7 is a state of action during package molding of another embodiment of the present invention.

제8도는 종래의 리드프레임 평면도.8 is a plan view of a conventional leadframe.

제9도는 종래의 패키지성형시의 작용상태도.9 is a state diagram of a conventional package molding.

제10도는 종래의 BGA 반도체패키지에 적용된 PCB의 패키지 성형시의 작용상태도.Figure 10 is a state diagram when the package of the PCB applied to the conventional BGA semiconductor package.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 반도체패키지 LF : 리드프레임10: semiconductor package LF: lead frame

CD : 탑재판 C : 반도체칩CD: Mounting Plate C: Semiconductor Chip

L : 리드 WB : 와이어본딩부L: Lead WB: Wire Bonding Part

A : 타원형 형태의 영역 W : 와이어A: oval shaped area W: wire

T1T4 : 타이바1,2 : 거리T1 T4: tie bar One, 2: distance

SS : PCB PC : 회로패턴SS: PCB PC: Circuit Pattern

이하 본 발명의 구성을 설명하면 다음과 같다.Hereinafter, the configuration of the present invention will be described.

반도체패키지(10)의 리드프레임(F)에 구비된 탑재판(CD)이 다수의 타이바에 연결되고, 탑재판(CD)외부에는 다수의 리드(L)가 형성된 것에 있어서, 상기 타이바중 패키지(P) 성형시 컴파운드재가 공급되는 측의 타이바(T1)와 이 반대측 타이바(T2)의 주변 리드(L)선단을 탑재판(CD)과의 거리(2)가 크게 유지된 상태로 구비되고, 상기 타이바(T1)의 교차부분에 구비된 타이바(T3)(T4)주변의 리드(L)의 선단은 탑재판(CD)과의 거리(2)를 짧게 유지시켜 리드(L)의 선단 전체 형상의 타원형 형상의 영역(A)을 갖도록 한 것이다.The mounting plate CD of the lead frame F of the semiconductor package 10 is connected to a plurality of tie bars, and a plurality of leads L are formed outside the mounting plate CD. (P) The distance between the tie bar T1 on the side where the compound material is supplied and the tip of the peripheral lead L on the opposite side of the tie bar T2 at the time of mounting plate CD. 2) is largely maintained, and the tip of the lead L around the tie bars T3 and T4 provided at the intersection of the tie bars T1 has a distance from the mounting plate CD. 2) is kept short so as to have an elliptical region A of the entire shape of the tip of the lead L. FIG.

이와 같이된 본 발명의 일 실시예를 첨부도에 의하여 상세히 설명하면 다음과 같다.When described in detail by the accompanying drawings an embodiment of the present invention as follows.

제1도는 발명의 리드프레임(LF)이 적용된 반도체패키지(10)의 구성도로서, 중앙에 탑재판(CD)과 이 양측에 다수의 리드(L)가 구비되고, 탑재판(CD)의 상부에는 에폭시(E)를 이용하여 반도체칩(C)을 부착시키며, 반도체칩(C)의 각 회로와 각 리드(L) 사이에는 쇄신으로 된 와이어(W)를 연결본딩시킨 것이다.1 is a configuration diagram of a semiconductor package 10 to which the lead frame LF of the present invention is applied, and a mounting plate CD is provided at the center and a plurality of leads L at both sides thereof, and an upper portion of the mounting plate CD is provided. The semiconductor chip C is attached to each other using epoxy (E), and a bonded wire W is connected between each circuit of the semiconductor chip C and each lead L.

제2도는 본 발명의 리드프레임(LF) 평면도로서, 1개의 리드프레임(LF) 스트립상에 다수의 반도체패키지(10)가 구해지도록 다수부위의 중앙에 탑재판(CD)을 형성하고, 탑재판(CD)의 4방향 모서리에는 리드프레임(LF)에 연결된 타이바를 형성한다.FIG. 2 is a plan view of a lead frame LF of the present invention, wherein a mounting plate CD is formed at the center of a plurality of portions so that a plurality of semiconductor packages 10 are obtained on one strip of lead frame LF. Tie bars connected to the lead frame LF are formed at four corners of the CD.

상기 탑재판(CD)은 반도체 기술의 발달에 의해 소형화된 반도체칩(C) 내부에 고집적화된 회로가 보다 많이 확장됨에 따라 초소형의 반도체칩(C)이 부착되는 탑재판(CD)의 면적(W)을 소형화시킨 상태로 형성하고, 소형화된 탑재판(CD)의 외부에는 제한된 면적에서 반도체칩(C)의 회로에 대응하는 개수로 다수의 리드(L)를 형성한다.The mounting plate CD has an area W of the mounting plate CD to which the microminiature semiconductor chip C is attached as the integrated circuit is further expanded in the miniaturized semiconductor chip C due to the development of semiconductor technology. ) Is formed in a miniaturized state, and a plurality of leads L are formed outside the miniaturized mounting plate CD in a number corresponding to the circuit of the semiconductor chip C in a limited area.

상기한 리드(L)는 리드프레임(LF)의 한정된 면적에 많은 수를 갖도록 하기 위해 리드(L)를 리드(L) 사이의 피치간격(PG)을 적정하게 확보되도록 형성하므로서 반도체칩(C)과 각 리드(L)사이의 거리가 크게 유지된다.In order to have a large number in the limited area of the lead frame LF, the lead L is formed such that the lead L is formed to appropriately secure the pitch gap PG between the leads L, and thus the semiconductor chip C. And the distance between each lead L are kept large.

또한 상기 리드(L)는 반도체패키지(10)의 제조공정중 반도체칩(C)의 각 회로와 각 리드(L) 사이에의 거리에 연결된 와이어(W)의 길이가 길게 형성됨에 따라 패키지(P)성형시 컴파운드재의 공급에 따른 충진공급압력에 의해 각 와이어(W)의 저항이 감소되도록 컴파운드재가 공급되는 측의 타이바(T1)와 이 반대측의 타이바(T2)측으로 거리가 기게 유지되는 타원형 형태의 영역(A)에 리드(L)의 와이어본딩부(WB)를 구비한 것이다.In addition, the lead (L) is a package (P) as the length of the wire (W) connected to the distance between each circuit of the semiconductor chip (C) and each lead (L) during the manufacturing process of the semiconductor package 10 is formed long. The oval that maintains the distance to the tie bar T1 on the side where the compound material is supplied and the tie bar T2 on the opposite side so that the resistance of each wire W is reduced by the filling supply pressure according to the supply of the compound material during molding. The wire bonding part WB of the lead L is provided in the area | region A of a form.

즉, 탑재판(CD) 중앙의 포인트(PT)를 중심으로 캄파운드재가 공급되는 측의 타이바(T1)에 위차한 리드(L)와 이 반대측의 타이바(T2)에 위치한 리드의 와이어본딩부(WB)는 탑재판(CD)과의 거리(1)를 크게 유지하고, 이 타이바(T1)(T2)이외의 부분의 양측에 교차되는 방향으로 구비된 타이바(T3)(T4)측의 리드(L)에 형성된 와이어본딩부(WB)의 거리(2)를 짧게 형성하여 리드(L)의 와이어본딩부(WB)가 타원형상의 영역(A)을 갖도록 한 것이다.That is, the wire bonding of the lead L located on the tie bar T1 on the side where the camping material is supplied centering on the point PT in the center of the mounting plate CD and the lead located on the tie bar T2 on the opposite side The part WB is a distance from the mounting plate CD 1) is kept large, and the wire bonding part WB formed in the lead L on the side of the tie bars T3 and T4 provided in the direction intersecting both sides of the parts other than the tie bars T1 and T2. Distance ( 2) is formed short so that the wire bonding portion WB of the lead L has an elliptical region A.

이러한 리드프레임(LF)은 반도체패키지(10) 제조공정중 탑재판(CD) 상부에 반도체칩(C)을 부착시키고, 반도체칩(C) 상부의 각 회로와 각 리드의와이어본딩부(WB) 상부 사이에 와이어(W)를 연결본딩 한다.The lead frame LF attaches the semiconductor chip C to the upper portion of the mounting plate CD during the manufacturing process of the semiconductor package 10, and wires WB of each circuit and each lead on the semiconductor chip C. Bond the wire (W) between the top.

이때 본딩된 와이어(W)는 컴파운재가 공급되는 측의 타이바(T1)와 이 반대편의 타이바(T2) 측의 리드(L)인 와이어본딩부(WB)에 연결된 부분이 길게 형성되고, 상기 타이바(T1)(T2)에 연결된 와이어(W)는 짧게 형성됨에 따라 상기 리드프레임(LF)을 패키지성형공정으로 투입시켜 컴파운드재의 공급에 의한 반도체칩(C)를 성형시키면 제5도와 같이 타이바(T1)측에서부터 이 반대방향의 타이바(T2)까지 컴파운드재가 충진된다.In this case, the bonded wire W is formed to have a long portion connected to the tie bar T1 on the side to which the compound material is supplied and the wire bonding part WB which is the lead L on the side of the tie bar T2 on the opposite side. As the wires W connected to the tie bars T1 and T2 are shortened, the lead frame LF is introduced into a package molding process to form the semiconductor chip C by supplying a compound material, as shown in FIG. 5. The compound material is filled from the tie bar T1 side to the tie bar T2 in the opposite direction.

이때 공급되는 컴파운드재는 소정의 공급압력을 가짐에 따라 이 공급압력이 타이바(T1)에서 교차되는 방향의 타이바(T3)(T4)의 주연에 구비된 리드(L)의 와이어본딩부(WB)에 연결된 와이어(W)가 가장 심한 공급압력을 받게 된다.At this time, as the compound material to be supplied has a predetermined supply pressure, the wire bonding portion WB of the lead L provided at the periphery of the tie bars T3 and T4 in the direction in which the supply pressure crosses the tie bars T1. ), The wire (W) connected to is subjected to the most severe supply pressure.

그러나, 상기 부분의 각 와이어본딩부(WB)에 연결된 와이어(W)는 반도체칩(CD)과의 사이의 거리(2)가 짧게 유지됨에 따라 컴파운드재의 충진공급압력에 대한 견고성이 유지되어 와이어(W)의 변 방지에 관한 와이어 스위핑 불량이 방지된다.However, the wires W connected to the respective wire bonding portions WB of the portion have a distance (a distance between the semiconductor chips CD). As 2) is kept short, the firmness to the filling supply pressure of the compound material is maintained to prevent the wire sweeping defect related to the change of the wire W.

이와 같이된 본 발명의 다른 실시예에 있어서는 제7도 및 제8도에서 보는 바와 같이 PCB(SS)가 작용되는 BGA반도체패키지의 PCB(SS)에 형성된 회로패턴(PC)의 와이어본딩부(WB)를 컴파운드재가 공급되는 런너(R)측으로 부터 이 반대측으로 거리가 긴 타원형 형태의 영역을 갖도록 형성하여 컴파운드재의 공급으로 패키지(P)성형시 사이와 같은 작용을 가짐으로서 와이어 스위핑을 방지할 수 있게 한 것이다.In another embodiment of the present invention as described above, as shown in FIGS. 7 and 8, the wire bonding portion WB of the circuit pattern PC formed on the PCB SS of the BGA semiconductor package on which the PCB SS is actuated. ) Is formed to have an elliptical region with a long distance from the runner (R) side to which the compound material is supplied, to the opposite side, so that the wire sweeping can be prevented by having the same action as when the package (P) is formed by supplying the compound material. It is.

이상에서와 같이 본 발명은 보다 많은 집적회로를 가진 초소형의 반도체칩이 부착되는 리드프레임의 타이바 외부에 구비된 각 리드의 와이어본딩부가 패키지 성형시 컴파운드재가 공급되는 측의 일측의 타이바와 이 반대 방향의 타이바까지 소정의 타원형 형태의 영역을 형성하며 패키지성형시 컴파운드재의 충진공급압력에 의한 와이어 스위핑 불량과 숏팅불량을 방지하여 제품의 품질신뢰도를 높이고, 패키지성형 작업을 용이하게 할 수 있는 효과가 있다.As described above, in the present invention, the wire bonding portion of each lead provided on the outside of the tie bar of the lead frame to which the microminiature semiconductor chip having more integrated circuits is attached is opposite to the tie bar on the side of the side where the compound material is supplied during package molding. Forms a predetermined oval shape area up to the tie bar in the direction, and prevents the wire sweeping defect and the shorting defect caused by the filling supply pressure of the compound material during package molding, thereby improving the quality reliability of the product and facilitating the package molding operation. There is.

Claims (3)

반도체패키지(10)의 리드프레임(F)에 구비된 탑재판(CD)이 다수의 타이바에 연결되고, 탑재판(CD)외부에는 다수의 리드(L)가 형성된 것에 있어서, 상기 타이바중 패키지(P)성형시 컴파운드재가 공급되는 측의 타이바(T1)와 이 반대측 타이바(T2)의 주변 리드(L) 선단을 탑재판(CD)과의 거리(2)가 크게 유지된 상태로 구비되고, 상기 타이바(T1)의 교차부분에 구비된 타이바(T3)(T4)주변의 리드(L)의 선단은 탑재판(CD)과의 거리(2)를 짧게 유지시켜 리드(L)의 선단 전체 형상이 타원형 형상의 영역(A)을 갖도록 한 것을 특징으로 하는 반도체패키지용 리드프레임.The mounting plate CD of the lead frame F of the semiconductor package 10 is connected to a plurality of tie bars, and a plurality of leads L are formed outside the mounting plate CD. (P) The distance between the tie bar T1 on the side to which the compound material is supplied and the tip of the peripheral lead L of the opposite tie bar T2 on the mounting plate CD ( 2) is largely maintained, and the tip of the lead L around the tie bars T3 and T4 provided at the intersection of the tie bars T1 has a distance from the mounting plate CD. 2) The short frame is a semiconductor package lead frame characterized in that the entire shape of the front end of the lead (L) has an elliptical region (A). 제1항에 있어서, 상기 반도체패키지(P)는 PCB(SS)가 적용된 BGA 반도체패키지의 PCB(SS)에 형성된 회로패턴(PC) 선단이 타원형 형태의 영역(A)를 갖도록 한 것을 특징으로 하는 반도체패키지용 리드프레임.The method of claim 1, wherein the semiconductor package (P) is characterized in that the front end of the circuit pattern (PC) formed on the PCB (SS) of the BGA semiconductor package to which the PCB (SS) is applied to have an elliptical region (A). Lead frame for semiconductor package. 제1항에 또는 제2항중 어느 한 항에 있어서, 상기 타원형 형태의 영역(A)은 리드(L)의 선단에 형성된 와이어본딩부(WB)에 구비한 것을 특징으로 하는 반도체패키지용 리드프레임.The lead frame for a semiconductor package according to any one of claims 1 to 3, wherein the elliptical region (A) is provided in a wire bonding portion (WB) formed at the tip of the lead (L).
KR1019960077919A 1996-12-30 1996-12-30 Lead frame KR100199829B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019960077919A KR100199829B1 (en) 1996-12-30 1996-12-30 Lead frame
JP9368625A JP3047174B2 (en) 1996-12-30 1997-12-29 Wiring board for mounting electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960077919A KR100199829B1 (en) 1996-12-30 1996-12-30 Lead frame

Publications (2)

Publication Number Publication Date
KR19980058591A KR19980058591A (en) 1998-10-07
KR100199829B1 true KR100199829B1 (en) 1999-06-15

Family

ID=19492728

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960077919A KR100199829B1 (en) 1996-12-30 1996-12-30 Lead frame

Country Status (2)

Country Link
JP (1) JP3047174B2 (en)
KR (1) KR100199829B1 (en)

Also Published As

Publication number Publication date
JPH113962A (en) 1999-01-06
JP3047174B2 (en) 2000-05-29
KR19980058591A (en) 1998-10-07

Similar Documents

Publication Publication Date Title
US7439097B2 (en) Taped lead frames and methods of making and using the same in semiconductor packaging
KR940007757Y1 (en) Semiconductor package
US9806035B2 (en) Semiconductor device
US7410835B2 (en) Method for fabricating semiconductor package with short-prevented lead frame
KR20050118665A (en) Semiconductor packaging with a partially prepatterned lead frame and method of manufacturing the same
JP2006344827A (en) Method for manufacturing semiconductor device
US20220199500A1 (en) Method of manufacturing semiconductor devices, component for use therein and corresponding semiconductor device
KR100199829B1 (en) Lead frame
JP3179003B2 (en) Apparatus and method for forming ultra-thin semiconductor package such as TSOP or UTSOP
KR20020093250A (en) ELP type leadframe and ELP using the same
KR200276092Y1 (en) Paddle cutting press device for leadframe
JP4477976B2 (en) Manufacturing method of semiconductor device
KR100290783B1 (en) Semiconductor package
KR100575859B1 (en) ball grid array package
KR970006222Y1 (en) Lead frame
JP2005135938A (en) Semiconductor device and its manufacturing method
JP2000049275A (en) Lead frame, semiconductor device and manufacture thereof
KR200141125Y1 (en) Structure of lead frame
JP2004200719A (en) Semiconductor device
EP1447847A2 (en) Lead frame for an electronic component package
KR19980058590A (en) Semiconductor Package
KR20020009885A (en) Leadframe for semiconductor package
KR19980020499A (en) Semiconductor Chip Package Using Flat Lead Frame
JP2005236127A (en) Semiconductor device and manufacturing method thereof
KR20020030174A (en) structure of lead frame for fabrication of semiconductor

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130306

Year of fee payment: 15

FPAY Annual fee payment

Payment date: 20140303

Year of fee payment: 16

FPAY Annual fee payment

Payment date: 20150303

Year of fee payment: 17

LAPS Lapse due to unpaid annual fee