KR100188209B1 - Image correction data loading method by using frame memory of projector - Google Patents

Abstract

According to the present invention, an image correction data storage for temporarily storing image correction data for error correction of each pixel constituting a screen is constituted by a frame memory that does not require addressing through an address line so that efficient image correction data can be processed. An image correction data loading / outputting method using a frame memory of a projection type image display system is provided.

Accordingly, in the present invention, the image correction data for correcting the pixel error of the image signal constituting the screen is stored in the image correction data storage section 42 and temporarily stored in the image correction data storage section 44. An image correction apparatus of a projection type image display system which performs pixel correction by data; When the initial power is turned on, the image correction data storage section 42 is enabled to read the image correction data specified by the address AD, and the image correction data storage section 44 is also reset. A first step of loading and storing the image correction data read by input enable (IE) and write enable (WE) using a color subcarrier (3.58 MHz) as a light clock (SWCK); When storing of the image correction data is completed by the image correction data storage unit 44, a system clock is used as the read clock SRCK to read-set the image correction data RSTR in units of frames and output enable (OE). And a second step of outputting the image correction data stored by the operation and the lead enable RE operation.

Description

Image Correction Data Loading / Output Method Using Frame Memory of Projection Image Display System

The present invention relates to a method of loading / outputting image correction data using a frame memory of a projection image display system. More particularly, the present invention relates to a projection type including a plurality of AMA (Actuated Mirror Array) members corresponding to each pixel constituting a screen. In the image display system, frame memory (FM) is used to load / output image correction data, which is used for loading / outputting image correction data to correct errors caused by the AMA member. An image correction data loading / outputting method using a frame memory of a projection type image display system that enables this.

Recently, the development of a projection type image display device employing an AMA member and a device has been promoted for practical use, and the device employing such an AMA member has a large number of pixel driving devices provided on a screen of 640 * 480 dimension, for example. For example, a plurality of pixel driving elements formed of, for example, MOS transistors corresponding to the number of pixels are formed in an active matrix substrate arranged in the form of a matrix array and a number corresponding to a plurality of pixels on the active matrix substrate, respectively. The actuator is inclinedly modified in accordance with the image signal voltage applied from the element to modulate incident light.

According to the projection type image display apparatus employing such an AMA member, the active matrix substrate is employed as the AMA member so that a plurality of pixel driving elements are arranged in a matrix array corresponding to the total number of pixels constituting the screen.

Accordingly, in order to reproduce an image by tilting the actuator corresponding to each pixel driver in response to the image signal voltage, the pixel driver provided in the AMA panel is formed in a matrix array form based on the image signal voltage corresponding to each pixel. A row / column driver circuit portion is provided for driving the pixel driver for driving odd pixels and even pixels in the row / column direction of the AMA panel to control the pixel driver of the pixel.

In addition, when driving the pixel driving element set in the AMA panel by the row / column driving circuit part, the pixel due to the tolerance or unevenness of the flatness accompanying the manufacture of the actuator formed on the AMA panel In order to exclude the unevenness of driving, correction data for fundamental errors in manufacturing including the overall flatness of the actuator formed on the corresponding AMA panel is calculated and added (or subtracted) to the image signal voltage when driving the AMA panel. It is provided in the row / column drive circuit section in such a manner that correction for fundamental errors in manufacturing the AMA panel is performed.

FIG. 1 is a block diagram showing an image correction apparatus of a general projection type image display system, in which reference numeral 20 denotes an image signal (Vin) to be reproduced by performing optical modulation by the AMA panel 10 constituting the projection type image display apparatus. ) Is a data conversion unit composed of an analog-digital converter for converting the R / G / B color signal into digital data when R / G / B is decoded and applied thereto, and 22 denotes a horizontal synchronous signal ( Hsync) and vertical sync signal (Vsync) and color subcarrier (fsc; approximately 3.58 MHz) to separate the synchronous separation / PLL circuit.

Reference numeral 24 denotes a combination of the vertical synchronization signal Vsync separated from the synchronization separation / PLL circuit section 22, the horizontal synchronization signal Hsync, and the clock signal CLK (4fsc) (fsc is the color subcarrier frequency). An address / control signal generator for generating an address signal and a control signal, wherein the address / control signal generator 24 synchronizes the clock signal CLK in synchronization with the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync. By dividing, the address and the control signal for driving the pixels are generated. For example, assuming a screen of 640 x 480, the total number of pixels on the screen is 307,200, and the addresses required for driving the pixels on the whole are 20 to 218.

In addition, the address / control signal generator 24 combines the horizontal synchronous signal Hsync and the vertical synchronous signal Vsync separated by the synchronous separation / PLL circuit unit 22, as known in the art. The clock signal CLK is divided miraculously to generate an address for pixel driving.

Reference numeral 26 denotes a non-volatile semiconductor memory (ROM) in which an error correction value for the flatness of each actuator provided correspondingly to the pixel driving elements constituting the AMA panel 10 is stored as image correction data. The image correction data storage section shows that the image correction data stored in the image correction data storage section 26 is used to correct the image correction data for correcting the error of the flatness during manufacturing previously measured by the AMA panel 10. The data is calculated, created into a ROM table, and correction data for a corresponding pixel is sequentially output based on an address and a control signal output from the address / control signal generation section 24.

Further, reference numeral 28 denotes that the read image correction data is read when the correction data in the pixel unit corresponding to the address generated by the address / control signal generation section 24 is read from the image correction data storage section 26. An image correction data storage portion constituted of an SRAM which is temporarily stored in response to a control signal provided from the address / control signal generation portion 24 and then output again.

Reference numeral 30 denotes the image data digitally converted by the data conversion unit 20 constituted by the analog-digital converter and the image correction data provided through the image correction data storage unit 28 corresponding to the image data. An image correction circuit section for outputting pixel drive data corrected by applying the image correction data to each pixel in correspondence with a matching method, and 32 denotes the address / control of the image data corrected by the image correction circuit section 30. A field memory which receives / stores the signals based on the control signal generated by the signal generator 24 and sequentially outputs them is shown.

Further, reference numeral 34 denotes a data inverse converting section constituted of a digital-analog converter for digitally-analog converting image correction data sequentially output from the field memory 32 under the control of the address / control signal generator 24.

Further, reference numeral 36 denotes a row driving circuit unit for driving the pixel unit actuator provided in the AMA panel 10 based on the image data analog-converted by the data inverse conversion unit 34 with respect to the AMA panel 10. 38 denotes a pixel driving element of the AMA panel 10 in pixel-alignment with the row driving circuit section 36 based on an address provided to the AMA panel 10 by the address / control signal generation section 24. Denotes a column driving circuit portion for tilting the corresponding actuator respectively.

Here, the image correction data processing method of the projection type image display apparatus will be described with reference to FIG. 2, in which the main portion to which the image correction data loading / output control circuit is applied is shown, where the image signal Vin to be reproduced is synchronized / PLL. The clock signal CLK (4fsc) obtained by synchronizing separation by the circuit section 22 converts the data into digital data in the data conversion section 20 and applies it to the image correction circuit section 30. In this state, the address / control signal The generation unit 24 generates an address and a control signal (write RD, read WE, chip enable CE, etc.) for reading the correction data of all pixels, and generates an image from the image correction data storage unit 26. The image correction data is loaded into the correction data storage unit 28 and then controlled to be output to the image correction circuit unit 30.

That is, the pixel correction data storage unit 26 transfers image correction data in pixel units having positions corresponding to addresses sequentially provided from the address / control signal generation unit 24 to the image correction data storage unit 28. The image correction data storage section 28 temporarily stores the image correction data based on the control signal provided from the address / control signal generation section 24, and then sequentially corrects the image correction circuit section 30. ) Is applied.

Accordingly, the image correction circuit unit 30 matches the image correction data provided from the image correction data storage unit 28 with respect to the digitally converted image signal in units of pixels, and corrects the pixel drive data corrected for the clock signal CLK. Is applied to the data inverse converting section 34 via the field memory 32 controlled by the same. The data inverse converting section 34 controls the clock signal CLK under the control of the address / control signal generating section 24. And converts the pixel drive data into analogues and then provides them to the row drive circuit section 36.

In this state, the column driver circuit section 38 designates the pixel driver in the column direction based on the address for pixel driving applied from the address / control signal generation section 24, and the designated pixel driver element. In response to the pixel driving data applied by the row driving circuit section 36 to incline and drive the actuator to reflect the light incident on the AMA panel 10 and to project it onto the screen through a projection lens (not shown). do.

On the other hand, according to the image correction data processing method of the projection type image display apparatus, when the projection type image display apparatus is in the operating state (ON), the address and control signal generated by the address / control signal generation section 24 during the system initialization period are applied. By this, the image correction data stored in the image correction data storage 26 is loaded into the image correction data storage 28.

However, when the image correction data is loaded, the address / control signal generator 24 combines the horizontal synchronous signal Hsync and the vertical synchronous signal Vsync to synchronize the clock signal CLK synchronously with the combined result. The pixel correction data from the image correction data storage unit 26 is generated by allowing the image correction data storage unit 26 and the image correction data storage unit 28 to continuously generate an address having, for example, 19 bits. Is to be transmitted to the image correction data storage unit 28 composed of SRAM, so that, for example, a 19-bit address line continuously generated for loading the image correction data is stored in the image correction data storage unit 28 composed of SRAM. There is a disadvantage that the circuit pattern of the component to be provided is complicated, and the frequency of digital noise increase.

Accordingly, the present invention has been made in view of the above-described circumstances, and an image correction data storage for temporarily storing image correction data for error correction of each pixel constituting a screen is used as a frame memory that does not require addressing through an address line. It is an object of the present invention to provide a method for loading / outputting image correction data using a frame memory of a projection type image display system that is configured to enable efficient processing of image correction data.

According to the image correction data loading / output method using the frame memory of the projection-type image display system according to the present invention, the image correction data for correcting the pixel error of the image signal constituting the screen is achieved. An image correction apparatus of a projection type image display system, which is stored in a storage unit and performs pixel correction by the image correction data through temporary storage in an image correction data storage unit; The image correction data storage unit is enabled when the initial power supply is turned on to read the image correction data specified by the address, and the image correction data storage unit is reset, and the color subcarrier is used as the light clock. A first step of loading and storing the image correction data read by the enable and write enable, and using the system clock as a lead clock when the image correction data is stored in the image correction data storage unit. A method of loading / outputting image correction data using a frame memory of a projection type image display system comprising a second step of resetting data in units of frames and outputting image correction data stored by an output enable operation and a lead enable operation. to provide.

Preferably, in the first and second steps, the image correction data is loaded / output by a frame memory constituting the image correction data storage.

According to the present invention configured as described above, in the case of correcting a pixel error with respect to an image signal constituting a screen in a projection type image display apparatus, for example, image correction data from an image correction data storage section made of ROM is directed to the correction circuit side. By employing a data storage for loading / outputting as a frame memory that does not require an address line, it is possible to reduce the generation of digital noise while simplifying the circuit pattern of the component.

1 is a block diagram showing an image correction apparatus of a general projection image display system;

FIG. 2 is a view showing a main part to which an image correction data loading / output control circuit is applied in the image correction apparatus shown in FIG. 1;

Fig. 3 is a block diagram showing the main parts of a method for loading / outputting image correction data using a frame memory of a projection image display system according to the present invention;

4A is a timing chart for explaining an operation of loading image correction data at initial power supply 0b on 0c according to a preferred embodiment of the present invention;

4B is a timing chart for explaining the output operation of the loaded image correction data according to the preferred embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

20 --- data converter, 22 --- sync / PLL circuit,

24 --- address / control signal generator, 26,42 --- image correction data storage,

28,44 --- Image correction data storage unit, 30,46 --- Image correction circuit unit,

32 --- field memory, 34 --- data inverse converter,

36 --- row drive circuitry, 38 --- thermal drive circuitry,

40 --- control unit.

Hereinafter, the present invention configured as described above will be described in detail with reference to the accompanying drawings.

That is, Fig. 3 is a block diagram showing the main part of the method for loading / outputting image correction data using the frame memory of the projection type image display system according to the present invention. A control unit for controlling the data processing of the image correction data for error correction for the control unit, wherein the control unit 40 is the image correction data described later by an address generated by the combination of the vertical / horizontal synchronization signal and the color subcarrier. The image correction data from the storage unit 42 is specified and outputted.

In addition, the control unit 40 generates and resets the reset write control signal RSTW in the image correction data storage unit 44, which will be described later, and uses a clock of 3.58 MHz as a serial write clock (SWCK). Input enable control signal (IE) and write enable control so that the image correction data output during the eighth count of the vertical synchronization signal can be loaded and stored in the image correction data storage section 44 composed of a frame memory to be described later. When the signal WE is generated and the loading state of the image correction data is finished, the reset control signal RSTR is generated and reset, and the internal system clock is used as the serial read clock (SRCK). The image correction data can be output by generating the output enable control signal OE and the lead enable control signal RE.

Further, reference numeral 42 denotes an image composed of, for example, a ROM in which an error correction value for the flatness of an actuator provided corresponding to a plurality of pixel driving elements forming an AMA panel is stored as image correction data that is measured and calculated in advance at the time of its manufacture. As the correction data storage unit, the image correction data storage unit 42 is designated by the address AD of, for example, 19 bits from the control unit 40, and the image correction data is stored by the read enable control signal RE. Poisoning becomes possible.

Further, reference numeral 44 denotes a frame memory that does not require an address line, and is reset by being supplied with a reset write control signal RSTW while the image correction data from the image correction data storage section 42 is loaded. The serial light clock (SWCK) is supplied from (40), the input enable control signal (IE) and the write enable control signal (WE) are input, the image correction data is loaded and stored, and the reset is completed when the loading is completed. The output enable control signal OE and the lead enable control signal RE are received while the control signal RSTR is reset and supplied with the serial lead clock SRCK from the controller 40. An image correction data storage portion which enables the stored image correction data to be output.

Further, reference numeral 46 denotes an image correction circuit section for generating the pixel drive data corrected by applying the image correction data to each pixel by matching the image correction data with the image data constituting the screen. Indicates.

Next, the operation of the present invention made as described above will be described in detail with reference to the timing charts of FIGS. 4A and 4B.

First, the loading operation of the image correction data in the state where the initial power is turned on will be described with reference to FIG. 4A.

That is, when the initial power is turned on while the power key installed in the remote controller or the control panel is operated by the user, the controller 40 supplies the lead enable control signal RE to the image correction data storage 42 to provide an image. The read operation of the correction data is enabled, for example, by the address generation period for 307200 pixels in a 640 * 480 size screen, and the vertical synchronization signal and the horizontal synchronization signal according to the image signal constituting the screen are displayed. In combination, for example, by generating an address of 19 bits, the image correction data from the image correction data storage section 42 is output.

In this case, the control unit 40 supplies a color subcarrier of 3.58 MHz to the image correction data storage unit 44 using a serial light clock (SWCK), and also enables an input enable control signal (IE) and light enable. The control signal WE is generated to start loading of the image correction data, while the image correction data is loaded during eight counts of the vertical synchronization signal according to the image data.

Then, when loading of the image correction data is completed, as shown in FIG. 4B, the controller 40 supplies an internal system clock as a serial lead clock SRCK and the image correction data storage unit. The reset lead control signal RSTR is supplied to 44 to reset the reset lead control signal RSTR so that the reset lead control signal RSTR is repeatedly generated for each frame period of the image correction data. OE) and the lead enable control signal RE are generated so that the image correction data loaded and stored are output so that the image correction circuit 46 can be supplied for pixel correction of the image data constituting the screen.

According to the above-described present invention, in the case of loading image correction data for correcting pixel error of an image signal constituting a screen in a projection type image display apparatus, an image correction data storage for temporarily storing the image correction data Can be used as a loading / output means for loading image correction data by constructing a frame memory that does not require an address line, so that the address line is reduced compared to an image correction data storage including an SRAM requiring a conventional address line. Not only is this simpler, it also has the advantage that the likelihood of digital noise is offset.

Claims (2)

Image correction data for correcting the pixel error of the image signal constituting the screen is stored in the image correction data storage section 42, and pixel correction by the image correction data through temporary storage to the image correction data storage section 44. In the image correction apparatus of a projection type image display system, When the initial power is turned on, the image correction data storage section 42 is enabled to read the image correction data specified by the address AD, and the image correction data storage section 44 is also reset. A first step of loading and storing the image correction data read by input enable (IE) and write enable (WE) using a color subcarrier (3.58 MHz) as a light clock (SWCK); When storing of the image correction data is completed by the image correction data storage unit 44, a system clock is used as the read clock SRCK to read-set the image correction data RSTR in units of frames and output enable (OE). And a second step of outputting image correction data stored by the operation and the lead-enable (RE) operation. The projection type image display according to claim 1, wherein the image correction data is loaded / outputted by a frame memory constituting the image correction data storage section 44 in the first and second steps. Image correction data loading / output method using frame memory of system.