KR100227105B1 - Plxel correction data loading apparatus for projector - Google Patents

Abstract

The present invention provides an accurate and increased loading speed by allowing the image correction data for the input image signal to be separately loaded and output for each of the radix line / excellent line in the projector employing the AMA member. Provided is a calibration data loading device.

Accordingly, the present invention provides a synchronization counting means (10, 12) for generating a counting output as a result of separating and counting the synchronization signal included in the input video signal, and the synchronization counting means (10,

Of image correction data for the input video signal based on the counting output from

Address (ADD1, ADD2) for loading output, write enable signals (WE1, WE2) and read enable signal (RE1, RE2) are generated per odd / excellent line, and images according to the odd / excellent line Control means 14 for generating a select control signal SEL for causing correction data to be applied to the pixel correction unit 28, and the operation is enabled by the control means 14 to address

Operation is enabled by the cardinal correction data storage means 16 and the control means 14 for reading out and outputting the image correction data allocated as the odd line in accordance with ADD1.

The odd correction data storage means 18 which reads and outputs the image correction data allocated as the even line according to ADD2, and is enabled by the write enable signal WE1 from the control means 14. The image correction data from the data storage means 16 is recorded and stored at a recording speed synchronized with the recording clock W CLK, and the read enable signal

A first data storage means 20 for reading out image correction data enabled and stored by RE1 at a read speed synchronized with the read clock R CLK, and a write enable signal from the control means 14 Enabled by WE2), the image correction data from the excellent correction data storage means 18 is recorded and stored at a recording speed synchronized with the recording clock W CLK, and enabled by the read enable signal RE2. Second data storage means 22 for reading out the stored image correction data at a read speed synchronized with the read clock R CLK, and the control means.

By the select control signal SEL from 14, image correction data according to the odd / excellent line from the first data storage means 20 and the second data storage means 22 is selectively It is characterized by comprising a data switch means 24 for performing the switching to apply to).

Description

Image correction data loading device of the projector {PLXEL CORRECTION DATA LOADING APPARATUS FOR PROJECTOR}

The present invention relates to a device for loading an image correction data of a projector. More particularly, in a projector for forming a projection type image using an AMA member, correction data for correcting a manufacturing error of the AMA member includes a radix line for an input image signal. The present invention relates to an image correction data loading apparatus for a projector that can be separately loaded for (Odd Line) and Even Line (Even Line).

Recently, a projector as a projection image display device employing an AMA member or device has been proposed and put into practical use. The AMA device has a number of pixels for driving a plurality of pixels provided on a screen of 640 x 480 dimension, for example. For example, a plurality of pixel driver elements composed of, for example, MOS transistors are formed in an active matrix substrate arranged in a matrix array form, and corresponding image pixels are formed on the active matrix substrate so as to correspond to each pixel. It is comprised by the actuator which inclines-deforms and modulates incident light (namely, optical path adjustment).

Assuming a screen of, for example, 640 × 480, such an AMA panel is provided with a plurality of pixel driving elements arranged in a matrix array corresponding to the total number of pixels constituting the screen.

Therefore, in order to reproduce an image by tilting the actuator corresponding to each pixel driver in response to the image signal voltage, the pixel driver provided in the AMA panel is formed in the form of a matrix array based on the image signal voltage corresponding to each pixel. In order to control the pixel driver, a row / column driver circuit is provided for driving the pixel driver to drive odd pixels and even pixels in the row / column direction of the AMA panel.

At this time, in the case of driving the pixel driving element set in the AMA panel by the row / column driving circuit section, the tolerance or unevenness of the flatness accompanying the manufacturing of the actuator formed on the AMA panel is caused. In order to reduce the nonuniformity of the pixel driving, a pixel correction device is added to allow correction data for a fundamental error at the time of manufacture including the overall flatness of an actuator formed on the corresponding AMA panel to be calculated and stored. (C) adding (or subtracting) the pre-calculated correction data to the image signal voltage by the image signal when the AMA panel is driven in a state in which a predetermined image signal is to be realized as a projection type image, and providing it to the row / column driving circuit unit. As a result, correction for the original error in manufacturing the AMA panel is performed.

According to the pixel correction device in such a projector, for example, when the image correction data for each pixel constituting the screen of 640 x 480 dimension is stored in the correction data memory in the form of ROM, the horizontal / The image correction data is read out by an address generated in synchronization with the vertical synchronization signal H SYNC / V SYNC and the color subcarrier frequency signal FSC, and temporarily stored in a correction data storage unit made of SRAM, and then a plurality of logics. The pixel correction means comprising a gate adds (subtracts) to the input video signal and outputs it as an image driving signal, thereby correcting an error on the AMA panel.

However, in the pixel correction apparatus of such a projector, an address based on the vertical / horizontal synchronization signal and the color subcarrier frequency signal of the input image signal is stored in a ROM type correction data memory in which the image correction data is stored when the pixel correction is performed on the input image signal. Since the image correction data can be read by applying a digital signal to the image correction data, the possibility of digital noise not only remains due to the address based on the vertical / horizontal synchronization signal and the color subcarrier frequency signal. The disadvantage is that the loading speed is slow.

Accordingly, the present invention has been made in view of the above circumstances, and is corrected and increased by allowing image correction data for an input image signal to be separately loaded and output for each odd number line / excellent line in a projector employing an AMA member. It is an object of the present invention to provide an image correction data loading apparatus of a projector that can have a predetermined loading speed.

According to the image correction data loading apparatus of the projector according to the present invention to achieve the above object, the image correction data and pixel per pixel for the error correction for the AMA member on the AMA device is converted into the input image signal digitally converted by the data conversion unit A pixel correction apparatus of a projector having a pixel correction unit for matching an analog signal to an analog conversion through a data inverse conversion unit and outputting the same as an image driving signal to an AMA device, the counting result of separating and counting a synchronization signal included in the input image signal An odd number / excellent line for outputting an address, a write enable signal and a read enable signal for a loading output of the image correction data for the input video signal based on a synchronous counting means for generating an output and a counting output from the synchronous counting means; In addition to the sugar, image correction data according to the radix / excellent line Control means for generating a select control signal to be applied to the pixel correction unit; odd correction data storage means for reading and outputting image correction data assigned as odd lines according to an address, the operation being enabled by the control means; Good correction data storage means for enabling operation by the means and reading out and outputting image correction data assigned as even lines according to the address, and enabled by the write enable signal from the control means, the odd correction data storage means First data storage means for recording and storing image correction data from the recording speed in synchronization with the recording clock, and reading image correction data enabled and stored by the read enable signal at a reading speed in synchronization with the reading clock; Is enabled by the write enable signal from the control means. Recording and storing the image correction data from the excellent correction data storage means at a recording speed synchronized with the recording clock, and reading the image correction data enabled and stored by the read enable signal at a reading speed synchronized with the read clock. Selectively applying image correction data corresponding to the odd / excellent line from the first data storage means and the second data storage means by the second data storage means and the select control signal from the control means; Provided is an image correction data loading apparatus for a projector, comprising a data switch means for performing switching for the projector.

According to the present invention configured as described above, in the projector employing the AMA member, the image correction data for correcting the manufacturing error of the AMA member is separate odd / excellent line data for each odd number line and even number line of the image signal. It can be stored in the storage means, and the image correction data according to the radix / excellent line through separate data for temporary radix / excellent line are pixel-matched by the radix / excellent line of the input video signal to correct the error. Make sure

1 is a block diagram showing an image correction data loading apparatus of a projector according to the present invention;

2 is a timing chart showing an operation waveform of each part shown in FIG. 1 according to a preferred embodiment of the present invention;

3 is a timing chart showing a generation state of a write / read clock supplied to each unit shown in FIG. 1 according to a preferred embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: synchronous separator, 12: synchronous counter,

14: controller, 16: odd correction data memory,

18: excellent correction data memory, 20: first line memory,

22: second line memory, 24: multiplexer,

26: ADC, 28: Pixel Assistance,

30: DAC, 32: AMA device.

Hereinafter, the present invention configured as described above will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing an image correction data loading apparatus of a projector according to the present invention. In the apparatus of the present invention, reference numeral 10 denotes a horizontal / vertical synchronous signal included in a predetermined input image signal. 12 shows a sync counter that counts the separated horizontal / vertical sync signals to generate a counting output.

Further, reference numeral 14 denotes for addressing image correction data corresponding to each radix / excellent line stored in the radix / excellent correction data memories 16 and 18 described later based on the counting output from the sync counter 12. For enabling the read operations of the first and second addresses ADD1 and ADD2 and their odd / excellent correction data memories 16 and 18 and the write operations of the first and second line memories 20 and 22 described later. First and second read enable signals WE1

And WE2, and generate first and second read enable signals RE1 and RE2 for enabling read operations of the first and second line memories 20 and 22, and will be described later. A control unit for generating the select control signal SEL for switching control of the multiplexer 24 is shown.

In this case, the control unit 14 has two pulse periods (ie, two image scanning line periods of the input image signal) of the horizontal synchronization signal H SYNC with respect to the input image signal as shown in FIG.

(2H)), the first write enable signal WE1 is generated, but the second write enable signal is generated.

WE2 is one pulse period (i.e., one video scanning period) with respect to the first write enable signal WE1.

(1H)), and the first address ADD1 is preceded by two pulse periods for the pulses of the horizontal synchronization signal H SYNC. And the second address ADD2 is delayed by one pulse period of the horizontal synchronization signal H SYNC with respect to the first address ADD1. And the first read enable signal RE1 is equal to or smaller than the horizontal sync signal H SYNC. -C-e-... corresponding to the image scanning line of the input image signal corresponding to the pulse) so that the corresponding image correction data is read out and the horizontal synchronization signal for the second read enable signal RE2. Corresponding to I-La-Bar -... Pulse (i.e., Na-La-Bar -... Pulse scan line of the input video signal corresponding to) It generates the image correction data to be read.

Further, reference numeral 16 is supplied with the first write enable signal WE1 from the control unit 14 as a read enable signal, the read operation is enabled, and is assigned to the odd line for the AMA device 32. 18 denotes a radix correction data memory made of, for example, a ROM that reads stored image correction data of stored radix lines synchronously to the clock W CLK by the first address ADD1 from the controller 14, and 18 denotes the controller ( The second write enable signal WE2 from 14) is applied as the read enable signal, and the read operation is enabled, and the image correction data of the even line is stored and assigned to the even line for the AMA device 32. A good correction data memory made of, for example, a ROM read out synchronously to the clock W CLK by the second address ADD2 from the control unit 14, is shown.

Reference numeral 20 denotes image correction data corresponding to the radix line from the radix correction data memory 16 after the recording operation is enabled by the first write enable signal WE1 from the controller 14. The data is recorded and stored at a recording speed synchronized with the recording clock W CLK, and the read operation is enabled by the first read enable signal RE1 from the control unit 14, and the read clock R CLK is stored therein. A first line memory for reading out image correction data stored at a read speed synchronous to the above, and 22 denotes that the write operation is enabled by the second write enable signal WE2 from the controller 14, and The image correction data according to the storm line from the storm correction data memory 18 is recorded and stored at a recording speed synchronized with the recording clock W CLK, and the second read enable signal from the controller 14 is stored. That by (RE2) Enabling the operation is taken up shows a second line memory which takes a reading the image correction data stored in the reading speed at which synchronization to the read clock (R CLK).

Here, the write clocks W CLK supplied to the odd / excellent correction data memories 16 and 18 and the first and second line memories 20 and 22 are first and second as shown in FIG. N equal to the number of n clocks forming the read clocks R CLK supplied to the line memories 20 and 22 are generated, so that the clock speed is 1/2 times that of the read clocks R CLK.

Further, reference numeral 24 denotes image correction data corresponding to the odd line from the first line memory 20 which is supplied with the select control signal SEL from the control unit 14 and input to the first input terminal A. And a multiplexer for switching to selectively output image correction data corresponding to even lines from the second line memory 22 input to the second input terminal B. FIG.

Reference numeral 26 denotes an analog-to-digital converter (ADC) for sampling and digitally converting a predetermined video signal, and 28 denotes the first through the multiplexer 24 corresponding to the digitally converted video data and the video data. A digital pixel that applies the image correction data to each pixel and outputs the corrected pixel driving data by matching the image correction data corresponding to the odd / excellent lines from the first and second line memories 20 and 22 by the pixel matching method. A numeral 30 denotes a digital-analog converter (DAC) which analog-converts the pixel-corrected image data and outputs it to the AMA device 32 as an image driving signal.

Next, the operation of the present invention made as described above will be described in detail with reference to the accompanying drawings.

First, the sync counter 12 counts a horizontal / vertical sync signal included in an input video signal separated from the sync separator 10 to generate a counting output according to the result, and the controller 14 controls the sync counter. On the basis of the counting output from (12), the first and second write enable signals WE1 and WE2 are applied to the cardinal / excellent correction data memories 16 and 18 and the first and second line memories 20 and 22, respectively. In addition, the first and second addresses ADD1 for reading other image correction data in the odd / excellent line into the odd / excellent correction data memories 16 and 18 are generated.

, ADD2).

Accordingly, the odd and excellent correction data memories 16 and 18 receive first and second write enable signals WE1 and WE2 from the control unit 14 as read enable signals, and the read operation is performed. Able to read and output image correction data corresponding to the odd / excellent line designated by the first and second addresses ADD1 and ADD2, while the first and second line memories 20 and 22 control the control unit. The write operation is enabled by the first and second write enable signals WE1 and WE2 from (14) to correct the image according to the odd / excellent lines from the odd / excellent correction data memories 16 and 18. The data is recorded and stored at a recording speed synchronized with the input clock clock W CLK.

At this time, the control unit 14, as shown in FIG. 2, the-from the pulse of the horizontal synchronization signal (H SYNC) with respect to the input video signal is-b-c-la-ma-bar-... The first read enable signal RE1 is generated so that the image correction data is read in response to the video scan line of the input video signal according to the pulse. The second read enable signal RE2 is generated such that the image correction data is read in response to the video scan line of the input video signal.

Accordingly, the first and second line memories 20 and 22 have the read operation enabled by the first and second read enable signals RE1 and RE2 from the controller 14 and the write clock. The image correction data according to the odd / excellent line stored at the read speed synchronized with the read clock R CLK having a clock speed twice that of (W CLK) is read, while the multiplexer 24 reads the control unit ( The first and second line memories 20 and 22 are received by selectively selecting the first input terminal A and the second input terminal B by receiving the select control signal SEL from the circuit 14). The image correction data corresponding to the odd / excellent line from is input to the pixel correction unit 28.

On the other hand, in the pixel correction unit 28, the input image signal digitally converted by the ADC 26 corresponds to the image correction data according to the odd / excellent line input through the multiplexer 24, respectively, in a pixel matching method. The pixel is output as the corrected image driving data, and the DAC 30 can analog convert the pixel corrected image driving data and supply it to the AMA device 32 as an image driving signal.

According to the present invention made as described above, the image correction data for correcting the manufacturing error of the AMA member in the projector employing the AMA member is stored in separate correction data storage means as radix / excellent correction data according to the radix / excellent line. Since the image correction data according to the radix / excellent line can be separately loaded and outputted, the digital noise generated on the loading output of the image correction data can be reduced, and the loading speed can be reduced. It has the advantage that it can be improved.

Claims (3)

The input image signal digitally converted by the data converter 26 is matched with the image correction data for error correction for the AMA member on the AMA device 32 per pixel and analog-converted by the data inverse converter 30. In the pixel correction device of a projector having a pixel correction unit 28 which is output to the AMA device 32 as an image driving signal, Sync counting means (10, 12) for generating a counting output as a result of counting the sync signals included in the input video signal; Address (ADD1, ADD2) and write enable signals (WE1, WE2) and read enable for loading output of the image correction data for the input video signal based on the counting output from the synchronous counting means (10, 12) A control for generating signals RE1 and RE2 per odd / excellent line, and generating a select control signal SEL for causing image correction data according to the odd / excellent line to be applied to the pixel correction unit 28. Means 14, Radix correction data storage means for operating by the control means 14 to read out and output image correction data assigned as radix lines according to the address ADD1. 16, Good correction data storage means for enabling the operation by the control means 14 to read and output the image correction data assigned as the even line according to the address ADD2. 18, Enabled by the write enable signal WE1 from the control means 14 to record and store image correction data from the radix correction data storage means 16 at a recording speed synchronized with the recording clock W CLK. First data storage means 20 for reading the image correction data enabled and stored by the read enable signal RE1 at a read speed synchronized with the read clock R CLK; Enabled by the write enable signal WE2 from the control means 14 to record and store image correction data from the good correction data storage means 18 at a recording speed synchronized with the recording clock W CLK. Second data storage means 22 for reading the image correction data enabled and stored by the read enable signal RE2 at a read speed synchronized with the read clock R CLK; Selecting the image correction data according to the odd / excellent line from the first data storage means 20 and the second data storage means 22 by the select control signal SEL from the control means 14 An image correction data loading apparatus for a projector, comprising: data switch means (24) for switching to apply to the correction unit (28). 2. An image correction data loading apparatus for a projector according to claim 1, wherein said first and second data storage means (20, 22) comprise a line memory. The method of claim 1, wherein the read clocks R CLK supplied to the first and second data storage means 20 and 22, respectively, have a clock speed twice that of the write clock W CLK. Image correction data loading device of the projector.