KR100203587B1 - Pixel data correction apparatus for projector - Google Patents

Abstract

The present invention provides an image correction apparatus for a projector which is intended to achieve stable pixel correction and noise reduction by loading and outputting pixel correction data through a plurality of line memories in a projector employing an AMA member.

Accordingly, according to the present invention, an address generating means 10 for generating an address based on a horizontal / vertical synchronization signal for a predetermined video signal and an address from the address generating means 10 are applied to correspond to the video signal. Correction data memory means 12 for outputting image correction data of the odd / excellent image line, and recording image correction data of the odd image line outputted from said correction data memory means 12 in synchronism with the recording clock WCK In the first line memory 14 and the recording clock WCK for storing and reading the image correction data of the radix video line synchronously stored in the read clock RCK having a double speed relative to the recording clock WCK. Synchronous recording and storage of the image correction data of the even image line output from the correction data memory means 12, and stored in synchronism to the read clock (RCK) A second line memory 16 for double-speed reading of image correction data of a line, and for resetting write operations of the first and second line memories 14 and 16 in synchronization with a horizontal / vertical synchronization signal by the video signal; A read enable signal RE for generating a write reset control signal RSTW and reading control of image correction data of stored odd / excellent video lines, respectively, to the first line memory 14 through the inverter 20. Control means 18 for outputting to the second line memory 16 and generating a read reset control signal RSTR for resetting the read operation, and the first and second line memories. And a signal adding means 22 for performing pixel correction by correspondingly adding the image correction data of the odd / excellent image line read out at 14 and 16 to the image signal.

Description

Image Correction Device of Projector

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image correction apparatus for a projector. More particularly, an image correction apparatus for correcting manufacturing errors for a plurality of AMA elements constituting an AMA member in a projector employing an AMA member to reproduce a projection type image on a screen. The present invention relates to an image correction apparatus of a projector that enables data to be loaded and output through a line memory to enable more accurate pixel correction and noise reduction.

Recently, a projector as a projection type image display device employing an AMA member or device has been proposed and put into practical use. The AMA device has a number of pixels for driving a plurality of pixels provided on a screen of 640 × 480 dimensions, for example. For example, a plurality of pixel driver elements composed of, for example, MOS transistors are formed in an active matrix substrate arranged in a matrix array form, and corresponding image pixels are formed on the active matrix substrate so as to correspond to each pixel. It is comprised by the actuator which inclines-deforms and modulates incident light (namely, optical path adjustment).

Assuming a screen of, for example, 640 × 480, such an AMA panel is provided with a plurality of pixel driving elements arranged in a matrix array corresponding to the total number of pixels constituting the screen.

Therefore, in order to reproduce an image by tilting the actuator corresponding to each pixel driver in response to the image signal voltage, the pixel driver provided in the AMA panel is formed in the form of a matrix array based on the image signal voltage corresponding to each pixel. In order to control the pixel driver, a row / column driver circuit is provided for driving the pixel driver to drive odd pixels and even pixels in the row / column direction of the AMA panel.

On the other hand, in the AMA member employed in such a projector, a primitive error occurs with respect to the initial inclination of each AMA element at the time of its manufacture, and image correction data based on the initial inclination with respect to the AMA member in order to attenuate such an original error. By generating and storing the data, the error of each pixel can be corrected by pixel matching with the input video signal.

According to an image correction apparatus in a projector for loading and outputting such image correction data for pixel matching with an image signal, a synchronization separator for separating a horizontal synchronization signal, a vertical synchronization signal, and a color subcarrier signal from the image signal, and its synchronization An address generator for generating an address signal and a control signal by combining a vertical synchronization signal separated from the separation unit, a clock signal generated by a horizontal synchronization signal, and a color subcarrier frequency signal; A correction data memory composed of, for example, a nonvolatile semiconductor memory (PROM) in which error correction values for the flatness of each actuator provided correspondingly to the transistor) are stored as image correction data, and pixel units corresponding to addresses generated by the address generator. Image is read from the correction data memory A data storage unit made of, for example, an SRAM which temporarily stores data and then re-outputs it; a pixel matching method comprising image data in which a predetermined video signal is digitally converted and image correction data provided through the data storage unit in response to the video data. A pixel correction unit for applying the image correction data to each pixel and outputting the corrected pixel driving data, and a data inverse converting unit for analog converting the pixel corrected image data and outputting it as an image driving signal to an AMA device. do.

The image correction apparatus of the projector having such a component reads the image correction data in pixel units at positions corresponding to the addresses sequentially provided by the address generator from the correction data memory, and stores them temporarily by the data storage unit, and then sequentially When applied to the digital pixel correction unit, the pixel correction unit matches the image data for the predetermined image signal digitally converted with the image correction data provided by the data storage unit on a pixel basis and outputs the corrected pixel drive data. The pixel error caused by the manufacturing error of each AMA device included in the AMA device can be accurately corrected so that the analog driving pixel driving signal can be supplied to the AMA device through the data inverse converter.

However, the image correction device of such a projector always generates 19 addresses for the image correction data so that the image correction data from the correction data storage unit is loaded and temporarily stored in the data storage unit made of SRAM. Not only does the digital noise increase due to the address, but also the cost burden is inevitably caused by the need to construct an expensive SRAM in which a data storage unit for temporarily storing image correction data is stored.

Accordingly, the present invention has been made in view of the above circumstances, and the projector employing the AMA member allows the pixel correction data to be loaded and output through a plurality of line memories to achieve stable pixel correction and noise reduction. The purpose is to provide a correction device.

In order to achieve the above object, according to the image correction apparatus of a projector according to the present invention, there is provided an address generating means for generating an address based on a horizontal / vertical synchronization signal for a predetermined video signal, and an address from the address generating means. Correction data memory means for outputting image correction data of the odd / excellent image line corresponding to the image signal, and recording and storing the image correction data of the odd image line outputted from the correction data memory means synchronously to a recording clock And a first line memory for double-speed reading of image correction data of a radix image line synchronously stored in a read clock having a double speed with respect to the recording clock, and an excellent image output from the correction data memory means synchronously with the recording clock. Record and store the image correction data of the line and store it in the read clock. A second line memory for double-speed reading of image correction data of a good image line stored in a conventional manner; and a recording reset for resetting the recording operation of the first and second line memories in synchronization with a horizontal / vertical synchronization signal caused by the video signal. A control signal is generated and a read enable signal for reading control of image correction data of stored odd / excellent video lines is outputted to the first line memory through an inverter, and outputted to the second line memory. Control means for generating a read reset control signal for resetting the read operation, and image correction data of the odd / excellent video line read speeds through the first and second line memories corresponding to the video signal. There is provided an image correction apparatus for a projector comprising a signal addition means for performing pixel correction.

According to the present invention configured as described above, the image correction data for correcting the manufacturing error for a plurality of AMA elements in the projector employing the AMA member is temporarily separated by the odd image line and the excellent image line through a plurality of line memories. By storing the double-speed read-out and matching the input video signal per pixel, pixel correction can be performed in a state where noise is reduced.

1 is a block diagram showing an image correction apparatus of a projector according to the present invention;

FIG. 2 is a timing chart showing a processing state of image correction data by the line memory shown in FIG. 1 according to a preferred embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: address generation unit, 12: correction data storage unit,

14: first line memory, 16: second line memory,

18: control unit, 20: inverter,

22: Adder.

Hereinafter, the present invention configured as described above will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing an image correction apparatus of a projector according to the present invention. In the apparatus of the present invention, reference numeral 10 denotes a horizontal / vertical synchronization signal (H) separated from a predetermined image signal to be reproduced as a projection image. SYNC / V SYNC) indicates an address generator that generates an address signal.

Further, reference numeral 12 denotes image correction data for a plurality of pixels for correcting manufacturing errors of a plurality of AMA elements constituting the AMA member, and stores the image according to an address signal from the address generator 10. Correction data for outputting the image correction data of the odd video line through the data terminals D0 to D7 corresponding to the signal, and for outputting the image correction data of the even video line through the data terminals D8 to D15. Represents storage.

Further, reference numeral 14 receives image correction data of the radix image line output from the correction data storage unit 12 at its data input terminal Din and synchronizes it with a recording clock WCK having a clock frequency of 12.5 MHz, for example. The recording operation is reset and stored by the recording reset control signal RSTW by the control unit 18, which is described later at a predetermined recording speed, and stored therein, and the readout from the control unit 18 as shown in FIG. The read operation is enabled by the enable signal RE, and is doubled with respect to the recording clock WCK. For example, the cardinal image line stored at the read speed synchronized with the read clock RCK having a frequency of 25 MHz A first line memory which reads the image correction data at double speed, outputs it through its data output terminal Dout, and whose read operation is reset by the read reset control signal RSTR.

Further, reference numeral 16 receives image correction data of the even image line output from the correction data storage unit 12 at the data input terminal Din and records at a recording speed synchronous to the recording clock WCK. The recording operation is reset and stored by the recording reset control signal RSTW by the control unit 18, and by the read enable signal RE from the control unit 18 as shown in FIG. When the read operation is enabled, the image correction data of the excellent video line stored at the read speed synchronized with the read clock RCK is read at double speed, the image correction data is output through the data output terminal Dout, and the read reset control signal RSTR Denotes a second line memory whose read operation is reset.

Further, reference numeral 18 denotes a write reset for resetting the write operation of the first and second line memories 14 and 16 in synchronization with the horizontal / vertical synchronization signal H SYNC / V SYNC separated from the video signal. A read enable signal RE for generating a control signal RSTW and controlling the image correction data of the odd / excellent video line temporarily stored in the first and second line memories 14 and 16 to be read at a double speed. The control unit which generates the read reset control signal RSTR for generating the read operation is also shown.

Reference numeral 20 denotes an inverter which inverts the signal level of the read enable signal RE from the control unit 18 and supplies the inverted signal level to the first line memory 14.

Reference numeral 22 matches and adds the image correction data of the odd / excellent video lines read out from the first and second line memories 14 and 16 to the pixel data and the pixel data digitally converted. The adder which correct | amends a pixel by a pixel and outputs is shown.

Next, the operation of the present invention made as described above will be described in detail with reference to the block diagram of FIG. 1 and the timing chart of FIG.

First, the correction data storage unit 12 outputs the image correction data of the odd image line through the data terminals D0 to D7 in accordance with the address signal from the address generator 10, and the data terminal D8. Through D15), image correction data of the even video line is output.

At this time, the first line memory 14 is outputted from the correction data storage section 12 at a recording speed synchronized with the recording clock WCK having a frequency of 12,5 MHz, for example, when the recording operation is enabled. The image correction data of the video line is recorded and stored, and the recording operation is reset by the recording reset control signal RSTW from the control unit 18, and the second line memory 16 is in the enabled state of the recording operation. The image correction data of the even video line output from the correction data storage unit 12 is recorded and stored at a recording speed synchronized with the recording clock WCK, and the recording operation is reset by the recording reset control signal RSTW. Is set.

Then, the control unit 18 generates a read enable signal RE in synchronization with the horizontal / vertical synchronization signal H SYNC / V SYNC separated from the image signal to be reproduced as the projection type image, and the first As the line memory 14 receives the read enable signal RE whose signal level is inverted by the inverter 20 and receives the read enable signal RE from the second line memory 16. As shown in FIG. 2, the signal levels of the read enable signal RE applied to the first and second line memories 14 and 16 are respectively inverted, so that the low level of the read enable signal RE is inverted. Image correction data of the odd / excellent image lines stored in each period are read out at a speed of reading synchronized with the read clock RCK, and are sequentially loaded and output.

Therefore, in the adder 22, image data obtained by digitally converting the image correction data of the odd / excellent image line which are read out and sequentially loaded through the first and second line memories 14 and 16 and sequentially loaded and output. The pixel is corrected for each pixel and the pixel is corrected and output.

According to the present invention made as described above, it is possible to individually load and output the image correction data of the odd / excellent video line through a plurality of line memory, it is possible to significantly reduce the digital noise by the address By separately loading and outputting image correction data of odd / excellent image lines, there is an advantage that stable pixel correction is possible even through low-cost line memories.

Claims (1)

Address generating means (10) for generating an address based on a horizontal / vertical synchronization signal for a predetermined video signal; Correction data memory means (12) for receiving an address from said address generating means (10) and outputting image correction data of odd / excellent video lines corresponding to said video signal; The image correction data of the odd image line output from the correction data memory means 12 is recorded and stored synchronously with the recording clock WCK, and the read clock RCK having a double speed with respect to the recording clock WCK is stored. A first line memory 14 for double-speed reading of image correction data of a rider image line stored synchronously; The image of the excellent image line synchronously stored in the read clock RCK is recorded and stored in the recording clock WCK in synchronism with the image correction data of the excellent image line output from the correction data memory means 12. Second line memory 16 for double-speed reading of the correction data; A stored odd / excellent image is generated by generating a write reset control signal (RSTW) for resetting the recording operation of the first and second line memories (14, 16) in synchronization with the horizontal / vertical synchronization signal caused by the video signal. A read enable signal RE for reading control of image correction data of a line, respectively, through the inverter 20 to the first line memory 14, and to the second line memory 16; Control means 18 for generating a read reset control signal RSTR for resetting the read operation; And signal adding means 22 for performing pixel correction by correspondingly adding the image correction data of the odd / excellent image line read out through the first and second line memories 14 and 16 to the image signal. The image correction apparatus of the projector, characterized in that the configuration.