KR0150535B1 - Pseudo-horizontal and vertical synchronizing signal generating circuit for projector - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo-synchronous signal generating circuit of an image display apparatus, and is applied to a projection type image display apparatus to display OSD information using an internally generated horizontal synchronization signal even when no image signal is input. Or under the control of the control unit 18 controlling the display of the background image and / or OSD text information when the image signal is not input, in order to generate a pseudo-synchronous signal (especially a vertical synchronization signal) necessary for displaying the background screen. A reference signal generator 30 for generating a reference signal corresponding to the subcarrier, and a pseudo horizontal synchronous signal generator 50 for generating a pseudo horizontal synchronous signal based on the reference signal generated by the reference signal generator 30. ), When the horizontal synchronous signal separated from the image signal and the horizontal synchronous signal of the image signal are not input, the pseudo horizontal synchronous signal generated by the pseudo horizontal synchronous signal generator 50 is switched. A pseudo-vertical synchronous signal generator 200 for generating a pseudo-vertical synchronous signal from the pseudo-horizontal synchronous signal generated by the pseudo-horizontal synchronous signal generator 50, and the image The second switching unit 100 for switching the pseudo-synchronous synchronous signal generated by the pseudo-vertical synchronous signal generating unit 200 when the vertical synchronous signal separated from the signal and the vertical synchronous signal of the image signal are not input. The pseudo synchronous signal generating means 17 is provided.

Description

Pseudo-synchronous signal generation circuit of image display device

1 is a block diagram showing the main part of a projection image display apparatus according to a conventional example.

2 is a schematic block diagram of a projection type image display apparatus employing a pseudo synchronous signal generating circuit according to a preferred embodiment of the present invention, capable of displaying a background image / OSD character information.

3 is a diagram showing a pseudo synchronous signal generating circuit of an image display apparatus according to a preferred embodiment of the present invention shown in FIG.

4 is a timing chart applied to the description of the pseudo synchronous signal generating circuit of the image display apparatus according to the preferred embodiment of the present invention shown in FIG.

* Explanation of symbols for the main parts of the drawings

10: RGB decoder 11: Data converter

12: address / control signal generator 13: sync signal separator

14: Image correction data storage unit 15: Image correction data storage unit (RAM)

16: image correction circuit portion 17: pseudo synchronous signal generation circuit portion

18: control unit 19: video memory

20: OSD processing unit 21: field memory

22: data inverse converter 23: AMA panel

24: row driving circuit section 25: column driving circuit section

30: reference signal generator 50: pseudo horizontal synchronous signal generator

60, 70: counter 90: first switching unit

100: second switching unit 102: Exclusive-OR gate

104: inverter 200: pseudo vertical synchronous signal generator

201, 207, 215: counter 213: AND gate

221: NAND gate

The present invention relates to a pseudo synchronous signal generation circuit of an image display apparatus, and more particularly, to an OSD using a color subcarrier (fsc) signal generated internally even when an image signal is not input because it is applied to a projection image display apparatus. (on screen display) relates to a pseudo synchronous signal generating circuit of an image display device for generating pseudo horizontal and vertical synchronous signals necessary for displaying information and / or displaying a background screen.

In general, a direct view type image display apparatus using a CRT apparatus which displays an image by emitting light of an R / G / B fluorescent point by an electron beam, or a projection type image display apparatus which reproduces an image by adjusting an arrangement state of liquid crystals When the signal is reproduced, horizontal and vertical synchronization signals separated from the image signal are essentially applied for the normal display of the screen.

In addition, according to the recently proposed reflective image display device employing an Actuated Mirror Array (AMA), an active matrix substrate in which pixel driving elements corresponding to all the pixels constituting one screen are arranged in a matrix array form; And an actuator arranged on the active matrix substrate to correspond to each pixel driving unit and reflecting incident light by a signal voltage applied corresponding to the pixel to reproduce a high quality image. In order to enable a proper screen configuration for a device, horizontal and vertical synchronization signals are necessary.

FIG. 1 is a schematic block diagram of the main part of such a projection image display apparatus, and reference numeral 10 denotes an image signal to be reproduced by performing optical modulation by an AMA panel (not shown) constituting the projection image display apparatus. Vin) shows an RGB decoder which decodes R / G / B signals, and 11 converts the R / G / B color signals decoded by the RGB decoder 10 into digital data by a clock signal CLK (4fsc). For example, a data conversion unit consisting of an analog-to-digital converter (ADC), 12 denotes a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync included in the image signal Vin by the synchronization signal separation unit 13, and An address / control signal generation section for generating an address signal and a control signal (writing and reading of data) by combining a clock signal 4fsc (fsc is a color subcarrier frequency). The address / control signal generator 12 divides the clock signal CLK in synchronization with the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync to generate an address and a control signal for pixel driving. For example, assuming a screen of 640 x 480, the total number of pixels of the screen is 307,200, and the address required for driving the pixels of the whole is 2 ⁰ -2 ¹⁸ . Accordingly, as is well known in the address / control signal generation unit 12, the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync separated by the synchronization signal separation unit 13 are combined and synchronous with the combined result. The clock signal is divided to generate an address for driving the pixel.

14 denotes an image correction data storage section composed of, for example, a nonvolatile semiconductor memory (ROM) in which correction values for the original error of each actuator provided correspondingly to the pixel driving elements constituting the AMA panel are stored as image correction data. The image correction data stored in the pixel correction data storage unit 14 is prepared in the form of a ROM table by calculating the correction data in advance with respect to the error of the result previously measured in the AMA panel, and the address / control signal generation unit 12 Correction data for the corresponding pixel are sequentially output based on the address and the control signal output from the.

In addition, when the correction data of the pixel unit corresponding to the address generated by the address / control signal generation unit 12 is read from the image correction data storage unit 14, the read image correction data is read by the address / control signal. An image correction data storage portion composed of, for example, a RAM which is temporarily stored in response to a control signal provided from the control signal generation portion 12 and then output again.

16 corresponds to the image correction data digitally converted by the data conversion unit 11 and the image correction data provided through the image correction data storage unit 15 in correspondence with the image data in a pixel matching method to perform the An image correction circuit section for outputting pixel drive data corrected by applying image correction data is shown.

Therefore, in such a projection type image display apparatus according to one conventional example, the image signal Vin to be reproduced is obtained as an R / G / B / color signal from the RGB decoder 10 and then the digital data from the data conversion section 11. Is applied to the image correction circuit section 16, and in this state, the address / control signal generation section 12 generates an address and a control signal for reading the correction data of all the pixels as described above to generate the image correction data. The storage unit 14 and the image correction data storage unit 15 are applied.

In the pixel correction data storage unit 14, image correction data of pixel positions corresponding to addresses sequentially provided by the address / control signal generation unit 12 is transmitted to the image correction data storage unit 15. The image correction data storage unit 15 temporarily stores the image correction data on the basis of the control signal provided from the address / control signal generation unit 12 and then sequentially applies the image correction data to the image correction circuit unit 16.

Therefore, the image correction circuit unit 16 matches the image correction data provided from the image correction data storage unit 15 with respect to the digitally converted image signal on a pixel-by-pixel basis to correct the pixel drive data corrected for the row / column drive circuit. It is provided to the furnace means (not shown), and accordingly, tilting for reflection of incident light is performed while the overall fundamental error of the actuator provided in the AMA panel is corrected.

In general, in the direct view type image display apparatus or the projection type image display apparatus using the CRT apparatus, the horizontal and vertical synchronous signals for the configuration of the screen are horizontal and vertical synchronous signals Hsync included in the image signal Vin when the image signals are input. Display the screen including the background screen and / or OSD text information because the screen is not available when the image signal Vin is not received. To this end, clock signals of a predetermined frequency oscillated by the oscillation means are divided into horizontal synchronization signals, and the divided horizontal synchronization signals are divided again to generate pseudo horizontal and vertical synchronization signals.

That is, in order to display a blue screen as a background or to display OSD text information for displaying a current operation state as text information in the state where no external image signal is received, such pseudo horizontal and vertical synchronization is performed. Signal is required, and accordingly, in the projection image display device or the direct image display device, the frequency signal oscillated from the usual oscillation means is divided by the dispensing means to generate pseudo horizontal and vertical synchronization signals. Must be given.

The present invention has been made in view of the above circumstances, and generates a pseudo horizontal synchronizing signal from a reference signal corresponding to the color subcarrier signal oscillated by the oscillating means, and generates a pseudo vertical synchronizing signal using the pseudo horizontal synchronizing signal. Another object of the present invention is to provide a pseudo-synchronization signal generating circuit of an image display device which can be switched to display OSD character information and, when receiving an image signal, to switch the horizontal and vertical synchronization signals separated from the image signal to the screen display. have.

In order to achieve the above object, according to a preferred embodiment of the present invention, an AMA panel for optically modulating an input image signal by an optical modulation method, and a row / column drive for driving control of optical modulation by the AMA panel in a row / column direction. A circuit portion, a synchronous signal separator for separating the synchronous signal from the input image signal, image correction data storage for image display and image correction data stored in the image correction data storage based on the synchronous signal detected by the synchronous signal separation A projection type image display apparatus comprising: an address / control signal generation section for processing of an image; and an image correction circuit section for generating corrected image correction data by adding the image signal and the image correction data to a non-input of the image signal. A reference unit for generating a reference signal corresponding to a color subcarrier under the control of a control unit that controls the display of the background image and / or OSD character information. A pseudo horizontal synchronous signal generator for generating a pseudo horizontal synchronous signal based on the reference signal generated by the reference signal generator, a ratio of the horizontal synchronous signal separated from the image signal to the horizontal synchronous signal of the image signal A first switching unit for switching the pseudo horizontal synchronizing signal generated by the pseudo horizontal synchronizing signal generating unit on input, and generating a pseudo vertical synchronizing signal from the pseudo horizontal synchronizing signal generated by the pseudo horizontal synchronizing signal generating unit; A pseudo-synchronous vertical signal generator for switching the pseudo-synchronous synchronizing signal generated by the pseudo-vertical synchronizing signal generator when switching between the vertical synchronizing signal separated from the image signal and the vertical synchronizing signal of the image signal; A synchronous signal generating circuit of an image display device is provided, comprising a pseudo synchronous signal generating circuit portion having a switching portion.

Preferably, the pseudo horizontal synchronizing signal generator is configured to logic the first and second counters and the count results of the first and second counters to hexadecimal count the reference signal by the number of pulses included in the period of the horizontal synchronizing signal. And a logic gate for outputting the result of the logic processing as a pseudo horizontal synchronization signal.

According to the present invention, the first counter of the pseudo horizontal synchronous signal generation unit has a constant ground potential (GND) of the first, third, and fourth input terminals to count the lower digits of data obtained by converting the period of the horizontal synchronous signal into a hexadecimal number. And a second input terminal connected to a constant power supply potential (Vcc), wherein the second counter of the pseudo horizontal synchronization signal generation unit counts the upper digits of the data obtained by converting the period of the horizontal synchronization signal to hexadecimal. To third input terminals A0, B0, and C0 are connected to the ground potential GND, and the fourth input terminal D is connected to the constant power potential Vcc, and the logic gate of the pseudo horizontal synchronizing signal generator And NAND gates for performing logic NAND processing of the count outputs of the first and second counters.

An exclusive logic sum gate having one end connected to a horizontal synchronous signal separated from the image signal and another end connected to the pseudo-generated horizontal synchronous signal to switch the horizontal synchronous signal and the pseudo horizontal synchronous signal; And an inverter for inverting the output of the exclusive logical sum gate.

Further, according to the present invention, the pseudo synchronous signal generating portion of the pseudo synchronous signal generating circuit part includes first to hexadecimal counts of the pseudo horizontal synchronous signal over a period of the vertical synchronous signal, and generates a count result as a pseudo vertical synchronous signal. A third logical counter, a first logic gate for logic processing the count results of the first and second counters, an output of the first logic gate and a count result of the third counter, and a logic process to output a count as a pseudo vertical synchronization signal The first to third counters, each of which is composed of second logic gates, are executed by counting the periods of the vertical synchronization signal converted into hexadecimal digits, and counting is performed at the end of the count (ie, carry). Is output as a pseudo-vertical synchronous signal.

In addition, the first counter is clock-controlled by a pseudo horizontal synchronization signal so that the clock stage CLK is clocked by the pseudo horizontal synchronization signal so as to count the least significant digit of the hexadecimal data for the period of the vertical synchronization signal (the number of pulses of the pseudo-synchronous synchronization signal). The third input terminal is connected to the ground potential GND at all times, and the fourth input terminal D1 is connected to the power supply potential Vcc so that its initial value is set to '8' (hexadecimal), and from the initial value to '7' (16). Decimal number) and outputs a high level count result, and the second counter clock-controls the clock stage CLK by the pseudo horizontal synchronization signal to count the intermediate digits of the hexadecimal data of the vertical synchronization signal. And the first to fourth input terminals A2,-, D2 are connected to the constant power supply potential Vcc, and the fifth input terminal END is connected to the high level output of the first counter, and its initial value is 'F' ( Hexadecimal) and the high level count result from the first counter. Is applied to output a high level count result (ie, carry), and the third counter has a clock stage CLK horizontal to count the most significant digit for the period of the vertical synchronization signal converted into the hexadecimal number. The clock is controlled by the synchronization signal, and the first input terminal is connected to the constant ground potential GND, and the second to fourth input terminals B3, C3, and D3 are connected to the constant power supply potential Vcc, and the fifth input terminal END Connected to the high level output of the second counter and its initial value is set to 'E' (hexadecimal) so that the hexadecimal count is executed from the second counter according to the high level count result (i.e., Carry).

Preferably, the second switching unit of the pseudo synchronous signal generation circuit portion is connected to the vertical synchronous signal, one end of which is connected to the vertical synchronous signal separated from the image signal, and the other end of the pseudo synchronous signal generation circuit portion, to the pseudo synchronous signal and the pseudo vertical. And an exclusive logic sum gate for switching output of the synchronous signal and an inverter for inverting the output of the exclusive logic sum gate.

According to the pseudo synchronous signal generation circuit of the image display apparatus according to the present invention configured as described above, a pseudo signal is generated by hexadecimal counting a reference signal corresponding to the color subcarrier frequency of the image signal over a period (approximately 228) of the horizontal synchronous signal. Generates a horizontal synchronous signal and generates a pseudo vertical synchronous signal according to the result of the hexadecimal count over the period (approximately 263) of the vertical synchronous signal, so that the background image and / or OSD character information when the image signal is not input. When the horizontal and vertical synchronous signals are provided in accordance with the input of the image signal, the horizontal and vertical synchronous signals separated from the image signal are switched. Under control, it is possible to output the background image and / or OSD character information.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a projection-type image display apparatus including a pseudo-synchronous signal generating circuit according to the present invention and enabling display of a background screen and / or OSD character information on the basis of a synchronization signal generated by the pseudo-synchronous signal generating circuit. Is a block diagram of a projection structure, which is generally similar to the projection type image display apparatus described with reference to FIG. 1, but has a pseudo synchronizing signal upon non-input of an image signal at the rear end of the synchronizing signal separation section for separating the synchronization signal from the image signal. And a pseudo synchronous signal generation circuit unit for generating a synchronous signal, and a control unit for controlling the display of a background screen and / or OSD text information using the pseudo synchronous signal generated by the pseudo synchronous signal generation circuit unit. An OSD processing unit for generating the set video memory and OSD text information is additionally provided.

That is, according to the projection type image display apparatus shown in FIG. 2, where the same reference numerals are given to the same or similar components as those of the image display apparatus shown in FIG. 1, reference numeral 10 designates the projection image display apparatus. An RGB decoder which decodes an image signal Vin to be reproduced by R / G / B signal by performing optical modulation by the AMA panel denoted by reference numeral 23, 11 denotes an R / G decoded by the RGB decoder 10. A data converting unit converts the / B signal into digital data, and 12 denotes a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, and a clock signal included in the image signal Vin by the synchronizing signal separating unit 13. (4fsc; fsc denotes an address / control signal generation unit that combines a color subcarrier frequency) to generate an address signal and a data write / read control signal.

Reference numeral 14 denotes an image correction data storage configured by, for example, a nonvolatile semiconductor memory (ROM) in which correction values for primitive errors of respective actuators provided corresponding to the pixel driving elements constituting the AMA panel 23 are stored as image correction data. As shown, the image correction data stored in the pixel correction data storage unit 14 is generated in the form of a ROM table by calculating correction data with respect to an error of flatness previously measured by the AMA panel 23. On the basis of the address and the control signal output from the control signal generator 12, correction data for the corresponding pixel is sequentially output.

In addition, when the correction data of the pixel unit corresponding to the address generated by the address / control signal generation unit 12 is read from the image correction data storage unit 14, the read image correction data is read by the address / control signal. An image correction data storage portion composed of, for example, a RAM, preferably an SRAM, which is temporarily stored in response to a control signal provided from the control signal generation portion 12 and then output again.

16 corresponds to the image correction data digitally converted by the data conversion unit 11 and the image correction data provided through the image correction data storage unit 15 in correspondence with the image data to the pixel matching method. An image correction circuit section for outputting pixel drive data corrected by applying image correction data is shown.

17 denotes a case where the synchronization signal is not separated by the synchronization signal separating unit 13 which separates the synchronization signal from the diffuser image signal Vin, i.e., under the control of a controller to be described later when the image signal Vin is not input. A pseudo synchronous signal generation circuit portion for generating a pseudo horizontal synchronous signal and a pseudo vertical synchronous signal by dividing a reference signal corresponding to the color subcarrier signal generated in response to the system clock signal CLS, and 18 denotes the pseudo synchronous signal. A control unit is configured to control the display of the background image and / or the OSD text information on the image display device by applying the pseudo horizontal and vertical synchronization signals generated by the generation circuit unit 17. 19 denotes an image signal under the control of the control unit 18. (Vin) indicates a video memory in which screen data for displaying a blue screen Bd, for example, as a background screen, is set on a screen when no input is performed, and 20 denotes a control of the controller 18. The OSD processing unit for generating OSD character information OSD to be displayed on the screen according to the pseudo synchronous signal is shown below.

21 denotes a field memory for receiving and storing image data corrected by the image correction circuit unit 16 based on the control signal generated by the address / control signal generation unit 12 and sequentially outputting the result. The image correction data or background image Bd and / or OSD character information OSDd sequentially output from the field memory 21 are digitally controlled by the control signal generated by the address / control signal generation unit 12. Indicates the data inverse conversion unit for analog conversion.

In addition, 24 is a row driving circuit unit for driving the pixel-based actuator provided in the AMA panel 23 based on the image data analog-converted by the data inverse conversion unit (DAC) 22 with respect to the AMA panel 23. 25 denotes a column drive circuit portion for driving the actuator by designating a pixel drive element consistent with the row drive circuit portion 24 to the AMA panel 23.

Therefore, in such a projection type image display apparatus, the video signal Vin to be reproduced is decoded into an R / G / B signal by the RGB decoder 10 and then converted into digital data by the data conversion section 11 to be imaged. The horizontal / vertical synchronization signals Hsync and Vsync and the clock signal 4fsc which are applied to the correction circuit unit 16 and in that state are separated by the synchronization signal separation unit 13 in the address / control signal generation unit 12. This generates an address and a control signal for reading the correction data of all the pixels constituting the AMA panel 23.

In the image correction data storage unit 14, image correction data of pixel positions corresponding to addresses sequentially provided by the address / control signal generation unit 12 is transmitted to the image correction data storage unit 15, and The image correction data storage section 15 temporarily stores the image correction data based on the control signal provided from the address / control signal generation section 12, and then sequentially applies the image correction data to the image correction circuit section 16.

Therefore, the image correction circuit unit 16 matches the image correction data provided from the image correction data storage unit 15 with respect to the digitally converted image signal on a pixel-by-pixel basis and corrects the pixel drive data corrected for the field memory 21. In the field memory 21, the pixel drive data is applied to the data inverse converter 22 by analog address by the address / control signal provided from the address / control signal generator 12, and then analog-converted. And provided on the AMA panel 23 under the driving of the column drive circuit section 25 which selects a pixel based on the address generated by the control signal generation section 12 at that time. The true pixel driving element is driven to reflect the incident light.

In this case, when the image signal Vin is not input, the background signal and / or OSD text information cannot be displayed because the synchronization signal is not detected. However, in the present invention, the control unit 18 will be described later. The pseudo synchronous signal generating circuit section 17 generates pseudo horizontal and vertical synchronous signals from the reference signals provided from the reference signal generating means and provides them to the address / control signal generating section 12, thereby providing the address / control. The signal generation unit 12 controls the field memory 21 and the data inverse conversion unit 22 by the pseudo horizontal and vertical synchronization signals from the video memory 19 applied under the control of the control unit 18. Processing the background screen (Bd) of the OSD or the OSD text information (OSDd) provided by the OSD processing section 20 is analog converted in the data inverse conversion section 22, and then the AMA panel 23 ) Is applied.

FIG. 3 is a diagram showing a detailed configuration of the pseudo synchronous signal generating circuit portion 17 shown in FIG. 2, and the pseudo synchronous signal generating circuit portion 17 generally has a standard equivalent to a color subcarrier fsc (≒ 3.58 MHz). A reference horizontal signal generator 30 for generating a signal, and a pseudo horizontal synchronized signal generator 50 for generating a pseudo horizontal synchronized signal based on the reference signal fsc generated by the reference signal generator 30. A first switching unit 90 for switching and outputting the horizontal synchronous signal Hsync separated when the image signal is input and the pseudo horizontal synchronous signal Hsync generated by the pseudo horizontal synchronous signal generator 50 when the image signal is not input. It is constructed with).

Here, the pseudo horizontal synchronization signal generator 50 has a period of 279 nsec of color subcarrier frequency (approximately 3.58 MHz) generated from the reference signal generator 30, as shown in the timing chart shown in FIG. (See FIG. 4 (a)), approximately 228 number of color subcarrier signals exist in one horizontal synchronization signal (approximately 63.5 μsec period) (see FIG. 4 (b)), and one vertical In the period of the synchronization signal (approximately 16.67 msec), the horizontal synchronization signal is present with approximately 263 pulses (see FIG. 4 (c)).

Accordingly, the pseudo horizontal synchronizing signal generator 50 includes first and second counters 60 and 70 for hexadecimal counting the reference signal to obtain a pseudo horizontal synchronizing signal. When the first counter 60 counts a reference signal included in one horizontal synchronous signal to generate a pseudo horizontal synchronous signal from the reference signal, a period (ie, a reference signal of 228 pulses) for the horizontal synchronous signal is counted. The hexadecimal reciprocal of the '4' is set to an initial value so that the hexadecimal count ('4') of the hexadecimal data (ie, 'E 4'-1110 0100) is hexadecimal counted. That is, the first, third and fourth input terminals A, C, and D of the first counter 60 are connected to the power supply potential Vcc, and the second input terminal B is always connected to the ground potential GND. When connected to count '4' (hexadecimal), the output terminal RCO outputs a high level count result (ie, carry). Similarly, the second counter 70 sets the period of the horizontal synchronization signal (ie, the reference signal of 228 pulses) to the higher digit ('E 4'-1110 0100) of the hexadecimal data. The hexadecimal reciprocal of the 'E' is set to the initial value so that the hexadecimal count is counted. That is, the first to third input terminals A0, B0, and C0 of the second counter 70 are connected to the power supply potential Vcc, and the fourth input terminal D0 is connected to the constant ground potential GND. Counting E '(hexadecimal) outputs a high level count result (ie, carry) at the output terminal RCO.

In addition, the output RCO of the first counter 60 and the output RCO of the second counter 70 are respectively connected to the first and second counters through the inverters 62, 64; 72, 74. The NAND results of the counts 60 and 70 are logically NAND-processed to output the result of the processing as a pseudo horizontal synchronization signal Hsync '.

In addition, the pseudo horizontal synchronous signal generating unit 50 has the first and second counters 60 and 70 when the horizontal synchronous signal Hsync separated from the image signal Vin and the image signal are not input. A first switching unit 90 for switching the obtained pseudo horizontal synchronization signal Hsync 'is provided. The switching unit 90 includes an exclusive logical sum gate 92 and an exclusive logical sum gate 92 for switching and outputting the horizontal synchronization signal Hsync and the pseudo horizontal synchronization signal Hsync 'separated from the image signal Vin. The inverter 94 which inverts the output of the circuit is provided.

In addition, the pseudo synchronous signal generating circuit unit 17 receives the vertical synchronous signal Vsync when the image synchronous signal Vin is separated from the synchronous signal separator 13 when the image signal Vin is input. When the vertical synchronization signal Vsync is not input while the switching output is performed, the pseudo vertical synchronization signal Hsync 'generated by the pseudo horizontal synchronization signal generator 50 generates a pseudo vertical synchronization signal Hsync'. A second vertical switching unit 100 for switching and a pseudo vertical synchronizing signal generator 200 for counting the pseudo horizontal synchronizing signal Hsync 'when the image signal Vin is not input to obtain a pseudo vertical synchronizing signal; ) Is also included.

The switching unit 100 switches and outputs the vertical synchronous signal Vsync separated from the synchronous signal separator 13 and the pseudo vertical synchronous signal Vsync 'generated by the pseudo vertical synchronous signal generator 200. The logic sum gate 102 and the inverter 104 which inverts the output of the gate 102 are provided.

In addition, the pseudo vertical synchronous signal generator 200 generates a pseudo vertical synchronous signal Vsync 'based on the pseudo horizontal synchronous signal Hsync' generated by the pseudo horizontal synchronous signal generator 50. And an AND gate 213 for performing logical AND processing on the third counters 201, 207, and 215, and the count result (carrie) of the first and second counters 201 and 207, and the output of the AND gate 213. And a NAND gate 221 for performing logic NAND processing on the count result (carrie) of the third counter 215, and the output of the NAND gate 221 is a pseudo vertical synchronization signal Vsync '. It is applied to the exclusive logical sum gate 102 which constitutes 100, and is switched and output as the pseudo vertical synchronization signal Vsync 'when the image signal Vin is not input.

Here, while the vertical synchronization signal Vsync separated from the image signal Vin is 262.5, when the period of the pseudo vertical synchronization signal Vsync 'is assumed to be N, the vertical synchronization signal Vsync is included in the period of one vertical synchronization signal. The horizontal synchronization signal is

N = scan line ÷ frame / 2

= 525/2

= 262.5 ≒ 263

If 263 is converted into hexadecimal, it is approximately '107' (hexadecimal).

Accordingly, as can be seen in FIG. 3, the first counter 201 constituting the pseudo vertical synchronous signal generator 200 has the least significant digit for the period N of the vertical synchronous signal converted into hexadecimal. The clock terminal CLK is clocked by the pseudo horizontal synchronization signal Hsync 'to count' 7 ', and the first to third input terminals A1, B1, and C1 are connected to the constant ground potential GND. The fourth input terminal (D1) at the top is connected to the power supply potential (Vcc), and the initial value of the count is set to '8' (hexadecimal) and counts '7' (hexadecimal) from the initial value to output terminal (RCO). Is configured to output a high level count result (ie, carry).

The second counter 207 has a clock stage CLK for counting the intermediate digit '0' with respect to the period N of the vertical synchronization signal converted into the hexadecimal number, and the pseudo horizontal synchronization signal Hsync '. The first to fourth input terminals A2, B2, C2, and D2 are connected to the power supply potential Vcc, and the fifth input terminal (END) is connected to the first counter 201. Is connected to a high level output (carry) and its initial value is set to 'F' (hexadecimal) to output a high level count result (ie, carry) when a high level is applied from the first counter 201. do.

The third counter 215 is clock-controlled by the pseudo horizontal synchronization signal so that the clock stage CLK counts the last digit '1' for the period N of the vertical synchronization signal converted into the hexadecimal number. Meanwhile, the first input terminal A3 is connected to the constant ground potential GND, and the second to fourth input terminals B3, C3, and D3 are connected to the constant power supply potential Vcc, and the fifth input terminal END is enabled. ) Is connected to the output RCO of the second counter 207 and its initial value is set to 'E' (hexadecimal) so that the high level count is applied when the high level output is applied from the second counter 207. To output the result (ie, carry).

The AND gate 213 and the NAND gate are connected to the output side of the first counter and the second counter 201 and 207 through inverters 203, 205, 209 and 211 of series connection for waveform shaping, respectively. The corresponding input terminal of 221 is connected, and the NAND gate 221 is connected to the output (RCO) side of the AND gate 213 and the output (RCO; inverters 217 and 219 connected) of the third counter 215. The corresponding input terminal of N is connected, and the output of the NAND gate 221 is applied as a pseudo vertical synchronizing signal Vsync 'to one end of the exclusive logic sum gate 102 of the switching unit 100.

Referring to the operation relating to the generation of the pseudo horizontal and vertical synchronization signals in such a configuration, first, when the image signal Vin is input, the image signal Vin is subjected to a reproduction process by the above-described procedure, and such a reproduction process. When the horizontal and vertical synchronous signals Hsync and Vsync included in the image signal Vin are separated by the synchronous signal separator 13 and applied to the pseudo synchronous signal generator 17, the pseudo synchronous signal Due to the switching action of the exclusive OR gates 92 and 102 configured in the first and second switching units 90 and 100 of the generation unit 17, the exclusive OR gates 92 and 102 are used to generate the image signal Vin. Subsequent processing described with reference to FIG. 2 as separate horizontal and vertical synchronization signals Hsync and Vsync are switched and output to the subsequent control signal generation unit 12 via inverters 94 and 104. Will be performed.

In contrast, when the image signal Vin is not input, the control unit 18 outputs an internal system clock signal CLS, for example, and the color subcarrier in the reference signal generator 30 illustrated in FIG. Corresponding to the reference signal is generated. Accordingly, the pseudo horizontal synchronous signal generator 50 hexadecimal counts the reference signal at the first and second counters 60 and 70 to generate a pseudo horizontal synchronous signal (Hsync). Will generate '). That is, the first counter 60 counts the lower digits '4' of the hexadecimal data (ie, 'E 4') of the horizontal synchronization signal allocated for generating the horizontal synchronization signal, and then highs the output terminal RCO. The second counter 70 counts 'E' in the hexadecimal data of the allocated horizontal sync signal by outputting the high level at the first counter 60 and outputs the high level at the output terminal. Done. The high level outputs of the first and second counters 60 and 70 are logically NAND-processed at the NAND gate 80 to be switched out of the exclusive logic sum gate 92 of the first switching unit 90, and then to the inverter. Inverted at 94 is output as a pseudo horizontal synchronization signal Hsync '.

The pseudo horizontal synchronizing signal Hsync 'generated as described above is applied to the first to third counters 201, 207, and 215 of the pseudo vertical synchronizing signal generating unit 200, and thus the first to third counters. The counters 201, 207, and 215 convert the period 262.5 of the vertical synchronization signal into hexadecimal (i.e., '107'), and the counters 201, 207, and 215 are allocated to the counters with their inverses set to initial values. The count operation for the initial value is executed.

That is, with respect to the first counter 201, when the count of '7' is counted with '8' which is the inverse of the least significant digit 7 for the period of the vertical synchronization signal converted into hexadecimal, RCO) outputs a high level signal (ie, carry).

In addition, the second counter 209 is connected to the first to fourth input terminals at a constant power supply potential to perform counting for the inverse of the intermediate digit '0' in the period of the vertical synchronization signal converted into the hexadecimal number. When a high level signal is applied from the first counter 201, a high level count result (ie, a carry) is immediately output. When the count result of the first and second counters 201 and 207 becomes high level and is applied to the AND gate 213 through the inverters 203, 205, 209 and 211, respectively, the AND gate 213 is high. The level is output and applied to the third counter 215.

Therefore, in the third counter 215, the AND gate 213 for ANDing the count for the most significant digit '1', that is, the count results of the first and second counters, in the period of the vertical synchronization signal converted into the hexadecimal number. The high level output of " 1 " of hexadecimal numbers is performed to output a high level count result (ie, carry).

The NAND gate 221 connected to the output side of the AND gate and the output side of the third count is applied to the third counter 215 through the output result of the AND gate 213 and the inverters 217 and 219. Is generated as a pseudo vertical synchronization signal (Vsync '), where the counting result of the first counter 201 shows the counting result of' 7 'from the initial value 8 and the second counter 207 is the initial value. Since the counting is performed at 15, the output indicates 15 of the hexadecimal number, and the output of the third counter 215 counts '1' with the initial value set to 14 to provide the count output corresponding to 15 of the hexadecimal number. Eventually, the output values of the first to third counters 201, 207, and 215 correspond to 256 in decimal, but the count of '7' in hexadecimal is counted from the state in which the initial value of the first counter is set to '8'. Therefore, the result of the final count is the vertical sync. 263 is the equivalent to the period of the (Vsync ').

The pseudo-vertical synchronous signal Vsync 'generated as described above is applied to the exclusive OR gate 102 of the switching unit 100 to be switched and then inverted by the inverter 104 to generate the address / control signal. Applied to the unit 102.

In this state, the control unit 18 controls the video RAM 19 and / or the OSD processing unit 20 to display a set background screen and / or text information, and outputs a blue screen as a background screen or OSD text. The information is applied on the AMA panel 23 to perform the screen display of the background screen or text information.

As described above, according to the present invention, pseudo-horizontal and vertical synchronizing signals which are applied for displaying on-screen display (OSD) information and / or a background screen in the state in which no image signal is input in the image display device are easily generated. Thus, even in the non-input state of the image signal, the display of the background screen or the screen output of the character information is possible.

On the other hand, the above description has been made of an example in which the present invention is applied to a projection type image display apparatus. However, the present invention is not limited to the example. Of course it can.

Claims (7)

The AMA panel 23 which optically modulates the input image signal by the optical modulation method, the row / column driving circuit sections 24 and 25 which drive control the optical modulation by the AMA panel 23 in the row / column direction, and the input A synchronization signal separation unit 13 for separating the synchronization signal from the image signal, an image correction data storage unit and an image correction data storage unit 14 for displaying an image based on the synchronization signal detected by the synchronization signal separation unit 13; 15. A projection type comprising an address / control signal generation section 12 for processing image correction data stored in < RTI ID = 0.0 > 15 < / RTI > and an image correction circuit section 16 for generating corrected image correction data by adding the image signal and the image correction data. In the image display apparatus, a reference signal generation section (30) which generates a reference signal corresponding to a color subcarrier under the control of a control unit (18) which controls the display of a background image and / or OSD character information when the image signal is not input. ) And the reference signal generation The pseudo horizontal synchronous signal generator 50 for generating a pseudo horizontal synchronous signal based on the reference signal generated by the unit 30, when the horizontal synchronous signal separated from the image signal and the horizontal synchronous signal of the image signal are not inputted. From the first switching unit 90 for switching the pseudo horizontal synchronization signal generated by the pseudo horizontal synchronization signal generator 50 and the pseudo horizontal synchronization signal generated by the pseudo horizontal synchronization signal generator 50. The pseudo-vertical synchronous signal generator 200 which generates a pseudo-vertical synchronous signal, and generates the pseudo-vertical synchronous signal generator 200 when the vertical synchronous signal separated from the image signal and the vertical synchronous signal of the image signal are not input. And a pseudo synchronous signal generating circuit section (17) having a second switching section (100) for switching the output of the pseudo vertical synchronous signal. The first and second counters 60 and 70 of claim 1, wherein the pseudo horizontal synchronous signal generator 50 hexadecimal counts the reference signal by the number of pulses included in a period of the horizontal synchronous signal; Generating a pseudo synchronous signal of the image display apparatus, comprising: a logic gate 80 for logically processing the count results of the first and second counters 60, 70 and outputting the result of the logic processing as a pseudo horizontal synchronous signal. Circuit. The first counter 60 of the pseudo horizontal synchronous signal generation unit 50 is configured to count the lower digits of data obtained by converting the period of the horizontal synchronous signal into hexadecimal. The input terminals A, C, and D are connected to the constant ground potential GND, and the second input terminal B is connected to the constant power supply potential Vcc. The counter 70 has a first to third input terminals A0, B0, and C0 connected to the ground potential GND so as to count the upper digits of the data obtained by converting the period of the horizontal synchronization signal to hexadecimal. D) is connected to the constant power supply potential (Vcc), and the logic gate 80 of the pseudo horizontal synchronization signal generator 50 controls the logic output of the count outputs of the first and second counters 60 and 70. A pseudo synchronous signal generation circuit of an image display apparatus, comprising: a NAND gate to process. 2. The first switching unit (90) according to claim 1, wherein one end of the first switching unit (90) is connected to the horizontal synchronous signal separated from the image signal and the other end is connected to the pseudo synchronously generated horizontal synchronous signal. A pseudo synchronous signal generation circuit of an image display apparatus, comprising: an exclusive logical sum gate (92) for switching and outputting a horizontal synchronous signal; and an inverter (94) for inverting the output of the exclusive logical sum gate (92). 2. The pseudo synchronous signal generator 200 of the pseudo synchronous signal generator circuit 17 hexadecimal counts a pseudo horizontal synchronous signal over a period of a vertical synchronous signal, and counts the result of the pseudo vertical synchronous signal. First to third counters 201, 207, and 215 to be generated as a first logic gate, and a first logic gate 213 and a first logic unit to logically count results of the first and second counters 201, 207, and 215. And a second logic gate 221 which logically processes the output of the logic gate 213 and the count result of the third counter 215 and outputs it as a pseudo-vertical synchronous signal. The first to third counters 201, 207 and 215, the period of the vertical synchronization signal is converted into a hexadecimal number, and the count is executed for the allocated digit, and at the end of the count, the count result is output as a pseudo vertical synchronization signal. Pseudo-synchronous signal generation circuit. The clock stage CLK of claim 5, wherein the first counter 201 counts the least significant digit of the hexadecimal data with respect to the period of the vertical synchronization signal (the number of pulses of the pseudo-synchronous synchronization signal). The first to third input terminals A1, B1, C1 are connected to the ground potential GND, and the fourth input terminal D1 is connected to the power source potential Vcc, and its initial value is '8'. Hexadecimal) and counts '7' (hexadecimal) from the initial value to output a high level count result, and the second counter 207 is intermediate to the hexadecimal data of the vertical synchronization signal. The clock stage CLK is clock-controlled by a pseudo horizontal synchronizing signal to count the digits, and the first to fourth input terminals A2,-, D2 are connected to the constant power supply potential Vcc, and the fifth input terminal END is Connected to the high level output of the first counter 201 and its initial value is set to 'F' (hexadecimal); Is configured to output a high level count result (i.e., carry) when a high level count result is applied from the output unit 201, and the third counter 215 is provided in a period of the vertical synchronization signal converted into the hexadecimal number. The clock stage CLK is clock-controlled by the horizontal synchronizing signal so that the first input stage A3 is always connected to the ground potential GND, and the second through fourth input terminals B3, C3, and D3 are The second input terminal END is connected to the high level output of the second counter 207 and its initial value is set to 'E' (hexadecimal) so that the second counter 207 is connected to the power supply potential Vcc. And a hexadecimal count in accordance with the high level count result to output a high level count result (i.e., a carry). The vertical synchronizing signal of claim 1, wherein the second switching unit 100 of the pseudo synchronizing signal generating circuit unit 17 is connected to a vertical synchronizing signal, one end of which is separated from the image signal, and the other end of which is pseudo-generated. An exclusive logic sum gate 102 connected to the switching circuit and outputting the vertical synchronizing signal and the pseudo vertical synchronizing signal, and an inverter 104 for inverting the output of the exclusive logic sum gate 102. Pseudo synchronous signal generation circuit.