KR0152785B1 - Thin film transistor for lcd device - Google Patents
Thin film transistor for lcd deviceInfo
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- KR0152785B1 KR0152785B1 KR1019940035322A KR19940035322A KR0152785B1 KR 0152785 B1 KR0152785 B1 KR 0152785B1 KR 1019940035322 A KR1019940035322 A KR 1019940035322A KR 19940035322 A KR19940035322 A KR 19940035322A KR 0152785 B1 KR0152785 B1 KR 0152785B1
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- metal pattern
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- 239000010409 thin film Substances 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 43
- 239000010408 film Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000007743 anodising Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 239000007769 metal material Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 abstract description 15
- 238000002048 anodisation reaction Methods 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 14
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000010407 anodic oxide Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 210000001747 pupil Anatomy 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
Landscapes
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
본 발명은 액정표시소자용 박막트랜지스터의 제조방법에 관한 것으로, 기판상에 양극산화되지 않은 물질이나 투명전극 식각용 에천트에 강한 물질을 증착시킨 후 패터닝하여 제1게이트용 금속패턴을 형성하는 공정과, 상기 제1게이트용 금속패턴 위에 양극산화가 가능한 물질을 증착시킨 후 상기 제1게이트용 금속패턴의 폭보다 넓게 패터닝하여 제2게이트용 금속패턴을 형성하는 공정과, 상기 제2게이트용 금속패턴을 모두 양극산화시켜 양극산화막을 형성하는 공정을 포함하여 구성되며, 상기와 같이 양극산화되지 않는 물질이나 양극산화되더라도 투명전극 식각용 에천트에 강한 물질로 제1게이트용 금속패턴을 형성함으로써 절연신뢰성을 향상시킬 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor for a liquid crystal display device, the method of forming a first gate metal pattern by depositing a material that is not anodized or a strong material on an etchant for etching an transparent electrode on a substrate. And depositing a material capable of anodizing on the first gate metal pattern and patterning the material to be wider than the width of the first gate metal pattern to form a second gate metal pattern, and the second gate metal. And forming an anodization film by anodizing all the patterns, and insulating by forming the first gate metal pattern with a material that is not anodized as described above or a material resistant to an etchant for etching transparent electrodes even when anodized. There is an effect that can improve the reliability.
Description
제1도는 종래의 기술에 의한 액정표시소자용 박막트랜지스터의 제조방법을 도시한 단면도.1 is a cross-sectional view showing a method of manufacturing a thin film transistor for a liquid crystal display device according to the prior art.
제2도는 본 발명에 의한 액정표시소자용 박막트랜지스터의 제조방법을 도시한 단면도.2 is a cross-sectional view showing a method of manufacturing a thin film transistor for a liquid crystal display device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 기판 12 : 제1게이트용 금속패턴11 substrate 12 metal pattern for first gate
13 : 제2게이트용 금속패턴 13＇: 양극산화막13: metal pattern for second gate 13 ': anodization film
14 : 절연막 15 : 활성층14 insulating film 15 active layer
16 : 저항층 17 : 투명전극16 resistance layer 17 transparent electrode
18 : 소스/드레인용 금속패턴 19 : 보호막18: metal pattern for the source / drain 19: protective film
본 발명은 액정표시소자용 박막트랜지스터의 제조방법에 관한 것으로, 특히 케이트 전극의 절연신뢰성을 개선하기 위한 액정표시소자용 박막트랜지스터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor for liquid crystal display devices, and more particularly, to a method for manufacturing a thin film transistor for liquid crystal display devices for improving insulation reliability of a gate electrode.
일반적으로 액정표시소자용 박막트랜지스터나 대개의 반도체소자에서는, 게이트전극(워드라인)이나 배선금속이 전기전도도가 높고 접점에서의 저항성분이 작으며 실리콘이나 실리콘산화막에 잘부착되어 안정한 상태로 남아 있어야 하는 외에도 다른 여러 가지 조건을 만족시켜야 하는데, 알루미늄은 상기와 같은 조건 들을 어느 정도 만족시킬뿐만 아니라 경제적 측면에서도 유리하므로 가장 많이 사용되어 왔다.In general, in a thin film transistor or a semiconductor device for a liquid crystal display device, a gate electrode (word line) or a wiring metal has a high electrical conductivity, a small resistance component at a contact point, adheres well to silicon or a silicon oxide film, and remains stable. In addition to satisfying a number of other conditions, aluminum has been used the most because it not only satisfies the above conditions to some extent, but also advantageous in terms of economics.
그러나 상기 알루미늄은 막질이 거칠고 온도가 높아지게 되면 결정입자가 증가하므로 게이트 전극과 소스/드레인 전극 사이에 공정중에 발생할 수 있는 층간단락에 의한 화소결함이나 신호결함이 발생하는 문제점이 있다.However, the aluminum has a problem that pixel defects or signal defects occur due to interlayer short circuits that may occur during the process between the gate electrode and the source / drain electrodes because the crystal grains increase when the film quality is rough and the temperature increases.
따라서 종래에는 게이트를 절연시키기 위해 절연층을 두 번 적층시키거나 또는 양극산화가 가능한 금속층을 형성시킨 후 이를 일부 양극산화하고, 그 위에 다시 다른 절연층을 형성시키는 양극산화법을 주로 사용하였다.Therefore, in order to insulate the gate, conventionally, an anodization method is mainly used in which an insulating layer is stacked twice or an anodized metal layer is formed, followed by partial anodization, and another insulating layer is formed thereon.
제 1도는 이러한 양극산화법을 이용한 종래의 액정표시소자용 박막트랜지스터의 제조방법을 도시한 것으로, 이를 참조하여 설명하면 다음과 같다.FIG. 1 illustrates a conventional method for manufacturing a thin film transistor for a liquid crystal display device using the anodization method, which will be described with reference to the following.
먼저, 제1도의 (a) 및 (b)에서와 같이 절연기판(1) 위에 금속물질을 소정의 두께로 증착시킨 후 패터닝하여 제1게이트용 금속패턴(2)을 형성하고, 상기 제1게이트용 금속패턴(2) 위에 다시 금속물질을 증착시킨 후 패터닝하여 제2게이트용 금속패턴(3)을 형성한다.First, as shown in (a) and (b) of FIG. 1, a metal material is deposited on the insulating substrate 1 to a predetermined thickness, and then patterned to form a first gate metal pattern 2, and then the first gate. After depositing a metal material on the metal pattern 2 again, the metal material 3 is patterned to form a second gate metal pattern 3.
이때 상기 제 1 및 제 2게이트용 금속패턴(2),(3)을 이루는 물질은 순수한 알루미늄이나 약간의 실리콘 또는 구리가 첨가된 알루미늄이다.At this time, the material constituting the first and second gate metal patterns 2 and 3 is pure aluminum or aluminum to which some silicon or copper is added.
이어서, 제1도의 (c) 및 (d)에서와 같이 상기 제2게이트용 금속패턴(3)의 상부를 소정깊이까지 양극산화시켜 제1절연막(3')을 형성한 후 그 위에 실리콘 나이트라이드(SixNy)와 같은 절연물질을 증착시켜 제2절연막(4)을 형성한다.Subsequently, as shown in (c) and (d) of FIG. 1, the upper portion of the second gate metal pattern 3 is anodized to a predetermined depth to form a first insulating layer 3 ′, and silicon nitride is formed thereon. An insulating material such as (Si x N y ) is deposited to form the second insulating film 4.
그리고, 제1도의 (e)에서와 같이 상기 제2절연막(4) 위에 비정질실리콘과 불순물이 도핑된 비정질실리콘을 순차적으로 적층시킨 후 패터닝하여 활성층(5)과, 후속공정시 증착될 소스/드레인용 금속패턴과 접촉하는 저항층(6)을 형성하며, 상기 소스/드레인용 금속패턴과 전기적으로 접촉되어지도록 ITO로 투명전극(7)을 형성한다.As shown in (e) of FIG. 1, amorphous silicon and amorphous silicon doped with impurities are sequentially stacked on the second insulating film 4 and then patterned to form the active layer 5 and the source / drain to be deposited in a subsequent process. A resistive layer 6 is formed in contact with the quoted metal pattern, and a transparent electrode 7 is formed of ITO to be in electrical contact with the source / drain metal pattern.
마지막으로, 제1도의 (f)에서와 같이 상기 저항층(6) 및 투명전극(7)이 형성된 구조물 위에 다시 금속물질을 증착시킨 후 상기 저항층(6) 및 투명전극(7)과 접촉하도록 패터닝하여 소스/드레인용 금속패턴(8)을 형성한 다음 기판 전면에 보호막(9)을 형성한다.Finally, as shown in (f) of FIG. 1, a metal material is further deposited on the structure on which the resistive layer 6 and the transparent electrode 7 are formed, and then contacted with the resistive layer 6 and the transparent electrode 7. Patterning is performed to form the metal pattern 8 for the source / drain, and then a protective film 9 is formed on the entire surface of the substrate.
그러나, 이러한 양극산화공정을 사용하여 게이트 절연막을 이중으로 구성하는 방법도 상기 투명전극을 형성하기 위한 사진식각공정시, ITO식각 에천트(etchant)가 취약한 게이트용 금속패턴으로 스며들어가 양극산화되지 않은 부분의 알루미늄 또는 알루미늄을 주성분으로 하는 물질의 일부분을 용융시킴으로써 게이트 배선이 단선되거나, 기판과 양극산화된 절연막사이에 동공이 형성되므로 박막트랜지스터의 전기적 특성이 저하되는 문제점이 있었다.However, the method of dually forming a gate insulating film using the anodization process also does not anodize into the gate metal pattern in which the ITO etching etchant is weak during the photolithography process for forming the transparent electrode. By melting a part of aluminum or a part of a material mainly composed of aluminum, the gate wiring is disconnected or a hole is formed between the substrate and the anodized insulating film, thereby deteriorating the electrical characteristics of the thin film transistor.
따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여, 양극산화되지 않는 물질이나 양극산화되더라도 투명전극 식각용 에천트에 강한 물질로 제 1게이트용 금속패턴을 형성함으로써 ITO 에천트에 게이트 물질이 단선되는 것을 방지하고 게이트 전극의 절연신뢰성을 개선하며 박막트랜지스터의 전기적 특성을 향상시킬 수 있는 액정표시소자용 박막트랜지스터의 제조방법을 제공함에 목적이 있다.Therefore, in order to solve the above-mentioned problems, the present invention forms a gate material on the ITO etchant by forming a metal pattern for the first gate using a material that is not anodized or a material resistant to the transparent electrode etching etchant even if it is anodized. It is an object of the present invention to provide a method of manufacturing a thin film transistor for a liquid crystal display device which can prevent the disconnection, improve the insulation reliability of the gate electrode, and improve the electrical characteristics of the thin film transistor.
상기 목적을 달성하기 위한 본 발명의 액정표시소자용 박막트랜지스터의 제조방법은, 기판상에 양극산화되지 않는 물질이나 양극산화되더라도 투명전극 식각용 에천트에 강한 물질을 증착시킨 후 패터닝하여 제1게이트용 금속패턴을 형성하는 공정과, 상기 제1게이트용 금속패턴 위에 양극산화가 가능한 물질을 증착시킨 후 상기 제1게이트용 금속패턴의 폭보다 넓게 패터닝하여 제2게이트용 금속패턴을 형성하는 공정과, 상기 제2게이트용 금속패턴을 모두 양극산화시킨 후 절연막을 형성하는 공정을 포함하여 제조하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a thin film transistor for a liquid crystal display device according to an embodiment of the present invention may include: depositing a material that is not anodized on a substrate or a strong material on an etchant for etching an transparent electrode, even if anodized, and then patterning the first gate Forming a metal pattern for the second gate, forming a second gate metal pattern by depositing a material capable of anodizing on the first gate metal pattern, and then patterning the metal pattern wider than the width of the first gate metal pattern; And anodizing the second gate metal pattern to form an insulating film.
이하, 본 발명의 액정표시소자용 박막트랜지스터의 제조방법의 예시도인 제2도를 참조하여 상세히 설명한다.Hereinafter, a description will be given in detail with reference to FIG. 2 which is an exemplary view of a method of manufacturing a thin film transistor for a liquid crystal display device of the present invention.
제2도의 (a) 및 (b)에서와 같이 절연성 기판(11) 위에 Cr 이나 Ta과 같은 양극 산화되지 않는 금속물질이나 후속공정시 형성될 ITO 투명전극의 식각에천트에 강한 금속물질을 1500Å 이하의 두께로 증착시킨 후, 사진식각하여 제1게이트용 금속패턴(12)을 형성한다.As shown in (a) and (b) of FIG. 2, a metal material that is not anodized such as Cr or Ta or a strong metal material that is resistant to the etching etchant of the ITO transparent electrode to be formed during subsequent processing is formed on the insulating substrate 11. After the deposition to a thickness of the photo-etched to form a first gate metal pattern 12.
이때, 상기 제1게이트용 금속패턴(12)의 단면 테이퍼 각도는 45˚가 넘지 않도록 하며, 이어서 상기 제1게이트용 금속패턴(12) 위에 양극산화가능한 알루미늄 또는 알루미늄을 주성분으로 하는 물질을 1000Å 이하 또는 3000Å 이상의 두께로 증착시킨 후 그 폭이 상기 제1게이트용 금속패턴(12)의 폭보다 넓도록 사진식각하여 제2게이트용 금속패턴(13)을 형성한다.In this case, the tapered angle of the cross section of the first gate metal pattern 12 is not more than 45 °, and then, on the first gate metal pattern 12, an anodized aluminum or a material containing aluminum as a main component is 1000 Å or less. Alternatively, the second gate metal pattern 13 is formed by photo-etching such that the width is greater than the width of the first gate metal pattern 12 after the deposition to a thickness of 3000 Å or more.
그리고, 제2도의 (c)에서와 같이 상기 제2게이트용 금속패턴(13)을 완전히 양극 산화시켜 양극산화막(13')을 형성한다.As shown in FIG. 2C, the second gate metal pattern 13 is completely anodized to form an anodic oxide film 13 ′.
이어서, 제2도의 (d)로부터 제2도의 (f)에서와 같이 종래와 동일하게 상기 양극 산화막(13')위에 실리콘 나이트 라이드(SixNy)와 같은 절연물질을 증착시켜 절연막(14)을 형성하고, 상기 제2절연막(14) 위에 비정질실리콘과 불순물이 도핑된 비정질 실리콘을 순차적으로 적층시킨후 패터닝하여 활성층(15)과, 후속공정시 증착될 소스/드레인용 금속패턴(18)과 접촉하는 저항층(16)을 형성하며, 상기 소스/드레인용 금속패턴(18)과 전기적으로 접촉되어지도록 ITO로 투명전극(17)을 형성한 다음, 상기 저항층(16) 및 투명전극(17)과 접촉하도록 패터닝하여 소스/드레인용 금속패턴(18)을 형성하고, 마지막으로 기판 전면에 보호막(19)을 형성한다.Next, as shown in FIG. 2 (d) to FIG. 2 (f), an insulating material such as silicon nitride (Si x N y ) is deposited on the anodic oxide film 13 'as in the prior art. And sequentially deposit and pattern the amorphous silicon and the doped amorphous silicon on the second insulating layer 14, and pattern the active layer 15 and the source / drain metal pattern 18 to be deposited in a subsequent process. Forming a resistive layer 16 in contact, and forming a transparent electrode 17 with ITO to be in electrical contact with the source / drain metal pattern 18, and then the resistive layer 16 and the transparent electrode 17 ) To form a metal pattern 18 for source / drain, and finally to form a protective film 19 on the entire surface of the substrate.
이상에서와 같이 본 발명에 의하면, 기판상의 제 1게이트용 금속패턴을 양극 산화되지 않는 금속물질이나 ITO 투명전극의 식각에천트에 강한 금속물질로 형성한 후 양극산화막을 형성하므로, 투명전극용 식각에천트에 의한 게이트 전극물질의 용융과, 이로인한 게이트 배선의 단선 및 동공형성을 방지하고, 양극산화막에 의한 절연효과로 절연신뢰성을 향상시킬 수 있는 효과가 있다.As described above, according to the present invention, since the first gate metal pattern on the substrate is formed of a metal material which is not anodized or a metal material resistant to the etchant of the ITO transparent electrode, an anodization film is formed, thereby etching the transparent electrode. It is possible to prevent the melting of the gate electrode material by the etchant, the disconnection and the pupil formation of the gate wiring, and to improve the insulation reliability by the insulation effect by the anodization film.
Claims (2)
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| KR1019940035322A KR0152785B1 (en) | 1994-12-20 | 1994-12-20 | Thin film transistor for lcd device |
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| KR1019940035322A KR0152785B1 (en) | 1994-12-20 | 1994-12-20 | Thin film transistor for lcd device |
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| KR0152785B1 true KR0152785B1 (en) | 1998-10-01 |
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