KR950005488B1 - Making method of tft - Google Patents
Making method of tft Download PDFInfo
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- KR950005488B1 KR950005488B1 KR1019920020824A KR920020824A KR950005488B1 KR 950005488 B1 KR950005488 B1 KR 950005488B1 KR 1019920020824 A KR1019920020824 A KR 1019920020824A KR 920020824 A KR920020824 A KR 920020824A KR 950005488 B1 KR950005488 B1 KR 950005488B1
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- South Korea
- Prior art keywords
- metal
- layer
- forming
- thin film
- film transistor
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- 238000000034 method Methods 0.000 title claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 239000010409 thin film Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims description 17
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- 238000007743 anodising Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 230000008016 vaporization Effects 0.000 abstract 2
- 238000010030 laminating Methods 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 239000011521 glass Substances 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 229910018575 Al—Ti Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
제1도는 종래의 박막트랜지스터 구조 단면도.1 is a cross-sectional view of a conventional thin film transistor structure.
제2도는 본 발명의 박막트랜지스터 공정 단면도.2 is a cross-sectional view of a thin film transistor process of the present invention.
제3도는 본 발명 다른 실시예의 박막트랜지스터 공정 단면도.3 is a cross-sectional view of a thin film transistor process according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2a : 제1금속1 substrate 2a first metal
2b : 제2금속 3 : 제1절연막2b: second metal 3: first insulating film
4 : 제2절연막 5 : 반도체층4: second insulating film 5: semiconductor layer
6 : 오믹 접촉층 7 : 소오스/드레인 전극6 ohmic contact layer 7 source / drain electrode
본 발명은 반도체 소자에 관한 것으로 특히, 게이트 배선의 저 저항화 및 양질의 게이트 절연막을 얻을 수 있는 박막트랜지스터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a thin film transistor capable of reducing the resistance of a gate wiring and obtaining a high quality gate insulating film.
종래의 박막트랜지스터를 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the conventional thin film transistor with reference to the accompanying drawings as follows.
제1도는 종래의 박막트랜지스터 구조 단면도로써, 제조방법은 제1도(a)와 같이 유리기판(1)위에 양극 산화가 가능한 금속을 증착하고 패터닝하여 게이트 전극(2)을 형성하고 게이트의 저 저항화 및 게이트와 소오스/드레인간의 절연 불량을 방지하기 위하여 게이트 전극(2)을 양극 산화시켜 격리용 제1절연막(3)을 형성한 다음 전면에 제2절연막(4)을 CVD법법으로 형성한다. 이때, 게이트전극(2)으로는 A1, Ta, Mo-Ta등을 사용한다. 그리고 제2절연막(4)위에 비정질 실리콘 등의 반도체층(5)을 증착하고 게이트전극(2) 상측 영역의 부위에만 남도록 불필요한 부분을 제거한 다음, 반도체층(5) 위에 n+비정질 실리콘등의 오믹접총층(Ohmiccontact)(6)을 형성하고 금속을 증착하고 불필요한 부분을 제거하여 소오스/드레인 전극(7)을 형성하고 채널영역의 오믹 접촉층(6)을 제거하여 종래의 박막트랜지스터를 완성한다. 다른 방법으로 제1도 (b)와 같이 게이트 배선의 저항을 줄이기 위해 제1금속(2a)을 알루미늄 등으로 형성하고 제1금속(2a)을 감싸도록 제2금속(2b)을 증착하여 게이트전극(2)을 형성하고 제2금속(2b)의 표면을 양극산화하여 제1절연막(3)을 형성하였다. 이때 제2금속은 Ta를 많이 사용한다.FIG. 1 is a cross-sectional view of a conventional thin film transistor structure. In the manufacturing method, the gate electrode 2 is formed by depositing and patterning anodized metal on the glass substrate 1 as shown in FIG. In order to prevent poor insulation between the gate and the source / drain, the gate electrode 2 is anodized to form a first insulating film 3 for isolation, and then a second insulating film 4 is formed on the entire surface by the CVD method. At this time, A1, Ta, Mo-Ta, or the like is used as the gate electrode 2. Then, a semiconductor layer 5 of amorphous silicon or the like is deposited on the second insulating film 4, and unnecessary portions are removed so as to remain only in the region of the upper region of the gate electrode 2, and then an ohmic contact such as n + amorphous silicon or the like is formed on the semiconductor layer 5 The ohmic contact 6 is formed, the metal is deposited, and unnecessary portions are removed to form the source / drain electrodes 7 and the ohmic contact layer 6 in the channel region is removed to complete the conventional thin film transistor. Alternatively, as shown in FIG. 1 (b), in order to reduce the resistance of the gate wiring, the first metal 2a is formed of aluminum or the like, and the second metal 2b is deposited to surround the first metal 2a, thereby depositing the gate electrode. (2) was formed and the surface of the second metal 2b was anodized to form the first insulating film 3. At this time, the second metal uses Ta much.
그러나, 이와같은 종래의 박막트랜지스터에 있어서는 게이트 전극의 제2금속(2b) 물질로 Ta를 사용하여 이중 일부를 양극산화하여 게이트 절연막으로 사용하기 때문에 Ta의 비저항은 25 Ω㎝정도이고 Cr은 50Ω㎝정도로써 알루미늄(Al)에 비해 상당히 높고, 순수한 Al은 고온에서 힐록(hillok)이 발생하기 때문에 대면적의 TFT-LCD에서 박막트랜지스터로 사용하기에 적합하지 않는 문제점이 있다.However, in the conventional thin film transistors, since Ta is used as a gate insulating film by using a portion of Ta as the second metal (2b) material of the gate electrode, the specific resistance of Ta is about 25 Ωcm and Cr is 50 Ωcm. To some extent, considerably higher than aluminum (Al), since pure Al has high hillocks at high temperatures, it is not suitable for use as a thin film transistor in a large area TFT-LCD.
본 발명은 이와같은 문제점을 해결하기 위하여 안출한 것으로써 게이트 전극의 저 저항화 및 게이트 절연막을 양질화하여 대면적의 표시소자에 적당한 박막트랜지스터를 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to provide a thin film transistor suitable for a display device having a large area by lowering the resistance of the gate electrode and improving the quality of the gate insulating film.
이와같은 목적을 달성하기 위한 본 발명은 2층 구조의 게이트 전극을 형성하여 윗층의 전부 또는 기저층의 일부까지 양극산화하여 게이트 절연막을 형성한 박막트랜지스터이다.In order to achieve the above object, the present invention is a thin film transistor in which a gate insulating film is formed by forming a gate electrode having a two-layer structure and anodizing the entire upper layer or a part of the base layer.
상기와 같은 본 발명의 박막 트랜지스터의 제조 방법은 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.The manufacturing method of the thin film transistor of the present invention as described above will be described in more detail with reference to the accompanying drawings.
제2도는 본 발명의 박막트랜지스터 공정 단면도로써, 제2도(a)와 같이 유리기판(1)위의 소정의 부위에 알루미늄(Al) 등의 제1금속(2a)층을 증착하고 제2도(b)와 같이 제1금속층(2a)층 위에 알루미늄에 Ta, Si, Ti등이 합금된 제2금속(2b)층을 형성하여 게이트를 형성한다. 이때, 제1금속(2a)층과 제2금속(2b)층을 연속증착하고 패터닝하여도 무방하다. 제2도(c)와 같이 제2금속(2b)층을 양극산화하여 제1절연막(3)을 형성한다.FIG. 2 is a cross-sectional view of a thin film transistor process of the present invention, as shown in FIG. 2 (a), to deposit a layer of a first metal (2a) such as aluminum (Al) on a predetermined portion on the glass substrate 1, and FIG. As shown in (b), a gate is formed by forming a second metal (2b) layer in which Ta, Si, Ti, etc. are alloyed with aluminum on the first metal layer (2a). At this time, the first metal layer 2a and the second metal layer 2b may be continuously deposited and patterned. As shown in FIG. 2C, the first insulating layer 3 is formed by anodizing the second metal layer 2b.
제2도(d)와 같이 전면에 제2절연막(4)을 형성하고 비정질 실리콘 등의 반도체를 증착하고 불필요한 부분을 제거하여 게이트 상측 영역의 제2절연막(4) 위에 반도체층(5)을 패터닝한다. 그리고 제2도(e)와 같이 반도체층(5)위에 고농도 n+비정질 실리콘 등의 오믹 접촉층(6)을 형성하고 게이트를 중심으로 반도체층(5) 및 오믹 접촉층(6)상부양측에 각각 소오스/드레인 전극(7)을 형성하고 채널영역 부위의 오믹 접촉층(6)을 제거하여 본 발명의 박막트랜지스터를 완성한다.As shown in FIG. 2D, the semiconductor layer 5 is patterned on the second insulating layer 4 in the upper region of the gate by forming a second insulating layer 4 on the entire surface, depositing a semiconductor such as amorphous silicon, and removing unnecessary portions. do. As shown in FIG. 2 (e), an ohmic contact layer 6 such as high concentration n + amorphous silicon is formed on the semiconductor layer 5, and on both sides of the semiconductor layer 5 and the ohmic contact layer 6 around the gate. The thin film transistor of the present invention is completed by forming the source / drain electrodes 7 and removing the ohmic contact layer 6 in the channel region.
또한, 제3도의 본 발명 다른 실시예의 박막트랜지스터 공정 단면도로써, 본 발명의 다른 실시예의 박막트랜지스터 제조방법은 제3도(a)와 같이 유리기판(1)위에 알루미늄(Al) 등의 제1금속(2a)으로 게이트 전극을 형성하고 제3도(b)와 같이 전면에 Ta, Si, Ti등과 알루미늄이 합금된 제2금속(2b)을 증착하고 제2금속(2a)이 제1금속(2a)층을 감싸도록 포토에치 공정으로 패터닝한 다음, 제3도(c)와 같이 제1금속(2a)을 감싸고 있는 제2금속(2b)양극산화하여 제1절연막(3)을 형성한다. 그리고 제3도(d)와 같이 전면에 제2절연막(4)을 형성하고 제2절연막(4)위에 비정질 실리콘 등의 반도체층(4)을 증착하고 게이트 상측영역상에만 남도록 불피룡한 부분을 제거한 다음 제3도(E)와 같이 반도체층(5)위에 고농도 n형 비정질 실리콘등의 오믹 접촉층(6)을 형성하고 게이트를 중심으로 반도체층(5) 및 오믹 접촉층(6)양측상부에 소오스/드레인전극(7)을 형성하고 채널영역 부위의 오믹접촉층(6)을 제거하여 박막트랜지스터를 완성한다.3 is a cross-sectional view of a thin film transistor process according to another embodiment of the present invention, in which the thin film transistor manufacturing method of another embodiment of the present invention is a first metal such as aluminum (Al) on the glass substrate 1 as shown in FIG. (2a) forms a gate electrode and deposits a second metal (2b) alloyed with Ta, Si, Ti, etc. and aluminum on the front surface as shown in FIG. 3 (b), and the second metal (2a) is the first metal (2a). Patterned to cover the layer), and then anodized the second metal (2b) surrounding the first metal (2a) as shown in FIG. 3 (c) to form a first insulating film (3). As shown in FIG. 3 (d), a second insulating film 4 is formed on the entire surface, and a semiconductor layer 4, such as amorphous silicon, is deposited on the second insulating film 4, and an uneven portion is formed so as to remain only on the upper region of the gate. After the removal, as shown in FIG. 3E, an ohmic contact layer 6 made of a high concentration n-type amorphous silicon or the like is formed on the semiconductor layer 5, and the upper portions of both sides of the semiconductor layer 5 and the ohmic contact layer 6 around the gate. A source / drain electrode 7 is formed on the substrate, and the ohmic contact layer 6 in the channel region is removed to complete the thin film transistor.
이상에서 설명한 바와같이 본 발명의 박막트랜지스터에 있어서는 실재의 게이트로 알루미늄을 사용하여 게이트 배선의 저 저항화를 실현하고 알루미늄 위에 Al-Ta, Al-Si, Al-Ti등의 합금을 증착하므로 고온에서의 힐록발생을 방지하며 상기 합금을 양극산화하여 절연막을 형성함으로 양질의 절연성을 얻을 수 있어 대면적의 TFT-LCD에 적용하여도 신호지연등을 방지할 수 있는 효과가 있다.As described above, in the thin film transistor of the present invention, the resistance of the gate wiring is reduced by using aluminum as a real gate, and an alloy such as Al-Ta, Al-Si, Al-Ti is deposited on the aluminum at high temperature. It is possible to prevent the delay of the signal, and to prevent the delay of the signal even when applied to a large area TFT-LCD by obtaining an insulating film by anodizing the alloy to form an insulating film.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920020824A KR950005488B1 (en) | 1992-11-06 | 1992-11-06 | Making method of tft |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920020824A KR950005488B1 (en) | 1992-11-06 | 1992-11-06 | Making method of tft |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940012656A KR940012656A (en) | 1994-06-24 |
| KR950005488B1 true KR950005488B1 (en) | 1995-05-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920020824A KR950005488B1 (en) | 1992-11-06 | 1992-11-06 | Making method of tft |
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| Country | Link |
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| KR (1) | KR950005488B1 (en) |
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1992
- 1992-11-06 KR KR1019920020824A patent/KR950005488B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR940012656A (en) | 1994-06-24 |
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