KR0151253B1 - Assembly process reduced semiconductor device - Google Patents

Assembly process reduced semiconductor device

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Publication number
KR0151253B1
KR0151253B1 KR1019950026648A KR19950026648A KR0151253B1 KR 0151253 B1 KR0151253 B1 KR 0151253B1 KR 1019950026648 A KR1019950026648 A KR 1019950026648A KR 19950026648 A KR19950026648 A KR 19950026648A KR 0151253 B1 KR0151253 B1 KR 0151253B1
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KR
South Korea
Prior art keywords
chip
inner lead
paddle
semiconductor device
assembly process
Prior art date
Application number
KR1019950026648A
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Korean (ko)
Inventor
이준우
Original Assignee
문정환
엘지반도체주식회사
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Application filed by 문정환, 엘지반도체주식회사 filed Critical 문정환
Priority to KR1019950026648A priority Critical patent/KR0151253B1/en
Application granted granted Critical
Publication of KR0151253B1 publication Critical patent/KR0151253B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 반도체소자 제조용 조립 프로세스시 다이본딩 및 칩과 인너리드와의 전기적 열결이 동시에 수행되도록 하는 한편, 칩의 패드와 인너리드가 직접 접촉하도록 하여 와이어의 처짐 및 휩쓸림현상을 해소할 수 있도록 한 것이다.In the present invention, die bonding and electrical thermal bonding between the chip and the inner lead are simultaneously performed during the assembly process for manufacturing a semiconductor device, and the pad and the inner lead of the chip are in direct contact so as to solve the sagging and swept phenomenon of the wire. It is.

이를 위해, 본발명은 칩이 패들에 접착되도록 패들 위에 안착된 인너리드 사이에 접착제를 도포한 상태에서 상기 칩의 전기적 연결통로인 패드와 인너리드가 각각 접촉되도록 칩을 뒤집어 접착제 위에 부착하여서 된 조립 프로세서 감축형 반도체소자이다.To this end, the present invention is assembled by inverting the chip so as to contact the pad and the inner lead of the electrical connection path of the chip in contact with the adhesive on the adhesive while the adhesive is applied between the inner lead seated on the paddle so that the chip is bonded to the paddle It is a processor reduction type semiconductor device.

Description

조립 프로세스 감축형 반도체소자Assembly Process Reduction Type Semiconductor Device

제1도는 종래의 리드프레임 패들에 칩이 본딩된 상태를 나타낸 평면도 및 정면도.1 is a plan view and a front view showing a state in which a chip is bonded to a conventional leadframe paddle.

제2도의 (a) 내지(f)는 와이어 본딩공정의 과정을 순차적으로 나타낸 종단면도.(A)-(f) of FIG. 2 is a longitudinal cross-sectional view which shows the process of a wire bonding process sequentially.

제3도는 본발명에 따른 조립공정을 나타낸 정면도로서,3 is a front view showing an assembly process according to the present invention,

(a)는 패들 위에 인너리드가 안착되고 접착제가 도포된 후의 상태도.(a) is a state after the inner lead is seated on the paddle and the adhesive is applied.

(b)는 칩이 뒤집힌 상태로 접착완료된 후의 상태도.(b) is a state after the completion of the adhesion in the state in which the chip is turned upside down.

제4도는 (a) 및 (b)는 본발명에 따른 리드프레임의 다른 실시예를 나타낸 평면도 및 종단면도.Figure 4 (a) and (b) is a plan view and a longitudinal cross-sectional view showing another embodiment of a lead frame according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 칩 2 : 패들1: chip 2: paddle

3 : 인너리드 4 : 접착제3: inner lead 4: adhesive

6 : 홈6: home

본 발명은 조립 프로세스 감축형 반도체소자에 관한 것으로서, 더욱 상세하게는 반도체소자 제조를 위한 조립(Assembly)공정시 다이본딩 및 칩과 인너리드의 전기적 연결이 동시에 행해지도록 하여 와이어 본딩 공정 및 와이어가 생략될 수 있도록 한 것이다. 일반적으로, 조립 프로세스(Assembly Process)란 집적회로가 형성된 웨이퍼를 집적회로 칩으로 분리, 이것을 블라스틱 패키지나, 세라믹 패키지에 탑재하고 회로 기판에의 실장이 용이하도록 조립하는 것을 말한다. 또한, 이러한 조립 프로세스의 주된 목적은 기판이나 소켓에 실장하기 위한 형상의 확보와 기능보호에 있다고 할 수 있는데 집적회로의 고집적화에 따른 다핀화, 미세조립기술 그리고 실장형태의 다양화에 따른 패키지의 다종류화등, 조립 프로세스 기술로 이러한 변화추세에 따라 크게 변화하고 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an assembly process reduction type semiconductor device, and more particularly, a die bonding and an electrical connection of a chip and an inner lead are simultaneously performed during an assembly process for fabricating a semiconductor device, thereby omitting a wire bonding process and a wire. It would be possible. In general, an assembly process refers to separating a wafer on which an integrated circuit is formed into an integrated circuit chip and mounting it on a plastic package or a ceramic package and assembling the circuit board to facilitate mounting on the circuit board. In addition, the main purpose of the assembly process is to secure the shape and function protection for mounting on the board or socket. The multi-pinning, micro-assembly technology and package of the package due to the high integration of integrated circuits The assembly process technology, such as sorting, is changing greatly according to this trend.

한편, 종래에는 제1도 및 제2도에 나타낸 바와 같이, 반도체소자 제조를 위한 조립공정시 웨이퍼(도시는 생략함)에 형성된 다수의 집적회로 칩(1)을 개별로 분리하는 다이싱(Dicing)공정 후, 분리된 집적회로 칩(1)을 칩부착부인 리드프레임의 패들(paddle)(2) 위에 접착시키는 다이본딩(Die Bonding)공정을 실시하게 된다. 이때, 일반적으로 패들(2)과 칩(1) 사이에는 소자로부터의 발열이 적은 경우 에폭시수지를 접착제(4)로 많이 이용한다.Meanwhile, as shown in FIG. 1 and FIG. 2, dicing for dividing a plurality of integrated circuit chips 1 separately formed on a wafer (not shown) during an assembly process for manufacturing a semiconductor device. After the process, a die bonding process of bonding the separated integrated circuit chip 1 onto the paddle 2 of the lead frame as the chip attaching part is performed. In this case, generally, when there is little heat generation between the paddle 2 and the chip 1, an epoxy resin is used as the adhesive 4.

그리고, 상기한 바와 같이 다이본딩이 끝난 후에는 패들(2)위에 접착된 칩(1) 상면의 패드(pad)와 리드프레임의 인너리드(3a) 사이를 금선(Gold wire)(5)으로 연결하여 칩(1)과 인너리드(3a) 사이를 전기적으로 연결하게 되는데 이를 보다 상세히 설명하면 다음과 같다.Then, as described above, after the die bonding is completed, a gold wire 5 is connected between the pad on the upper surface of the chip 1 bonded on the paddle 2 and the inner lead 3a of the lead frame. The electrical connection between the chip 1 and the inner lead (3a) is described as follows.

먼저, 제2도의 (a)와 같은 상태에서 금선(5)이 중앙을 관통하는 캐필러리(capillary)(7)는 하강하여 칩(1) 상면의 패드에 본딩을 실시하게 된다(제2도의 (b)도)First, in the state as shown in FIG. 2A, the capillary 7 through which the gold wire 5 penetrates the center is lowered to bond to the pad on the upper surface of the chip 1 (FIG. (b) degrees)

그후, 캐필러리(7)는 제2도의 (c) 및 (d)에 나타낸 바와 같이 상승 및 좌우 이동한 후 다시 하강하여 제2도(e)에 나타낸 바와 같이 리드프레임의 인너리드(3a)에 2번째 본딩을 실시하게 된다.Thereafter, the capillary 7 is moved up and down and left and right as shown in (c) and (d) of FIG. 2 and then lowered again, and the inner lead 3a of the lead frame as shown in FIG. The second bonding will be performed.

2번째 본딩의 끝난 후에는 캐필러리(7) 상부의 글램퍼(8)가 금선(5)을 클램핑한 상태에서 캐릴러리(7)를 상승시켜 인너리드(3a)의 본딩부와 금선(3a)의 선단부를 단절시키게 된다. 한편, 상기한 본딩시에는 칩(1) 및 인너리드(3a)에 각각 열이 가해진 상태에서 금선(5)에 초음파진동(Ultrasonic Vibration) 및 압력이 가해져 접합을 돕게 된다.After the end of the second bonding, the clamper 8 on the upper part of the capillary 7 raises the carrier 7 while clamping the gold wire 5 so that the bonding portion and the gold wire 3a of the inner lead 3a are raised. ) Will break the tip. On the other hand, in the bonding, the ultrasonic wire (Ultrasonic Vibration) and pressure is applied to the gold wire 5 in a state where heat is applied to the chip 1 and the inner lead 3a, respectively, to assist the bonding.

그러나, 이와 같은 종래의 반도체소자 조립시에는 다이본딩공정과 와이어 본딩공정이 순차적으로 진철되어야만 하므로 상기 두 공정의 수행에 많은 시간이 소요될 수 밖에 없었다.However, since the die bonding process and the wire bonding process have to be carried out in order when assembling such a conventional semiconductor device, it takes a lot of time to perform the two processes.

또한, 다이본딩 공정후의 칩(1)과 인너리드(3a) 사이의 간격이 커서 와이어본딩시 칩(1)과 인너리드(3a)를 연결하는 금선(5)에 처짐(sagging)현상이 발생하게 되거나, 후공정인 몰딩공정시 캐비티(cavity)내로 주입되는 몰딩 수지에 의한 휩쓸림(Sweeping)현상이 발생하게 된다. 이에따라, 조립 프로세스를 마친 후 반도체소자의 전기적 특성에 이상이 발생하므로 인해 수율이 저하되는등 많은 문제점이 있었다. 본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 반도체소자 제조를 위한 조립 프로세스시 칩의 패드와 인너리드가 와이어 없이 직접 연결되도록 하여 와이어의 처짐현상 및 몰딩공정에서의 휩쓸림현상을 해소함과 동시에 다이본딩 및 칩과 인너리드와의 전기적 접속이 동시에 이루어질 수 있도록 한 조립 프로세스 감축형 반도체소자를 제공하는데 그 목적이 있다. 상시한 목적을 달성하기 위해 본발명은 칩이 패들에 접착되도록 패들위에 안착된 인너리드 사이에 접착제를 도포한 상태에서 상기 칩의 전기적 연결통로인 패드와 인너리드가 각각 접촉되도록 칩을 뒤집어 접착제 위에 부착하여서 된 조립프로세스 감축형 반도체소자이다.In addition, the gap between the chip 1 and the inner lead 3a after the die bonding process is large so that sagging occurs in the gold wire 5 connecting the chip 1 and the inner lead 3a during wire bonding. Or, the sweeping phenomenon caused by the molding resin injected into the cavity during the molding process, which is a post process, occurs. Accordingly, since the abnormality occurs in the electrical characteristics of the semiconductor device after completing the assembly process, there are many problems such as a decrease in yield. The present invention is to solve the above-mentioned problems, in the assembly process for manufacturing a semiconductor device so that the pad and the inner lead of the chip is directly connected without wire to solve the sagging of the wire and swept in the molding process and at the same time An object of the present invention is to provide an assembly process reduction type semiconductor device capable of simultaneously performing die bonding and electrical connection between a chip and an inner lead. In order to achieve the purpose of the present invention, the present invention is to turn the chip over the adhesive so that the pad and the inner lead of the chip is in contact with each other while the adhesive is applied between the inner lead seated on the paddle so that the chip adheres to the paddle. An assembly process reduction type semiconductor device attached thereto.

이하, 본발명의 일실시예를 첨부도면 제3도를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 3.

제3도는 본발명에 따른 조립공정을 나타낸 정면도로서, 칩(1)이 패들(2) 상면에 접착되도록 패들(2) 상면 양쪽으로 안착된 인너리드(3) 사이의 패들(2)면에 적당량의 접착제(4)를 도포한 후, 상기 접착제(4) 위에 칩(1)의 전기적 연결통로인 패드와 인너리드(3)가 접촉하도록 칩(1)을 뒤집어서 부착하여 구성된다.3 is a front view showing the assembling process according to the present invention, in which the chip 1 is adhered to the upper surface of the paddle 2, a suitable amount on the surface of the paddle (2) between the inner lead 3 seated on both sides of the upper surface of the paddle (2) After applying the adhesive (4) of the, it is configured to turn the chip (1) upside down so that the pad and the inner lead (3) is in contact with the electrical connection path of the chip (1) on the adhesive (4).

이와같이 구성된 본발명은 제3도에 나타낸 바와 같이, 반도체소자 제조를 위한 조립 프로세스시 패들(2) 상면으로 연장형성된 양측 인너리드(3) 사이의 패들 상면에 접착제(4)를 도포한다. 이때, 상기 인너리드(3)는 칩(1)의 패드에 각각 접촉하도록 연장 형성되며, 패들(2) 상면에 부착된다. 한편, 상기한 바와 같이 패들(2)상면의 인너리드(3) 사이에 접착제(4)가 도포된 후에는 다이싱된 칩(1)을 뒤집은 상태에서 칩(1)의 패드가 각 인너리드(3)이 일치하도록 맞춰 붙이게 된다. 따라서, 칩(1)의 패드가 인너리드(3)에 직접 접촉되어, 종래와 같이 금선(5)을 이용하여 이격된 인너리드(3)과 칩(1)의 패드를 본딩했을 때 발생하는 처짐(sagging) 또는 몰딩공정에서의 휩쓸림(sweeping)현상을 해소할 수 있게 되므로써 반도체소자의 불량을 줄여 수율을 향상시킬 수 있게 된다. 뿐만 아니라, 칩(1)을 패들(2)에 부착시키는 다이본딩공정과 칩(1)과 인너리드(3)를 연결하는 공정이 동시에 수행되므로 인해 패키지공정의 소요시간을 단축시킬 수 있으므로 인해 생산성을 향상시킬 수 있는 효과도 가져올 수 있게 된다.In the present invention configured as described above, as shown in FIG. 3, the adhesive 4 is applied to the upper surface of the paddle between the two inner leads 3 extending to the upper surface of the paddle 2 during the assembly process for manufacturing a semiconductor device. At this time, the inner lead 3 is formed to extend to contact the pad of the chip 1, respectively, and is attached to the upper surface of the paddle (2). On the other hand, as described above, after the adhesive 4 is applied between the inner leads 3 of the upper surface of the paddle 2, the pads of the chips 1 are turned on each inner lead in the state of inverting the diced chips 1. 3) are matched to match. Therefore, a deflection occurs when the pad of the chip 1 is in direct contact with the inner lead 3 and the pads of the inner lead 3 and the chip 1 spaced apart using the gold wire 5 as in the related art. By eliminating the sweeping phenomenon in the sagging or molding process, it is possible to reduce the defect of the semiconductor device and improve the yield. In addition, the die bonding process of attaching the chip 1 to the paddle 2 and the process of connecting the chip 1 and the inner lead 3 are simultaneously performed, thereby reducing the time required for the packaging process. It can also bring effects that can be improved.

한편, 상기 리드프레임의 패들(2) 위로 연장되는 인너리드(3)는 제4도에 나타낸바와 같이 패들(2)에 형성된 홈(6) 내에 삽입되어 인너리드(3)가 패들(2) 상면으로 돌출하지 않도록 형성할 수도 있다.Meanwhile, the inner lead 3 extending over the paddle 2 of the lead frame is inserted into the groove 6 formed in the paddle 2 as shown in FIG. 4 so that the inner lead 3 is placed on the upper surface of the paddle 2. It may be formed so as not to protrude.

또한 상기 인너리드(3)에는 전도성이 좋은 금속물질을 입혀 칩(1)의 접착시 칩(1)의 패드와 인너리드(3)와의 전기적 접촉이 원활히 이루어지게 할 수 있다.In addition, the inner lead 3 may be coated with a metal material having good conductivity so that electrical contact between the pad of the chip 1 and the inner lead 3 may be smoothly performed.

이상에서와 같이, 본 발명은 반도체소자 제조용 조립프로세스시 다이본딩 및 칩(1)과 인너리드(3)와의 전기적 연결이 동시에 수행되도록 하는 한편, 칩(1)의 패드와 인너리드(3)가 직접 접촉하도록 하여 와이어의 처짐 및 휩쓸림현상을 해소할 수 있으므로 인해 반도체소자 조립공정의 생산수율을 향상시킨 매우 유용한 발명이다.As described above, the present invention allows the die bonding and electrical connection between the chip 1 and the inner lead 3 to be simultaneously performed during the assembly process for manufacturing a semiconductor device, while the pad and inner lead 3 of the chip 1 It is a very useful invention that improves the production yield of the semiconductor device assembly process because it can eliminate the sagging and swept phenomenon of the wire by direct contact.

Claims (3)

칩이 패들에 접착되도록 패들 위에 안착된 인너리드 사이에 접착제를 도포한 상태에서 상기 칩의 전기적 연결통로인 패드와 인너리드가 각각 접촉되도록 칩을 뒤집어 접착제 위에 부착하여서 됨을 특징으로 하는 조립 프로세스 감축형 반도체소자.Assembly process reduction type, characterized in that the chip is inverted and attached on the adhesive so that the pad and the inner lead of the chip is in contact with each other while the adhesive is applied between the inner lead seated on the paddle to adhere the chip to the paddle. Semiconductor device. 제1항에 있어서, 상기 패들에 형성된 홈에는 연장형성된 인너리드가 패들 상면으로 돌출되지 않도록 삽입 설치되는 조립 프로세스 감축형 반도체소자.The assembly process reduction type semiconductor device of claim 1, wherein the groove formed in the paddle is inserted and installed such that an extended inner lead does not protrude to an upper surface of the paddle. 제2항에 있어서, 상기 인너리드에는 인너리드와 칩의 패드와의 통전선을 향상시키기 위해 전도성이 좋은 금속물질이 도포되는 조립 프로세스 감축형 반도체소자.The semiconductor process reduction type semiconductor device according to claim 2, wherein the inner lead is coated with a conductive metal material to improve the conduction line between the inner lead and the pad of the chip.
KR1019950026648A 1995-08-25 1995-08-25 Assembly process reduced semiconductor device KR0151253B1 (en)

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