KR0148723B1 - Integrated circuit parallel test system & method using test machine having single module structure - Google Patents

Abstract

In the logic device inspection equipment having a single module structure including several voltage / current sources, the inspection board is changed to a dual inspection board, and the measurement part of the processor can be changed to allow two logic devices to pass through, and a quad op amp can be measured. Power supply by connecting voltage / current supply pins in parallel so that four single operational amplifiers and two dual operational amplifiers can be set during the hardware setup time of the power supply and test equipment for a single logic integrated circuit. Supply.

Description

Integrated Circuit Parallel Inspection System and Method Using Inspection Equipment with Single Module Structure

1 is a schematic diagram of an inspection system using the A360 integrated circuit inspection equipment of TERADYNE, USA having a conventional single module structure.

2 is a flow chart of the inspection process by conventional integrated circuit inspection equipment.

3 is a test circuit diagram of a dual operational amplifier using a test substrate (DUT) according to the prior art.

4 is an inspection circuit diagram for simultaneously examining two dual operational amplifiers in parallel using an inspection substrate having a structure suitable for use in the present invention.

5 is a schematic representation of a matrix having a structure suitable for practicing the present invention.

6 is a flowchart of a parallel inspection method according to the present invention.

* Explanation of symbols for main parts of the drawings

10: A360 inspection equipment 12: terminal

14: main frame 16: extended frame

18: Inspection substrate (DUT) 19: Processor

Sx: power terminal GND: ground terminal

XPI-XP48: Matrix terminal VM1, VM2: Volt meter terminal

OPx: op amp 50: voltage current source

52: matrix BINx: test result output signal

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to inspection of semiconductor integrated circuits, and more particularly, to an inspection system and an inspection method capable of inspecting integrated circuits in parallel using an integrated circuit inspection system having a single module structure.

[Private Technology]

Parallel test is widely applied in logic test equipment (including memory test equipment) or mixed signal test equipment that can test by applying signals on a pin basis to check the electrical characteristics of the integrated circuit (IC). It is becoming. However, test equipment with a single module structure, especially analog test equipment with multiple power sources, cannot simultaneously test multiple IC devices of the same pin configuration or function, but only one at a time.

1 is a schematic diagram of an inspection system using a conventional single-module inspection equipment, such as the A360 LSI inspection equipment of TERADYNE, USA. The A360 inspection equipment 10 is a device capable of analyzing and mass-producing an analog LSI device, and is mainly composed of a terminal 12, a main frame 14, and an expansion frame 16. Although not specifically shown in the drawings, the main frame 12 is composed of a computer driven by software for controlling the inspection equipment and a voltage / current source for supplying ± 60 V / ± 200 mA. The expansion frame 16 is a hardware for inspecting a single operational amplifier (OP AMP), a dual operational amplifier, a quad operational amplifier, a comparator buffer, etc., and an RB101 substrate having four channels, and driving a digital signal. Digital module for detection and detection, analog module capable of applying and measuring analog signals from 0 to 256KHz, and measurement module for measuring very fine DC levels with an accuracy of 0.004% and outputting ± 13.1V / ± 20mA And a time meter that measures the width of the signal on the time axis and has a built-in noise suppression filter. The terminal 12 is composed of a monitor, a control panel, and the like.

The inspection is performed by inserting an integrated circuit device to be inspected into a device under test (DUT) board. The substrate 18 includes an application circuit suitable for measuring electrical characteristics of the circuit device. . The handler 19 automatically inserts the IC to be inspected into the inspection substrate 18 or automatically classifies the IC after inspection as pass / fail.

By the way, IC inspection by such inspection equipment inspects IC one by one as shown in the flowchart of FIG. After the IC is inserted into the inspection board (20), the test equipment is powered on and the instrument is set up to be ready for inspection by giving an initial value necessary to inspect a specific IC (22). After a certain set time has elapsed in response to the power supplied to the IC or for the test equipment to operate stably for a given condition (24), the test equipment checks the IC according to a certain program and measures the output value ( 26). If the output value is within the acceptable range, the IC is classified by treating it as good and otherwise treating it as reject (28). After the inspection of one IC is completed, the process proceeds to inserting another IC again.

The inspection process according to the prior art uses a concept of a single pin (per pin) that allows the application and measurement of a signal to a single pin, so that inspection of one IC at a time takes a long time and productivity to set up each IC. There is a downside to falling. In particular, in the entire inspection flow shown in FIG. 2, the time to set up the test equipment and measure the output value is very short (10%) while the time to set time takes about 90%.

Accordingly, an object of the present invention is to apply a parallel inspection program to the inspection equipment having a single module structure, especially the logic device inspection equipment with a plurality of built-in power source, the hardware setting time such as the relay during the IC inspection time and the setting time by the power source By setting two ICs at one IC setting time, the inspection time is shortened, and during the inspection, the defective IC stops the inspection and inspects only good ICs to maximize productivity.

In order to achieve this object, in the present invention, the structure of the DUT is changed from a single test board to a double test board, and two ICs can pass through only one IC in the test unit of the processor. The software that drives the mainframe's computer has been changed to suit the needs of the computer.

In the present invention, a change part of the present invention is that one or two channels among four channels of the RB101 substrate of the extended frame (14 of FIG. 1) are used, particularly in the case of a low pin IC such as a single operational amplifier or a dual operational amplifier. It is aimed at achieving the objective of this invention by raising its utilization as it focused on that it is not. In the RB101 board, four channels can be set simultaneously and measured sequentially from channel 1 to channel 4. That is, in FIG. 2, the power and hardware setup step 22 and the setting time elapsed step 24 are simultaneously set by four channels, and the output value measuring step 26 measures sequentially from channel 1 to channel 4. Structurally, the setting part is dual concept and the measuring part is single and the ratio of both is 50 to 50. However, when observed on the time axis, it takes 90% of time to power up the device to be inspected and stabilize the inspection system as described above. It takes up 10% of the time to measure the actual output value, and it is possible to improve productivity by dualizing 90% of the occupied market.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

3 is a test circuit diagram using a DUT according to the prior art. Matrix terminals XP2, XP1, XP5, XP4 to which the dual operational amplifier OP1 / OP2 is mounted on the inspection board (DUT) and to which the voltage / current sources S1, S2, S3 and S4 of the matrix of the inspection equipment are connected and the terminal D2 of the inspection board Connect D3, D6, and D5 to supply proper power. Substrate power supplies S5 and S6 are supplied to the board terminals D8 and D4, respectively. The output values coming from terminals D1 and D7 are measured at XP3 and XP6 to check the electrical characteristics of the dual operational amplifiers for good or bad judgment.

4 is a test circuit diagram using a DUT having a structure suitable for use in the present invention. Two dual operational amplifiers OP1 / OP2 and OP3 / OP4 are mounted by arranging the test substrate having the same structure as that of FIG. However, the pin function and role of the op amp are the same, so that the matrix terminals XP1, XP2, XP4, XP5 to which the voltage / current source terminals S1, S2, S3, and S4 of the test equipment are connected are different from the matrix terminals XP7, XP8, XP10, XP11. Can be connected simultaneously to supply power. Thus, two op amps can be set during the set-up time required to measure one op amp, saving equipment setup time.

5 is a schematic diagram of a matrix having a structure suitable for practicing the present invention. Terminals S1, S2, S3, S4, S9, and GND of the voltage current source 50 are power supply terminals, and VM1 and VM2 are terminals used as volt meters. There are 48 pins in the matrix 52, from XP1 to XP48, 24 in each of two 8-line by 24 matrix boxes (not shown). Matrix pins XP1-XP48 will be connected to the terminals of the integrated circuit mounted on the circuit board for inspection.

The switch is located at the intersection of the line from the terminal of the voltage current source 50 and the line from the matrix pins XP1-XP48. The switch consists of a relay, allowing automatic control. Voltage current source terminals S1, S2, S3, S4, S9, ground terminal GND and measuring terminals VM1, VM2 can be connected simultaneously to XPx (x = 1, 2, 3,…, 48). For example, S1 can be connected to both XP1-XP48 simultaneously or only to specific matrix pins. As shown in FIG. 3, when S1 is connected to XP1, a single inspection structure is used, and when XP1 and XP7 are simultaneously connected and used as shown in FIG.

6 is a flowchart of a parallel inspection method according to the present invention. First of all, it is necessary to drive and supply the hardware driving on the inspection equipment and the inspection board in order to perform the inspection. As described with reference to FIG. 4, not only one IC but also two ICs can be driven simultaneously. Then set time for stability of the hardware and power. In this case, give only one set time of one IC, and then measure the output by measuring two ICs sequentially without setting time.

Referring to FIG. 6, after the two ICs are mounted on the test board and the setting time for one IC has elapsed (60), a parallel test program A can be used to test two ICs simultaneously and compare output values. Check (62). If both ICs are good, output a BIN 1 signal and then proceed in the same way as previously described for the IC to be tested. If only the second IC is good and the first IC is defective, BIN 15 is output and the second IC is inspected using the second IC test program B (64). As a result, if the second IC is also defective, it outputs BIN 9 to indicate that all the tested ICs are defective, and if the second IC is good, it outputs BIN 3. As a result of the parallel inspection program A, if the second IC is good and the first IC is defective, BIN 25 is output and the inspection is performed using the first IC inspection program C (66). As a result, if the first IC is also defective, it outputs BIN 9 as before, indicating that all the tested ICs are defective, and outputs BIN 2 if the first IC is good.

As can be seen from the above description, when BIN 15 or BIN 25 is outputted, two ICs can be directly inspected without first setting the hardware of the test equipment to check the second or first IC. It can be seen that it only takes time to set up one IC to check for.

Table 1 below is a chart comparing the results of testing the dual operational amplifiers KA358 and KA4558 by applying the parallel test program according to the present invention described above with the results of the test by the conventional test program.

As shown in the table above, when the inspection program according to the present invention is applied, the inspection time of the KA 358 is reduced by about 37% compared to when applying the conventional program, and the KA 4558 is reduced by about 40%. It can be seen that the inspection time is reduced. In addition, even if 50 inspections are performed in one head, the inspection efficiency can be improved by 45% for KA 358 and 41% for KA 4558.

In addition, in order to investigate the possibility of the parallel program according to the present invention, there was no IC that the yield was 100% as a result of re-inspecting the device treated as good in the inspection using the parallel program using the existing inspection program. As a result of re-inspecting the IC processed as a result of the inspection by applying the existing inspection program according to the present invention, all the defective ICs are selected and it can be seen that even if the present invention is applied, there is no significant difference in the inspection data and can be applied to mass production. there was.

Claims (5)

An integrated circuit inspection method for inspecting electrical characteristics of an integrated circuit, the method comprising: inserting at least two integrated circuits into an inspection substrate, applying voltage / current to the integrated circuit at the same time, and setting inspection equipment for a predetermined time; Simultaneously inspecting the electrical characteristics of the integrated circuit; if only one integrated circuit is defective in the simultaneous inspection step; inspecting only the remaining integrated circuit; and the remaining integrated circuit is defective in the simultaneous inspection step. In the case of inspecting only one integrated circuit, and outputting a first result value when the two integrated circuits are good in the simultaneous inspection step, and in the step of inspecting only the remaining integrated circuits If the integrated circuit is a good product, outputting a second result value and inspecting only the one integrated circuit; If the integrated circuit is a good product, outputting a third result value; inspecting only the remaining integrated circuits; if the remaining integrated circuits are defective; and inspecting only the one integrated circuit; And outputting a fourth result value when the circuit is defective, and classifying the integrated circuit as good or bad according to the first to fourth result values. The method of claim 1, wherein the integrated circuits are integrated circuits having the same pin configuration and function, and the pins having the same function are connected in parallel with each other. An integrated circuit inspection system, comprising: an inspection substrate on which the integrated circuit is mounted, a) a main frame having a voltage / current source for supplying predetermined power to an integrated circuit mounted on the substrate, and a control means for controlling a drying process And b) a digital module for driving and detecting a digital signal, an analog module capable of applying and measuring analog signals, a measurement module for measuring a DC level, a time meter for measuring the time value of a signal, and a single operation. An inspection apparatus having an expansion frame having a substrate for measuring an amplifier, a dual operational amplifier, a quad operational amplifier, a comparator, a buffer, etc., a loading unit for mounting an integrated circuit to the inspection substrate, and A measuring unit for measuring an output value, and an unloading unit for classifying an integrated circuit as good or bad according to the measured value of the measuring unit. Integrated circuit inspection system having a retractor. 4. The integrated circuit inspection system according to claim 3, wherein one integrated circuit passes at a time in the loading and unloading sections of the processor and two integrated circuits pass at a time in the measurement section. According to claim 3, wherein the test board is equipped with two integrated circuits having the same pin configuration and function at the same time and the power pins of the two integrated circuits are connected in parallel to each other connected to the voltage / current source of the test equipment. Integrated circuit inspection system.