JPH0235382A - Preparing method of inspection program for integrated circuit and inspecting method of integrated circuit - Google Patents

Abstract

PURPOSE:To design a test pattern program easily and quickly by a method wherein measurement programs divided into a plurality of element programs beforehand are combined appropriately in accordance with IC to be inspected. CONSTITUTION:LSI to be inspected is divided into blocks B1 to Bn in the number of (n). L1 to Ln in the blocks B1 to Bn are made to be standardized LSIs or LSIs for which a test program can be set simply, respectively, and they are connected by gates G1 to Gn. An inspection program for the LSI is constituted of inspection programs for the LSIs L1 to Ln and of inspection programs for checking up connections between the gates G1 to Gn and the LSIs L1 to Ln. When the LSI L1 is tested, the gates G1 and G2 are opened and checking is made by the inspection program corresponding thereto. Then, the LSIs L2 to Ln are checked likewise, and lastly the connection of the gates G1 to G2 is checked.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a method for creating a test program for an integrated circuit such as a custom IC, and a method for testing an integrated circuit.

(Prior art) In general, tests for ICs under test include DC tests that evaluate direct current characteristics such as input/output current, input/output voltage, and power supply, AC tests that examine time axis characteristics, and patterns of logic symbols that change over time. Dynamic functional test 1-1 consists of various tests such as static functional test, which inputs logic symbols that do not change over time and evaluates their output characteristics. . It is customary to set a complex test pattern corresponding to the IC to be tested in advance, store it in a file system connected to the tester, and load the above test pattern program each time the test is performed. be.

In recent years, custom ICs such as gate arrays have spread rapidly, and ICs are becoming more complex and individualized to meet needs.However, even in the inspection of such custom ICs, the conventional inspection LSI button design Even when creating a complex test LSI pattern using a CAD system, it takes many days to create the test program, and depending on the content, it may be impossible. Occur.

Also, at the station for testing in accordance with item 2, a tester is connected to the input/output terminals of the IC to be tested, and testing is performed according to the test program described above.

(Problem to be solved by the invention) However, in the current situation where custom ICs are becoming more highly integrated and individualized to meet customer needs, it is already extremely difficult to design inspection patterns that correspond to individual custom ICs. , even if a CAD system is used, the time and
There is a problem that it is not possible to cope with the cost, and it requires a huge amount of testing cost.

In addition, custom ICs are becoming more highly integrated and complex, and testing pattern design is also becoming more difficult, creating the problem that it is almost impossible to achieve this goal.

The present invention was invented in view of two actual circumstances, and it facilitates the design of patterns for ICs to be tested, and is capable of testing integrated circuits that can sufficiently support even higher integration such as custom ICs. The purpose is to provide a method and a method for creating an inspection program for the same.

(Means for Solving the Problems) In order to solve the two problems, the present invention divides a measurement program for an IC to be tested into a plurality of element programs and stores them in advance. A method was adopted in which a measurement program for the IC to be tested could be set by appropriately selecting and combining each element program.

Furthermore, in testing integrated circuits, a method has been adopted in which the measurement area of the pattern of the IC to be tested is divided into a plurality of areas and each measurement area is inspected. It is preferable to inspect the connections between the measurement areas divided in this way separately from the second measurement area.

Furthermore, in testing integrated circuits, in order to perform testing without deteriorating the AC test characteristics of the IC under test in response to multiple divisions of the measurement area of the pattern of the IC under test,
In order to set up a buffer circuit with a low load capacity at the shortest distance from the measuring needle in the input section of the tester, we adopted a test circuit configuration method in which a test buffer element was mounted on a test probe card assembly.

(Function) Since the measurement area of the pattern of the IC to be inspected is divided into a plurality of areas, the degree of integration of the patterns in each measurement area is relatively gradual and uniform. A measurement program corresponding to the IC to be tested can be created by appropriately selecting and combining various test patterns, and the test can be performed using the created 81 standard program. Therefore, even if it is a custom IC, it is possible to quickly set up an inspection program, and it is possible to perform inspections that respond to requests immediately. No need to design.

Incidentally, since the inspection of the connection portion between the divided patterns is only to check for continuity, the programming thereof is also very simple.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an LSI pattern divided into n pieces in an integrated circuit according to an embodiment of the present invention;
, , B2...Bn circuits.

At this time, L□, B2,...Ln of each block B1, B7,...Bn are each standardized, that is, set by an LSI that has already been registered as an element circuit or by a simple test program. A possible LSI. G...
G2...Gn is LSI Ll, B2 of each block.
...Used as a gate circuit to set the output side to oven when testing Ln.

When testing LSIL, game 1 to G+, +62
When opening LSIB2 and testing LSIB2, use GetG, G3
open. Similarly, other LSIL3゜B4...L
As for n, each peripheral gate circuit is opened and a test is performed. Therefore, the creation of a test program for Ls to be inspected is as follows: ■ Element circuit L1 and gate circuit G, G2, ■ Element circuit L2 and gate circuit G, G, G3, ■... It will be completed if you create it. Moreover, if necessary, it is possible to set only the test program for the static function tests 1 to 1 of the LSI to be tested so as to be able to check the connections between each block.

Next, when executing Test 1 according to the test program set above, the des1-program of each block of the LSI to be tested can be quickly executed, and if necessary, it can be freely selected according to the user program. is important. FIG. 2 shows a system diagram of a tester including file connections of test programs according to the present invention.

In the figure, T1 is the main processor of the tester, T3. T4 is a file unit for the test l~program. T2 is a program editing CPU unit, which is operated and displayed by a terminal connected to it. The test program pattern processed by T□ is sent to a pattern generator T5, further converted into a pattern corresponding to each test pin, and sent to the driver/comparator unit 1-T6. This driver/compacitor unit T6 is generally installed near the LSI to be tested, drives the LSI, and receives its output signal. In the case of this embodiment, the test program for the LSI to be tested is collectively filed in T4, and the format is such that data can be transferred at high speed through a bus connection to T4. In addition, the file unit 1-T3 is a multi-product LSI.
File test programs for multiple products as required.

When testing the LSI under test according to the test program of the present invention according to the above embodiment, the file data of T4 is called at T according to the user program set at T2, and the test program for each block is sequentially read. It will be transferred to T5.

FIG. 3 shows an example of a schematic sequence flowchart on the tester side when wafer testing 1 to 1 is executed on the Unihub 0-ba according to the testing method of the present invention, and one test target LS
When testing I (device), block B x,
, B2...Bn indicates that each divided element circuit is sequentially tested by the element test program divided into Bn. Block B1. B2...Bn
Execute the test in this order, and open the gate circuits around each element circuit each time to prevent electrical influence from surrounding circuits. After the test of block Bn is completed, an inter-block connection program is run using only the input/output pins of the LSI, and function test 1 is executed. This completes the test of one device LSI.

When testing an integrated circuit according to the concept of the present invention, the higher the degree of integration of the pattern of the LSI to be tested, the more effective the creation of a test program and the measures taken when a problem occurs during testing. In this case, Bj,,B
The input/output terminals for testing the element circuits classified into 2...Bn are naturally set within the internal pattern on the wafer, and furthermore, the load capacity during testing is limited. The limit value of this load capacity is determined by the standard of the circuit, and is determined by each block B1. B2...Bn eggplant 1-
In addition to suppressing the ringing phenomenon of the output, this is to prevent the test results from being affected when performing the function tests 1 to 1 of the completed LSI.

FIG. 4 is a schematic structural diagram of the LSI to be tested in a wafer test. In the figure, 1 is a tester driver/comparator unit (test head), 3 is a card adapter/
- Arashi, 4 is a probe card, which shows that the tip of the probe card 4 contacts the LSI wafer 5 that is vacuum-tighted to the sample stage 6 installed on the XYZO stage 7 of the wafer prober. in this case,
Generally, the wiring length from the end of the probe card 4 to the connector of the pin electronics card 1-1 in the driver/comparator unit 1 is about 60 to 80 cm. Therefore, although there are differences depending on the wire material used, the equation 1. OF
It is unavoidable that the line capacity of F is loaded. In this embodiment, this load capacity is set to a maximum of 10PF, approximately several P
In order to suppress F, several hundred buffer elements 3-3 were mounted on the card adapter array 3 shown in FIG. 4, thereby reducing the load capacity when looking at the tester side from the tip of the probe card 4. As mentioned above, in order to divide and test the IC to be tested by dividing it into multiple parts, it is necessary to set up a test bat inside the LSI to be tested and connect a tester to those pads for testing. LS to be inspected
In order to perform the AC test without deteriorating the characteristics of the AC test, it is effective to set such a buffer circuit with a low load capacity at the shortest distance from the measurement pin of the input section of the tester.

In the figure, 3-1 is a pogo pin board that contacts the performance board 2 on the test head side, 3-2 is a wiring arrangement that is wired according to the type of device to be tested (LSI under test), and 3-4 is a pogo pin board that contacts the performance board 2 on the test head side. is a connector board to which the probe card 4 is tangentially connected, and the buffer element 3-
3 is specifically mounted on the connector board 3-4.

In this way, by setting the car 1-adapter arrangement 3 in the structure shown in FIG. 4, it becomes possible to test the inside of the pattern with satisfactory performance.

As is clear from the detailed explanation of the invention, according to the method of the present invention, complicated and individualized ICs to be measured, such as custom ICs, etc.
However, it becomes extremely easy to design a test pattern program for the IC under test, and it becomes possible to create it quickly. In addition, the configuration of the tester and the cart adapter/
By setting the test results according to the method of the present invention, stable test results can be obtained. Therefore, custom I
It has the effect of being able to sufficiently handle and test even higher integration of integrated circuits such as C and the like.

[Brief explanation of the drawing]

FIG. 1 is a circuit system diagram showing an embodiment of a circuit system in which an LSI to be tested is divided according to the present invention, FIG. 2 is a system diagram showing an embodiment of a tester system according to the present invention, and FIG. An example of a schematic sequence flowchart of a wafer test of an LSI to be tested in , and FIG. 4 is a schematic diagram of the main parts around the LSI to be tested in wafer tests 1 to 1. L1+L2”...Ln; Element circuit, G1.G2
...Gm; Peripheral gate circuit of each element circuit, B, -
, B 2...Bn; divided block, T,...
Main processor, T2...Editing CPU, T3
...Total test program file unit,
T4...Test program file unit for LSI under test, T5...Pattern generator, T6...
...Driver/comparator unit, 1...Driver/comparator unit (test head), 2.
...Performance pod, 3...Card adapter/arashii, 3-1...Pogo pin board, 3-2
... Wiring arrangement corresponding to the product type, 3-3 ... Mounting buffer element, 3-4 ... Connector board, 4 ...
...Probe card, 5... LSI wafer to be tested, 6
...Sample stage, 7...xyzθ stage.

Claims (3)

[Claims] (1) The measurement program for the IC to be tested is divided into multiple element programs and stored in advance, so that the measurement program for the IC to be tested can be set by combining each element program as appropriate depending on the IC to be tested. How to create a test program for integrated circuits. (2) A method for testing an integrated circuit, in which the measurement area of a pattern of an IC to be tested is divided into a plurality of areas, and each measurement area is inspected. (3) A method for configuring a test circuit in testing an integrated circuit, in which a test buffer element is mounted on a test probe card assembly corresponding to a plurality of divisions of the measurement area of the pattern according to claim 2.