KR0119966B1 - Forming method of interlayer insulating films in the semiconductor device - Google Patents
Forming method of interlayer insulating films in the semiconductor deviceInfo
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- KR0119966B1 KR0119966B1 KR1019940011483A KR19940011483A KR0119966B1 KR 0119966 B1 KR0119966 B1 KR 0119966B1 KR 1019940011483 A KR1019940011483 A KR 1019940011483A KR 19940011483 A KR19940011483 A KR 19940011483A KR 0119966 B1 KR0119966 B1 KR 0119966B1
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- interlayer insulating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1a 및 제1b도는 종래 반도체 소자의 금속층간 절연막 형성방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a method for forming an interlayer insulating film of a conventional semiconductor device.
제2a 및 제2b도는 본 발명에 따른 반도체 소자의 금속층간 절연막 형성방법을 설명하기 위한 소자의 단면도.2A and 2B are cross-sectional views of a device for explaining a method for forming an interlayer insulating film of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 2 : 불순물 영역1: silicon 2: impurity region
3 : 절연막 4 : 제1금속층3: insulating film 4: first metal layer
5 : 제1 IMO 6 : SOG 막5: first IMO 6: SOG film
7 : 제2 IMO 8 : 제2금속층7: second IMO 8: second metal layer
9 : 제1보호막 10 : 제2보호막9: first protective film 10: second protective film
본 발명은 반도체 소자의 금속층간 절연막 형성방법에 관한 것으로, 특히 보호막(passivation)으로 사용되는 플라즈마 질화막(plasmanitride)형성시 하부층으로 침투되는 H+이온(ion)에 대한 장벽(Barrier) 역할이 증대될 수 있는 금속층간 절연막을 형성시키기 위해 금속층간 산화막 형성후 수소이온(Hydrogen ion)을 주입시켜 SOG막 큐어링(curing)시 수분의 방출을 촉진시키고 금속층간 산화막내에 실리콘 댕글링 본드(Si dangling bond)를 다량으로 존재하게 하여 H+이온의 침투에 대한 장벽역할을 증대시킬 수 있을 뿐만 아니라 상부금속층 및 보호막의 질을 향상시킬 수 있는 반도체 소자의 금속층간 절연막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film of a semiconductor device. In particular, the role of a barrier against H + ions penetrating into an underlying layer during formation of a plasma nitride layer used as a passivation layer may be increased. In order to form a metal interlayer insulating film, hydrogen ions are implanted after forming the metal interlayer oxide film to promote the release of water during the curing of the SOG film, and a silicon dangling bond in the metal interlayer oxide film. The present invention relates to a method for forming an interlayer insulating film of a semiconductor device capable of increasing the barrier role against H + ion penetration by increasing the amount of ions and improving the quality of the upper metal layer and the protective film.
일반적으로 금속배선이 다층화 됨에 따라 금속배선간의 절연 및 표면 평탄화를 위해 절연막 형성공정을 실시하게 된다. 이 절연막은 제1 IMO(Inter Metal Oxide), SOG(Spin-On-Glass) 및 제2 IMO의 3중층으로 이루어지는데, 통상적으로 제1 IMO로는 TEOS 산화물을, 그리고 제2 IMO로는 SiH4산화물을 주로 사용한다. 그러면 종래 반도체 소자의 금속층간 절연막 형성방법을 제1a 및 제1b도를 통해 설명하면 다음과 같다.In general, as the metallization is multilayered, an insulating film forming process is performed to insulate and planarize the surfaces of the metallization. The insulating film is composed of a triple layer of first intermetal oxide (IMO), spin-on-glass (SOG) and second IMO. Typically, TEOS oxide is used as the first IMO, and SiH 4 oxide is used as the second IMO. Mainly used. A method of forming a metal interlayer insulating film of a conventional semiconductor device will now be described with reference to FIGS. 1A and 1B.
제1a 및 제1b도는 종래 반도체 소자의 금속층간 절연막 형성방법을 설명하기 위한 소자의 단면도로서, 제1a도는 절연막(3)이 형성된 실리콘 기판(1)의 불순물 영역(2)과 접속되도록 제1금속층(4)을 형성하고, 그 상부에 TEOS 산화물을 증착하여 제1 IMO(5)을 형성한 다음 SOG막(6)을 형성하고, SiH4산화물을 이용하여 제2 IMO(7)을 형성시켜 상기 제1금속층(4) 상부에 금속층간 절연막이 형성된 상태에서, 상기 제1금속층(4)과 접속되도록 마스크를 이용하여 사진 및 식각공정에 의해 상기 금속층간 절연막을 식각하여 비아 홀(Via hole)을 형성시킨 상태의 단면도이다.1A and 1B are cross-sectional views of a device for explaining a method of forming a metal interlayer insulating film of a conventional semiconductor device. FIG. 1A is a first metal layer connected to an impurity region 2 of a silicon substrate 1 on which an insulating film 3 is formed. (4) to form a first IMO (5) by depositing TEOS oxide on top of it, then to form an SOG film (6), and to form a second IMO (7) by using SiH 4 oxide In the state in which the intermetallic insulating film is formed on the first metal layer 4, the via interlayer insulating film is etched by a photolithography and an etching process using a mask so as to be connected to the first metal layer 4 to form a via hole. It is sectional drawing of the state formed.
제1b도는 제1a도의 상태에서 제2금속층(8)을 형성하고, 플라즈마 산화막(plasma oxide) 증착하여 제1보호막(Passivation)(9)을 형성시킨 후 N2열처리(Annealing) 공정을 진행하고, 플라즈마 질화막(plasmanitride)을 증착하여 제2보호막(10)을 형성시킨 상태의 단면도인데, 이때 상기 제2보호막(10)형성시 H+이온(ion)이 하부층으로 침투되기 때문에 상기 제1보호막(9)은 일반적으로 실리콘-리치 산화막(Si-rich oxide)을 사용한다. 그러나 SOG를 사용하는 공정에서는 SOG막의 큐어링이 완벽할 수 없기 때문에 이후 여러번의 열처리 단계에서 상기 SOG막은 수분(Moisture)을 외부 확산(Out diffusion)시켜 상기 제2금속층(8) 및 제1보호막(9)의 질(Quality)을 저하시킨다.In FIG. 1B, a second metal layer 8 is formed in the state of FIG. 1A, a plasma oxide film is deposited to form a first passivation layer 9, and then an N 2 annealing process is performed. A cross-sectional view of a state in which a second protective film 10 is formed by depositing a plasma nitride film is formed. In this case, H + ions penetrate into the lower layer when the second protective film 10 is formed. ) Generally uses a silicon rich oxide (Si-rich oxide). However, in the process using SOG, the curing of the SOG film may not be perfect. Therefore, in several subsequent heat treatment steps, the SOG film out-diffuses the moisture, so that the second metal layer 8 and the first passivation film ( 9) Reduces the quality.
즉, 하기의 (식1) 및 (식2)와 같은 반응이 연쇄적으로 이루어지면서 H20 성분이 외부 확산되는데, 이 성분은 하기의 (식3)에서와 같이 상기 제1보호막(9)의 산화막과 반응한다.That is, the H 2 O component is externally diffused while reactions such as the following Equations 1 and 2 are chained, and the first protective layer 9 is formed as shown in Equation 3 below. Reacts with an oxide film of
또한 상기 (식3)과 같은 반응에 의해 상기 제2 IMO(7)내의 실리콘 댕글링 본드(Si Dangling Bond)가 소실되어 침투되는 H+이온에 대하여 장벽 역할을 효과적으로 할 수 없기 때문에 소자의 신뢰도를 저하시키는 원인이 된다.In addition, since the silicon dangling bond (Si Dangling Bond) in the second IMO (7) is lost by the reaction as described above (3), it can not effectively act as a barrier against the H + ions that penetrate the device reliability It causes the deterioration.
따라서 본 발명은 금속층간 산화막 형성후 수소이온(Hydrogen ion)을 주입시켜 SOG막 큐어링(curing)시 수분의 방출을 촉진시키고 금속층간 산화막내에 실리콘 댕글링 본드(Si dangling bond)를 다량으로 존재하게 하여 상기한 단점을 해소할 수 있는 반도체 소자의 금속층간 절연막 형성방법을 제공하는데 그 목적이 있다.Therefore, the present invention promotes the release of water during the curing of the SOG film by injecting hydrogen ions after the formation of the interlayer metal oxide layer and the presence of a large amount of Si dangling bond in the intermetal oxide layer. Accordingly, an object of the present invention is to provide a method for forming an interlayer insulating film of a semiconductor device, which can solve the above disadvantages.
상기한 목적을 달성하기 위한 본 발명은 하부 금속층상에서 제1 IMO(5), SOG막(6) 및 제2 IMO(7)을 순차적으로 형성한 후, 상기 제2 IMO(7)에 수소이온을 주입시키는 것을 특징으로 한다.In order to achieve the above object, the present invention sequentially forms a first IMO 5, an SOG film 6, and a second IMO 7 on a lower metal layer, and then hydrogen ions are applied to the second IMO 7. It is characterized by injecting.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2a 및 제2b도는 본 발명에 따른 반도체 소자의 금속층간 절연막 형성방법을 설명하기 위한 소자의 단면도로서, 제2a도는 절연막(3)이 형성된 실리콘 기판(1)의 불순물영역(2)과 접속되도록 제1금속층(4)을 형성하고 그 상부에 TEOS 산화물을 증착하여 제1 IMO(5)을 형성한 다음 SOG막(6)을 형성하고 SiH4산화물을 이용하여 제2 IMO(7)을 형성시켜 금속층간 절연막(5,6 및 7)이 형성된 상태에서 수소 이온을 주입시키는 상태의 단면도이다.2A and 2B are cross-sectional views of a device for explaining a method for forming an interlayer insulating film of a semiconductor device according to the present invention, and FIG. 2A is a view for connecting the impurity region 2 of the silicon substrate 1 on which the insulating film 3 is formed. The first metal layer 4 is formed, and TEOS oxide is deposited thereon to form the first IMO 5, then the SOG film 6 is formed, and the second IMO 7 is formed using the SiH 4 oxide. It is sectional drawing of the state which inject | pours hydrogen ion in the state in which the intermetallic insulating film 5, 6, and 7 were formed.
제2b도는 마스크를 이용하여 사진 및 식각공정에 의해 상기 제1금속층(4)과 접속되도록 상기 금속층간 절연막(5,6 및 7)을 식각하여 비아홀을 형성시킨 후 그 상부에 제2금속층(8)을 형성하고, 플라즈마 산화막을 증착하여 제1보호막(9)을 형성시킨 후 N2열처리공정을 진행하고 플라즈마 질화막을 증착하여 제2보호막(10)을 형성시킨 상태의 단면도이다.FIG. 2B illustrates etching of the interlayer insulating films 5, 6, and 7 so as to be connected to the first metal layer 4 by a photolithography and etching process using a mask to form a via hole, and then a second metal layer 8 thereon. ), The plasma oxide film is deposited to form the first protective film 9, the N 2 heat treatment process is performed, and the plasma nitride film is deposited to form the second protective film 10.
상기한 공정단계에서 SOG막(6)을 도포한 후 1차 큐어링(curing)하여 SOG막(6)내에 포함되어 있는 수분을 어느 정도 방출시키고, 상기 비아 홀 형성후에 다시 2차 큐어링공정을 실시하여 SOG막(6)내의 수분을 방출시킨다.After applying the SOG film 6 in the above process step, the first curing (curing) to release the moisture contained in the SOG film 6 to some extent, and after the via hole is formed, the second curing process is performed again. This releases water in the SOG film 6.
상기 2차 큐어링공정시 SOG막(6)으로부터의 수분이 상부층을 이루는 제2 IMO(7)를 통하여 외부로 확산이 이루어져야 하는데, 상기 제2 IMO(7) 형성시 수소이온의 주입에 의하여 Si-H 본드 및 수소이온이 많아 SOG막(6)으로부터의 수분 방출을 용이하게 하여 1차 및 2차 큐어링공정으로 SOG막(6)내에 포함되어 있는 수분을 대부분 외부 확산시킬 수 있다.During the second curing process, the moisture from the SOG film 6 should be diffused to the outside through the second IMO 7 forming the upper layer, and when the second IMO 7 is formed, Si A large amount of -H bonds and hydrogen ions facilitate the release of water from the SOG film 6, and the water contained in the SOG film 6 can be externally diffused mostly in the primary and secondary curing processes.
따라서 후속공정으로 형성되는 제2금속층(8) 및 제1보호막(9) 형성시 SOG막(6)으로부터의 수분침투에 의한 막질의 저하를 방지할 수 있다. 또한 후속공정으로 제2보호막(10)을 형성할 때 침투되는 H+이온은 상기 막질의 저하가 없는 제1보호막(9)과 상기 실리콘 댕글링 본드가 많은 제2 IMO(7)이 우수한 장벽층 역할을 하기 때문에 소자 내부로 H+이온의 침투를 방지한다.Therefore, when the second metal layer 8 and the first passivation layer 9 are formed in a subsequent step, the degradation of the film quality due to water penetration from the SOG film 6 can be prevented. In addition, the H + ions penetrated when the second protective film 10 is formed in a subsequent process are superior to the first protective film 9 without deterioration of the film quality and the second IMO 7 having a large number of silicon dangling bonds. It acts to prevent the penetration of H + ions into the device.
이해를 돕기 위하여, 전술한 (식1)과 (식2)에 덧붙여 하기 (식4)와 (식5)의 반응이 일어난다.For the sake of understanding, in addition to the above formulas (1) and (2), the reactions of the following formulas (4) and (5) occur.
상기 (식4)와 (식5)의 반응이 일어나게 함으로써 2차 SOG 큐어링시 수분은 거의 완벽하게 외부 확산시킬 수 있어 제1보호막의 막질을 보호할 수 있다.By allowing the reaction of the above formulas (4) and (5) to occur, moisture can be almost completely diffused during the second SOG curing, thereby protecting the film quality of the first protective film.
상술한 바와 같이 수분 및 H+이온에 대한 장벽효과를 증대시켜 이들로 인하여 유발되는 소자의 결함을 방지함으로써 소자의 신뢰도를 증가시킬 수 있는 탁월한 효과가 있다.As described above, there is an excellent effect of increasing the reliability of the device by increasing the barrier effect against moisture and H + ions to prevent the defect of the device caused by them.
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| KR1019940011483A KR0119966B1 (en) | 1994-05-26 | 1994-05-26 | Forming method of interlayer insulating films in the semiconductor device |
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| KR1019940011483A KR0119966B1 (en) | 1994-05-26 | 1994-05-26 | Forming method of interlayer insulating films in the semiconductor device |
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| KR0119966B1 true KR0119966B1 (en) | 1997-10-17 |
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