KR100268795B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR100268795B1
KR100268795B1 KR1019970081287A KR19970081287A KR100268795B1 KR 100268795 B1 KR100268795 B1 KR 100268795B1 KR 1019970081287 A KR1019970081287 A KR 1019970081287A KR 19970081287 A KR19970081287 A KR 19970081287A KR 100268795 B1 KR100268795 B1 KR 100268795B1
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film
manufacturing
semiconductor device
forming
plasma
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KR1019970081287A
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Korean (ko)
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KR19990061033A (en
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이성준
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to recover a topology by using an SOG(Spin On Glass) layer doped with p-type dopant as a protective layer. CONSTITUTION: A MOS field effect transistor, a bit line, and a capacitor are formed on a semiconductor substrate(10). A planarization layer(12) is formed thereon. Each devices are connected by using a metal line(14). A plasma CVD(Chemical Vapor Deposition) layer(16) as a lower protective layer is formed on the whole surface. An intermediate protective layer(18) is formed on the plasma CVD layer(16). A reflow process for the intermediate protective layer(18) is performed. An upper protective layer(20) is formed on the intermediate protective layer(18).

Description

반도체소자의 제조방법Manufacturing method of semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 p 형 불순물이 도핑된 SOG 막을 보호막으로 사용하여 단차를 극복하고, 외부에서 주입된 불순물을 게터링(gettering)함으로써 소자를 안정하게 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technology for stabilizing a device by overcoming a step using a p-type impurity doped SOG film as a protective film and by gettering impurities injected from the outside. will be.

종래기술에 따른 반도체소자의 제조방법에 대하여 살펴보기로 한다.A manufacturing method of a semiconductor device according to the prior art will be described.

도 1 은 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도이다.1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the prior art.

먼저, 반도체소자를 형성하는 공지의 기술을 이용하여 반도체기판 상부에 소자들을 형성하고, 상기 구조 상부에 평탄화막(11)을 형성하여 평탄화시킨다.First, devices are formed on a semiconductor substrate by using a known technique of forming a semiconductor device, and a planarization film 11 is formed on the structure to planarize the semiconductor device.

그 다음, 금속배선(13)을 형성하여 상기 소자들을 연결시켜 준다.Next, a metal wiring 13 is formed to connect the devices.

다음, 외부로부터의 물리적, 화학적 자극으로부터 칩을 보호하기 위하여 보호막(15)을 형성한다.Next, a protective film 15 is formed to protect the chip from physical and chemical stimuli from the outside.

상기 보호막(15)은 플라즈마 화학기상증착(plasma enhanced chemical vapor deposition, 이하 PE-CVD 라 함) 산화막 또는 플라즈마 CVD 질화막을 사용하여 이중막으로 형성하거나, 플라즈마 CVD 질화막, 플라즈마 CVD 산질화막을 이용하여 단층막으로 형성한다.The passivation layer 15 is formed as a double layer using plasma enhanced chemical vapor deposition (PE-CVD) oxide film or plasma CVD nitride film, or a single layer using plasma CVD nitride film or plasma CVD oxynitride film. Form into a film.

그러나, 상기한 바와 같이 종래기술에 따른 반도체소자의 제조방법은, 소자가 미세화되고, 고집적화되어 감에 따라 단차가 심해지고, 금속배선 사이의 간격이 좁아지면서 보호막 상부의 양가장자리 부분이 좌·우로 돌출되는 커스핑(cusping) 현상이 발생되어 보호막이 서로 붙어서 크랙(crack) 또는 보이드(void)가 발생하여 외부로부터 불순물 침투에 의해 소자의 신뢰성 및 특성을 저하시키는 문제점이 있다.However, as described above, in the method of manufacturing a semiconductor device according to the prior art, as the device becomes finer and more highly integrated, the step becomes severe and the gap between the metal wires becomes narrower, so that both edge portions of the upper portion of the protective film are left and right. Protruding cuping occurs and a protective film adheres to each other, causing cracks or voids, thereby degrading reliability and characteristics of the device by infiltration of impurities from the outside.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 단차피복성이 우수힌 p 형 불순물이 도핑된 SOG를 이용하여 보호막을 형성함으로써 단차를 감소시키고, 불순물을 게터링(gettering)함으로써 보이드나 크랙이 발생하는 것을 방지하고, 소자를 안정화시켜 반도체소자의 특성을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION In order to solve the problems of the prior art described above, the step is reduced by forming a protective film using SOG doped with a p-type impurity having excellent step coverage, and gettering the impurities by getting getters or cracks. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which prevents the occurrence of this phenomenon and stabilizes the device to improve characteristics of the semiconductor device.

도 1 은 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도.1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.

도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

＜도면의 주요부분에 대한 부호 설명＞<Description of Signs of Main Parts in Drawings>

11, 12 : 평탄화막 13, 14 : 금속배선11, 12: planarization film 13, 14: metal wiring

15 : 보호막 16 : 하부보호막15: protective film 16: lower protective film

18 : 중간보호막 20 : 상부보호막18: intermediate protective film 20: upper protective film

이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,

소정 구조의 반도체기판 상에 형성되어 있는 평탄화막 상에 금속배선을 형성하는 공정과,Forming a metal wiring on the planarization film formed on the semiconductor substrate having a predetermined structure;

상기 구조 상부에 하부보호막을 형성하는 공정과,Forming a lower protective film on the structure;

상기 하부보호막 상부에 SOG를 사용하여 중간보호막을 형성한 후, 리플로우시켜 평탄화시키는 공정과,Forming an intermediate passivation layer using SOG on the lower passivation layer, and then reflowing and planarization;

상기 중간보호막 상부에 상부보호막을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming an upper protective film on the intermediate protective film.

이하, 본 발명에 따른 반도체소자의 제조방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

먼저, 반도체소자를 형성하는 공지의 기술을 이용하여 반도체기판(도시안됨) 상부에 MOS 전계효과 트랜지스터, 비트라인 및 캐패시터 들과 같은 소자들을 형성한 다음, 상기 구조를 평탄화하는 평탄화막(12)을 형성하고, 금속배선(14)을 이용하여 상기 소자들과 연결한다.First, devices such as MOS field effect transistors, bit lines, and capacitors are formed on a semiconductor substrate (not shown) using a known technique for forming a semiconductor device, and then the planarization film 12 for planarizing the structure is formed. It is formed and connected to the devices using a metal wire (14).

다음, 외부로부터 불순물이 침투하는 것을 방지하기 위하여 상기 구조 상부에 하부보호막(16)으로 플라즈마 CVD 산화막을 400 ∼ 600 Å 두께 형성한다. (도 2a참조)Next, in order to prevent impurities from penetrating from the outside, a plasma CVD oxide film is formed with a lower protective film 16 on the upper portion of the structure, 400-600 Å thick. (See Figure 2A)

그 다음, 상기 하부보호막(16) 상부에 중간보호막(18)을 형성한다. 상기 중간보호막(18)은 p 형 불순물이 도핑된 SOG 막으로 1500 ∼ 2000 Å 두께로 증착한다.Next, an intermediate passivation layer 18 is formed on the lower passivation layer 16. The intermediate protective film 18 is a SOG film doped with p-type impurities and deposited at a thickness of 1500 to 2000 m 3.

그리고, 상기 중간보호막(18)을 350 ∼ 400 ℃의 질소분위기에서 20 ∼ 30 분간 리플로우시키거나, 이-빔(E-beam) 열처리장비를 이용하여 230 ∼ 270 ℃에서 4 ∼ 6 keV의 이온주입에너지로 4000μc/㎠ 의 전하밀도를 갖도록 리플로우시킨다. (도 2b참조)The intermediate protective film 18 is then reflowed in a nitrogen atmosphere at 350 to 400 ° C. for 20 to 30 minutes, or 4 to 6 keV ions at 230 to 270 ° C. using an E-beam heat treatment equipment. The injected energy is reflowed to have a charge density of 4000 µc / cm 2. (See Figure 2b)

한편, 상기 중간보호막(18)을 유기계 SOG 막을 사용하여 형성할 수도 있다.In addition, the intermediate protective film 18 may be formed using an organic SOG film.

상기 중간보호막(18)인 유기계 SOG 막은 상기 유기계 SOG 막을 2500 ∼ 3500 Å 두께 형성한 다음, 도즈량 108∼ 109cm-3의 P31을 불순물을 7 ∼ 10 keV 의 이온주입에너지로 블랭켓 임플란트(blanket implant)공정을 실시하여 사용한다. 이때, 상기 유기계 SOG 막은 치밀화되면서 O-Si-CH3결합이 끊어지고, O-Si-P 결합을 형성한다. 이는 상기 O-Si-CH3결합 에너지가 O-Si-P 결합 에너지보다 낮아서 상기 O-Si-CH3결합이 끊어지기 쉽기 때문에 P 가 흡착되기 쉬워진다. 상기와 같은 방법을 사용하면 특별히 열처리공정을 실시할 필요가 없기 때문에 공정이 용이해진다. (도 2c참조)The organic SOG film, which is the intermediate protective film 18, is formed by forming the organic SOG film in a thickness of 2500 to 3500 mm 3 , and then blanketing P 31 with a dose of 10 8 to 10 9 cm -3 with an ion implantation energy of 7 to 10 keV. It is used after carrying out the blanket implant process. At this time, the organic SOG film is densified and O-Si-CH 3 bonds are broken to form O-Si-P bonds. This is because the O-Si-CH 3 bond energy is lower than the O-Si-P bond energy, so that the O-Si-CH 3 bond is easily broken, so that P is easily adsorbed. If the above-described method is used, the process is easy because there is no need to perform the heat treatment step in particular. (See FIG. 2C)

다음, 상기 중간보호막(18) 상부에 상부보호막(20)을 형성하되, 플라즈마 CVD 질화막 또는 굴절율이 높은 플라즈마 CVD 산질화막을 6000 ∼ 7000 Å 두께 형성하여 보호막 형성공정을 완료한다. 상기 하부보호막(20)은 사일렌(silane)가스의 양을 증가시켜 형성함으로써 Si 가 다량 함유되어 Si의 댕글링 본드가 발생하게 되고, 상기 Si 의 댕글링 본드는 외부로 부터 주입되는 수소 이온을 포획하는 역할을 한다. (도 2d참조)Next, an upper passivation layer 20 is formed on the intermediate passivation layer 18, and a plasma CVD oxynitride layer or a plasma CVD oxynitride layer having a high refractive index is formed to have a thickness of 6000 to 7000 Å to complete the passivation layer forming process. The lower passivation layer 20 is formed by increasing the amount of silane gas so that a large amount of Si is generated, and a dangling bond of Si is generated, and the dangling bond of Si receives hydrogen ions injected from the outside. To capture. (See FIG. 2D)

또한, 상기 p 형 불순물이 도핑된 SOG 막은 도전층과 금속배선간에 절연막으로 사용되어 전체적인 단차를 보정해주는 역할을 하기도 한다.In addition, the SOG film doped with the p-type impurity is used as an insulating film between the conductive layer and the metal wiring to serve to correct the overall step difference.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 마지막 금속배선을 형성하고 그 상부에 3층 보호막을 형성하되, 단차피복성이 우수한 p 형 불순물이 도핑된 SOG 막을 사용함으로써 보호막 형성후 보이드나 크랙이 발생하는 것을 방지하고, 상기 불순물이 외부로부터 들어오는 Na+, K+와 같은 모빌 이온을 포획하여 게터링 효과까지 얻어 소자를 안정화시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, after forming the last metal wiring and forming a three-layered protective film on the upper portion, the protective film is formed by using a SOG film doped with a p-type impurity having excellent step coverage. It is advantageous in that voids or cracks are prevented from occurring and the impurities are trapped in the mobile ions such as Na + and K + to obtain a gettering effect to stabilize the device.

Claims (7)

소정 하부구조물이구비된 반도체기판 상에 평탄화막을 형성하고, 상기 평탄화막 상에 금속배선을 형성하는 공정과,Forming a planarization film on the semiconductor substrate provided with a predetermined substructure, and forming metal wiring on the planarization film; 전체표면 상부에 보호막을 형성하되, 상기 보호막은 플라즈마 산화막, p형 불순물이 도핑된 SOG막 및 플라즈마 질화막이 순차적으로 형성된 적층구조로 형성하는 공정을 포함하는 것을 반도체소자의 제조방법.A protective film is formed over the entire surface, wherein the protective film includes a step of forming a plasma oxide film, a SOG film doped with p-type impurities, and a plasma nitride film in a stacked structure sequentially formed. 제 1 항에 있어서,The method of claim 1, 상기 플라즈마 산화막은 400 ∼ 600 Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 제조방법.The plasma oxide film is a manufacturing method of a semiconductor device, characterized in that formed to a thickness of 400 ~ 600 kHz. 제 1 항에 있어서,The method of claim 1, 상기 p 형 불순물이 도핑된 SOG 막 대신 유기계 SOG 막을 사용하는 것을 특징으로 하는 반도체소자의 제조방법.An organic SOG film is used instead of the SOG film doped with the p-type impurity. 제 1 항 또는 제 3 항에 있어서,The method according to claim 1 or 3, 상기 p 형 불순물이 도핑된 SOG 막은 1500 ∼ 2000 Å 두께로 증착한 다음, 350 ∼ 400 ℃의 질소분위기에서 20 ∼ 30 분간 리플로우시키거나, 이-빔(E-beam) 열처리장비를 이용하여 230 ∼ 270 ℃에서 4 ∼ 6 keV의 이온주입에너지로 4000μc/㎠ 의 전하밀도를 갖도록 리플로우시켜 형성되는 것을 특징으로 하는 반도체소자의 제조방법.The SOG film doped with the p-type impurity was deposited to a thickness of 1500 to 2000 Å, and then reflowed in a nitrogen atmosphere at 350 to 400 ° C. for 20 to 30 minutes, or 230 using an E-beam heat treatment equipment. A method of manufacturing a semiconductor device, characterized in that formed by reflowing to have a charge density of 4000μc / ㎠ at 4 ~ 6 keV ion implantation energy at ~ 270 ℃. 제 3 항에 있어서,The method of claim 3, wherein 상기 유기계 SOG 막은 2500 ∼ 3500 Å 두께 형성한 다음, 도즈량 108∼ 109cm-3의 P31을 불순물을 7 ∼ 10 keV 의 이온주입에너지로 블랭켓 임플란트하여 형성되는 것을 특징으로 하는 반도체소자의 제조방법.The organic SOG film is formed by forming a thickness of 2500 to 3500 다음, and then implanting P 31 having a dose of 10 8 to 10 9 cm -3 with a blanket implant with an ion implantation energy of 7 to 10 keV. Manufacturing method. 제 1 항에 있어서,The method of claim 1, 상기 플라즈마 질화막은 6000 ∼ 7000 Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 제조방법.The plasma nitride film is a semiconductor device manufacturing method, characterized in that formed to a thickness of 6000 ~ 7000 Å. 제 1 항에 있어서,The method of claim 1, 상기 플라즈마 질화막 대신 사일렌 가스의 양을 증가시켜 형성된 Si를 다량 함유한 플라즈마 산질화막을 사용하는 것을 특징으로 하는 반도체소자의 제조방법.And a plasma oxynitride film containing a large amount of Si formed by increasing the amount of xylene gas instead of the plasma nitride film.
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