KR950007019A - Method of forming interlayer insulating film of semiconductor device - Google Patents

Method of forming interlayer insulating film of semiconductor device Download PDF

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Publication number
KR950007019A
KR950007019A KR1019930016644A KR930016644A KR950007019A KR 950007019 A KR950007019 A KR 950007019A KR 1019930016644 A KR1019930016644 A KR 1019930016644A KR 930016644 A KR930016644 A KR 930016644A KR 950007019 A KR950007019 A KR 950007019A
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South Korea
Prior art keywords
film
interlayer insulating
forming
insulating film
layer metal
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KR1019930016644A
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Korean (ko)
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KR960012627B1 (en
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김시범
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김주용
현대전자산업 주식회사
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Priority to KR1019930016644A priority Critical patent/KR960012627B1/en
Publication of KR950007019A publication Critical patent/KR950007019A/en
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Publication of KR960012627B1 publication Critical patent/KR960012627B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 층간 절연막 형성방법에 관하여 기술한 것으로, 2층 금속배선구조를 갖는 CMOS소자에서 제2층 금속배선 형성 후 SiNχ보호막(Passivation) 증착 및 열 공정시 층간 절연막을 통해 소자 내부로 불순물이 침투함에 의하여 발생되는 기생 MOSFET의 드레인 영역과 소오스 영역간의 절연성 저하 또는 결함(Fail)유발의 소위 "필드 극성반전(Field Inversion)" 현상을 방지하기 위하여, 제1층 금속배선 형성 후 SOG(Spin-on-Glass)를 도포하기 전에 질화막(SiNχ)을 얇게 증착하는 방법으로, 층간 절연막을 형성하여 절연막 특성을 향상시켜 기생MOSFET의 필드 극성반전현상을 방지할 수 있도록 한 반도체 소자의 층간 절연막 형성방법이 기술된다.The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, and after forming the second layer metal wiring in a CMOS device having a two-layer metal wiring structure, through the interlayer insulating film during the deposition of SiNχ passivation and the thermal process. In order to prevent the so-called "field inversion" of the insulation or degradation of the parasitic MOSFET caused by the impurity penetration, the so-called "field inversion" phenomenon, SOG ( A method of thinly depositing a nitride film (SiNχ) before applying spin-on-glass to form an interlayer insulating film of a semiconductor device in which an interlayer insulating film is formed to improve insulating properties to prevent field polarity inversion of parasitic MOSFETs. The method is described.

Description

반도체 소자의 층간 절연막 형성방법Method of forming interlayer insulating film of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 층간 절연막이 적용된 2층 금속배선구조의 CMOS소자 단면도,2 is a cross-sectional view of a CMOS device of a two-layer metal wiring structure to which an interlayer insulating film according to the present invention is applied;

제3A도 내지 제3D도는 상기 제2도의 층간 절연막을 형성하는 단계를 설명하기 위한 단면도.3A to 3D are sectional views for explaining the step of forming the interlayer insulating film of FIG.

Claims (2)

2층 금속배선구조를 갖는 CMOS소자의 제조공정 중 층간 절연막을 형성하는 방법에 있어서, CMOS소자의 제조시 제2층 금속배선 형성 후 보호막 증착 및 열공정에 의해 발생되는 기생 MOSFET의 드레인 영역과 소오스 영역간의 절연 특성 저하를 방지하기 위하여, 다수의 제1층 금속배선(8)이 형성된 전제구조 상부에 PECVD방법으로 제1산화막(19a)을 증착한 후, 상기 제1산화막(19a)상부에 PECVD방법으로 질화막(19d)을 형성하는 단계와, 상기 질화막(19d) 상부에 SOG막(19b)을 도포하여 경화하는 단계와, 상기 SOG막(19b) 상부에 PECVD 방법으로 제2산화막(19C)을 증착하는 단계로 제1산화막/질화막/SOG막/제2산화막으로 된 층간 절연막(19)을 형성하는 것을 특징으로 하는 반도체 소자의 층간 절연막 형성방법.In the method for forming an interlayer insulating film during the manufacturing process of a CMOS device having a two-layer metal wiring structure, the drain region and source of the parasitic MOSFET generated by the protective film deposition and thermal process after the second layer metal wiring is formed during the manufacturing of the CMOS device In order to prevent the deterioration of the insulating properties between the regions, the first oxide film 19a is deposited on the entire structure on which the plurality of first layer metal wirings 8 are formed by PECVD, and then PECVD on the first oxide film 19a. Forming a nitride film (19d) by a method, applying and curing an SOG film (19b) on top of the nitride film (19d), and a second oxide film (19C) on the SOG film (19b) by PECVD. A method of forming an interlayer insulating film of a semiconductor device, characterized by forming an interlayer insulating film (19) consisting of a first oxide film / nitride film / SOG film / second oxide film by vapor deposition. 2층 금속배선구조를 갖는 CMOS소자의 제조공정 중 층간 절연막을 형성하는 방법에 있어서, CMOS소자의 제조시 제2층 금속배선 형성 후 보호막 증착 및 열공정에 의해 발생되는 기생 MOSFET의 드레인 영역과 소오스 영역간의 절연특성 저하를 방지하기 위하여, 다수의 제1층 금속배선(8)이 형성된 전체구조 상부에 PECVD방법으로 제1산화막(19d)을 형성하는 단계와, 상기 질화막(19d) 상부에 SOG막(19b)을 도포하여 경화하는 단계와, 상기 SOG막(19b) 상부에 PECVD 방법으로 제2산화막(19C)을 증착하는 단계로 질화막/SOG막/제2산화막으로 된 층간 절연막을 형성하는 것을 특징으로 하는 반도체 소자의 층간 절연막 형성방법.In the method for forming an interlayer insulating film during the manufacturing process of a CMOS device having a two-layer metal wiring structure, the drain region and source of the parasitic MOSFET generated by the protective film deposition and thermal process after the second layer metal wiring is formed during the manufacturing of the CMOS device Forming the first oxide film 19d on the entire structure on which the plurality of first layer metal wirings 8 are formed by the PECVD method to prevent the deterioration of the insulating properties between the regions, and the SOG film on the nitride film 19d. Forming an interlayer insulating film made of a nitride film / SOG film / second oxide film by applying (19b) and curing and depositing a second oxide film (19C) on the SOG film (19b) by PECVD. An interlayer insulating film forming method of a semiconductor device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930016644A 1993-08-26 1993-08-26 Forming method of inter-insulating film for semiconductor device KR960012627B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930016644A KR960012627B1 (en) 1993-08-26 1993-08-26 Forming method of inter-insulating film for semiconductor device

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KR1019930016644A KR960012627B1 (en) 1993-08-26 1993-08-26 Forming method of inter-insulating film for semiconductor device

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KR950007019A true KR950007019A (en) 1995-03-21
KR960012627B1 KR960012627B1 (en) 1996-09-23

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100268795B1 (en) * 1997-12-31 2000-11-01 김영환 Manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100268795B1 (en) * 1997-12-31 2000-11-01 김영환 Manufacturing method of semiconductor device

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KR960012627B1 (en) 1996-09-23

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