JPH03120745A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03120745A JPH03120745A JP25820489A JP25820489A JPH03120745A JP H03120745 A JPH03120745 A JP H03120745A JP 25820489 A JP25820489 A JP 25820489A JP 25820489 A JP25820489 A JP 25820489A JP H03120745 A JPH03120745 A JP H03120745A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating film
- interconnection
- film
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000010410 layer Substances 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- 239000011229 interlayer Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 12
- 239000002966 varnish Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 1
- 229920001187 thermosetting polymer Polymers 0.000 claims 1
- 229910000838 Al alloy Inorganic materials 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000002159 abnormal effect Effects 0.000 abstract description 2
- 230000004888 barrier function Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 239000002904 solvent Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体装置の製造方法に関し、特に、高集積化
されたＡＡ合金配線等の多層配線構造を持つ工Ｃの高信
頼性化に有効である。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and is particularly effective in improving the reliability of a process having a multilayer wiring structure such as highly integrated AA alloy wiring. It is.
［従来の技術］
従来より、配線の層間絶縁膜形成に平担化の目的でワニ
ス状態でスピンナー塗布し、熱硬化させることにより無
機（Ｓｉｎ２．５ｐｉｎ−ｏｎ −ＧｌａβＢ）、有機
（ポリイミド）の絶縁膜が用いられている。溶剤を完全
にキュアするためには６００℃〜８００℃の高温熱処理
を必要とする。[Prior art] Conventionally, inorganic (Sin2.5 pin-on-GlaβB) and organic (polyimide) insulation has been formed by applying spinner coating in a varnish state for the purpose of flattening the interlayer insulation film of wiring and curing it with heat. membrane is used. In order to completely cure the solvent, high temperature heat treatment at 600°C to 800°C is required.
［発明が解決しようとする課題］
しかしＡＬ金合金配線に用いた場合５００℃以上の熱処
理は、ＡＬの拡散層のつき抜けによる接合リークの増大
などの不具合を生じるために、完全にキュアができない
。このため溶媒中の不純物や溶媒自身が後工程の加熱時
にバルク中に拡散して、トランジスタにしきい値電圧（
ｖｔｈ ）異常の不具合を発生させたり、スピン塗布膜
と上層の膜の界面にボイドが生じるという不具合が発生
する。上記不具合は工０が高集積化し、凹凸・がより激
しくなったり、そして下のトランジスタとスピン塗布膜
の距離が短かくなった時に顕著になる。[Problem to be solved by the invention] However, when used for AL gold alloy wiring, heat treatment at 500°C or higher causes problems such as increased junction leakage due to penetration of the AL diffusion layer, so it cannot be completely cured. . For this reason, impurities in the solvent and the solvent itself diffuse into the bulk during heating in the subsequent process, causing the threshold voltage (
vth) Abnormal defects may occur, or defects may occur such as voids occurring at the interface between the spin-coated film and the upper layer film. The above-mentioned problems become noticeable when the process becomes highly integrated, the unevenness becomes more severe, and the distance between the underlying transistor and the spin-coated film becomes shorter.
本発明は、かかる従来の不具合を解決し、配線の層間に
平担化のためのスピン塗布絶縁膜が形成され、かつ、キ
ュア不足によって発生するＩＯの信頼性上の問題を回避
することを目的とする。The purpose of the present invention is to solve such conventional problems, and to avoid problems in IO reliability caused by the formation of a flattening spin-coated insulating film between wiring layers and insufficient curing. shall be.
［課題を解決するための手段］
本発明は、スピン塗布絶縁膜形成後、後工程の熱処理を
スピン塗布膜硬化（キュア）温度より低い温度で処理す
ることを特徴としている。スピン塗布絶縁膜は、−度あ
る温度で硬化すると、その温度より低い温度の熱処理で
は溶媒がスピン塗布膜から外には出に（い。このため溶
媒や不純物がスピン塗布膜内に閉じ込められたままで、
バルク中への拡散やスピン塗布膜と上層のＡ１合金また
はパッシベーション膜との界面に到達しない。このため
、トランジスタの電気特性異常や界面のバルブの発生を
回避できる。キーアが完全でないスピン塗布膜は、一般
に吸湿性を持つため、実際には、スピン塗布ｊ莫形成後
の後玉・程熱処理は、硬化（ギーア）温度より約５０℃
程度低く製造プロセスを設計した方が好ましい。[Means for Solving the Problems] The present invention is characterized in that, after forming a spin-coated insulating film, the post-process heat treatment is performed at a temperature lower than the curing temperature of the spin-coated film. When a spin-coated insulating film is cured at a certain temperature, heat treatment at a temperature lower than that temperature does not allow the solvent to escape from the spin-coated film. to,
It does not diffuse into the bulk or reach the interface between the spin-coated film and the upper layer A1 alloy or passivation film. Therefore, it is possible to avoid abnormalities in the electrical characteristics of the transistor and the occurrence of bulbs at the interface. Since spin-coated films with incomplete keir generally have hygroscopic properties, in reality, after spin-coating and heat treatment, the temperature should be approximately 50°C higher than the curing (gear) temperature.
It is preferable to design the manufacturing process to a lesser extent.
［実施例］ 以下、実施例にもとづいて本発明を説明する。[Example] Hereinafter, the present invention will be explained based on Examples.
第１〜６図は、本発明による半導体装置の製造方法をＡ
Ｌ合金２層配線工程に適用した場合の工程断面図を示し
ている。第１図では、Ｓｉ基板１」二には、多数のトラ
ンジスターが形成され、第１層のＡＬ合金配線６と絶縁
膜２により分離されている。Ｍ１層のＡＬ配線６形成後
、層間絶縁膜をＣＶＤ５ｉ０２膜４で形成後、スピン塗
布絶縁膜５により平担化されている。ここでスピン塗布
絶縁膜５に、例えば東京応化００ＤＰ−４８３１（Ｓｐ
ｉｎ−ｏｎ−Ｇｌａｓｅ ；５ＯＧ）を用いた場合、４
５０℃３０分の硬化（キュア）熱処理を行なう。この時
、第１層のＡＬ配線乙の下地には例えばＴｉＮなどのバ
リア層が存在すれば、Ａ ＴＪの拡散層のつき抜けなる
不具合は生じない。第２図では第２層のＡ１合金をスパ
ッタ形成している。加熱スパッタを行なえば、ＡＬ配線
乙のステンプカバレージが向上する。この加熱温度は前
記硬化温度４５０℃より低く、約３５０℃で処理する。1 to 6 illustrate the method of manufacturing a semiconductor device according to the present invention.
A cross-sectional view of the process when applied to the L alloy two-layer wiring process is shown. In FIG. 1, a large number of transistors are formed on a Si substrate 1'2, and are separated by a first layer of AL alloy wiring 6 and an insulating film 2. After forming the M1 layer AL wiring 6, an interlayer insulating film is formed using a CVD5i02 film 4, and then flattened with a spin coating insulating film 5. Here, the spin-coated insulating film 5 is coated with, for example, Tokyo Ohka 00DP-4831 (Sp
When using in-on-Glase; 5OG), 4
A curing heat treatment is performed at 50° C. for 30 minutes. At this time, if a barrier layer such as TiN is present under the first layer of AL wiring B, problems such as penetration of the ATJ diffusion layer will not occur. In FIG. 2, the second layer of A1 alloy is formed by sputtering. If heat sputtering is performed, the stamp coverage of the AL wiring B will be improved. This heating temperature is lower than the curing temperature of 450°C, and is performed at about 350°C.
第５図では、第２層ＡＬ配線６をバターニング後、Ｓｉ
３Ｎ４膜７をＣ’ＶＤ形成し表面を保護している。この
時のＯＶＤ反応温度は３５０℃〜４００℃に取、役、硬
化温度４５０℃より５０℃以上低い。本発明によればＳ
ＯＧのキュアは不完全ながら、後工程においてもＳＯＧ
の溶媒や不純物は５ＯＧ５内に閉じ込められている。In FIG. 5, after patterning the second layer AL wiring 6, Si
A 3N4 film 7 is formed by C'VD to protect the surface. The OVD reaction temperature at this time is 350°C to 400°C, which is 50°C or more lower than the curing temperature of 450°C. According to the present invention, S
Although OG curing is incomplete, SOG is also achieved in the post-process.
The solvent and impurities are confined within 5OG5.
第１図、第２図及び第６図は、本発明による半導体装置
の製造方法の実施例を示す工程断面図。1, 2, and 6 are process cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention.
１・・・・・・・・・Ｓ１基板
２・・・・・・・・・ Ｓｉｎ ２
３・・・・・・・・・Ａ１合金
４・・・・・・・・・５ｉｎ２
５ ・・・・・・・・・ ５ＯＧ
６・・・・・・・・・Ａ１合金
７ ・・・・・・・・・ Ｓ ｉ、Ｉ Ｎ４［発明
の効果コ
以上説明したように、本発明によれば、スピン塗布膜中
の溶媒や不純物のバルク（トランジスタの存在する）領
域への拡散が抑制され、かつ、スピン塗布膜と上層の薄
＋１との界面にボイドが形成されることがない。従って
、高集積化された多層配線構造を持つ高信頼性工Ｃを可
能にする、半導体装置の製造方法を提供する。1...S1 substrate 2...Sin 2 3...A1 alloy 4...5in2 5...・・・・・・・・・ 5OG 6・・・・・・・・・A1 alloy 7 ・・・・・・・・・ Si, I N4 [Effects of the invention As explained above, the present invention For example, the diffusion of the solvent and impurities in the spin-coated film into the bulk region (where the transistor is present) is suppressed, and voids are not formed at the interface between the spin-coated film and the upper thin +1 layer. Therefore, a method for manufacturing a semiconductor device is provided that enables a highly reliable manufacturing process having a highly integrated multilayer wiring structure.
以上that's all
Claims (1)
層、ワニス状態でスピンナー塗布し、熱硬化させること
により無機または有機の絶縁膜を用いる半導体装置にお
いて、該スピン塗布絶縁膜形成後の工程における熱処理
温度は、該熱硬化温度を越えないことを特徴とする半導
体装置の製造方法。In a semiconductor device using an inorganic or organic insulating film, at least one layer is spin-coated in a varnish state on the wiring interlayer film of an IC having multilayer metal wiring and cured by heat, and heat treatment is performed in a step after forming the spin-coated insulating film. A method for manufacturing a semiconductor device, characterized in that the temperature does not exceed the thermosetting temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25820489A JPH03120745A (en) | 1989-10-03 | 1989-10-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25820489A JPH03120745A (en) | 1989-10-03 | 1989-10-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03120745A true JPH03120745A (en) | 1991-05-22 |
Family
ID=17316957
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25820489A Pending JPH03120745A (en) | 1989-10-03 | 1989-10-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03120745A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160081625A (en) * | 2014-12-31 | 2016-07-08 | 손현우 | Recyclable box |
-
1989
- 1989-10-03 JP JP25820489A patent/JPH03120745A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160081625A (en) * | 2014-12-31 | 2016-07-08 | 손현우 | Recyclable box |
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