JPH0329308B2 - - Google Patents
Info
- Publication number
- JPH0329308B2 JPH0329308B2 JP59212972A JP21297284A JPH0329308B2 JP H0329308 B2 JPH0329308 B2 JP H0329308B2 JP 59212972 A JP59212972 A JP 59212972A JP 21297284 A JP21297284 A JP 21297284A JP H0329308 B2 JPH0329308 B2 JP H0329308B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- layer
- organic insulating
- silicone rubber
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 42
- 238000000034 method Methods 0.000 description 15
- 239000010408 film Substances 0.000 description 13
- 229920002379 silicone rubber Polymers 0.000 description 12
- 239000004945 silicone rubber Substances 0.000 description 12
- 239000004033 plastic Substances 0.000 description 9
- 230000001681 protective effect Effects 0.000 description 8
- 239000011347 resin Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 239000013039 cover film Substances 0.000 description 7
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000002966 varnish Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012634 fragment Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006388 chemical passivation reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000010137 moulding (plastic) Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はプラスチツクモールドによる封止時
の、樹脂の射出による衝撃を緩和する被膜を具え
た半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device provided with a coating that cushions the impact of resin injection during sealing with a plastic mold.
従来大規模集積回路LSI等半導体装置のパツシ
ベーシヨンのため、気相成長CVD法による燐珪
酸ガラスPSG等無機物の絶縁膜よりなるカバー
膜を基板上に被着する。 Conventionally, for passivation of semiconductor devices such as large-scale integrated circuits LSI, a cover film made of an insulating film of an inorganic material such as phosphosilicate glass PSG is deposited on a substrate by a vapor phase growth CVD method.
このカバー膜は化学的なパツシベーシヨンの作
用には有効であるが、機械的な衝撃や、圧力に対
しては余り効果がない。 Although this cover film is effective against chemical passivation, it is not very effective against mechanical impact or pressure.
特にLSIの封止にプラスチツクモールドが使用
されるときは、樹脂射出圧により、基板表面に及
ぼされる応力のために基板表面に被着されたカバ
ー膜にクラツクを生じ、甚だしい場合は基板が
粉々に破砕することがある。 Particularly when plastic molds are used to encapsulate LSIs, the stress exerted on the substrate surface by resin injection pressure can cause cracks in the cover film attached to the substrate surface, and in extreme cases, the substrate may shatter. May shatter.
プラスチツクパツケージは量産品種のLSIには
多用されているため、これらの欠点に対する対策
が要望されている。 Since plastic packages are widely used in mass-produced LSIs, there is a need for countermeasures against these drawbacks.
第２図は従来例による保護膜を有するプラスチ
ツクモールドLSIの断面図である。
FIG. 2 is a sectional view of a conventional plastic molded LSI having a protective film.
図において、１は半導体チツプでステージ３の
上にダイボンデイングされ、チツプ１の周辺に形
成されたパツド（接続端子）２とリード４とをワ
イヤ５によりボンデイングする。 In the figure, a semiconductor chip 1 is die-bonded onto a stage 3, and pads (connection terminals) 2 formed around the chip 1 and leads 4 are bonded using wires 5.
つぎに、モールド工程の前に予め、チツプの応
力吸収、保護のため柔軟なシリコーン等の樹脂６
を滴下してチツプを被覆しておく。 Next, before the molding process, a flexible resin such as silicone 6 is used to absorb stress and protect the chip.
Drip to coat the chips.
その後にモールド工程により樹脂７でパツケー
ジングする。 Thereafter, it is packaged with resin 7 in a molding process.
プラスチツクモールドLSIにおいて、従来例に
よるチツプ上への樹脂の滴下はアセンブリ工程で
１個宛行うため、精度、生産性の面で問題があつ
た。
In conventional plastic molded LSIs, resin is dripped onto the chip one by one during the assembly process, which poses problems in terms of accuracy and productivity.
上記問題点の解決は、半導体基板上にスピンコ
ート形成されパターニング形成されてなる有機物
絶縁層と、
該有機物絶縁層を損傷しないような低温にて、
該有機物絶縁層表面をすべて覆うように形成され
てなる無機物絶縁層と、
該無機物絶縁層表面を覆うように、また前記半
導体基板を覆うように形成され、絶縁物からなる
パツケージと
を有する半導体装置により達成される。
The solution to the above problem is to use an organic insulating layer formed by spin coating and patterning on a semiconductor substrate, and at a low temperature that does not damage the organic insulating layer.
A semiconductor device comprising: an inorganic insulating layer formed to completely cover the surface of the organic insulating layer; and a package made of an insulator formed to cover the surface of the inorganic insulating layer and the semiconductor substrate. This is achieved by
特に前記有機物絶縁層がシリコーンゴムよりな
り、また前記無機物絶縁体がプラズマ気相成長に
よる絶縁層よりなる場合は一層有効である。 It is particularly effective when the organic insulating layer is made of silicone rubber and the inorganic insulating material is made of an insulating layer formed by plasma vapor deposition.
従来アセンブリ工程において滴下法によりシリ
コーンゴム保護膜を形成したのに対して、本発明
はウエハ工程において行う。即ち、シリコーンゴ
ムワニスをウエハ上にスピン塗布して所定の保護
膜パターンを形成し、その上に低温プロセスのプ
ラズマCVD膜を被着し同じパターンを形成し、
この２層によりチツプの保護を行う。
While the silicone rubber protective film was conventionally formed by a dropping method in the assembly process, in the present invention it is formed in the wafer process. That is, silicone rubber varnish is spin-coated onto a wafer to form a predetermined protective film pattern, and then a low-temperature process plasma CVD film is deposited on top of it to form the same pattern.
These two layers protect the chip.
シリコンゴムのような柔軟な有機物絶縁層は、
スピンコートしてパターニング形成するという通
常のウエハ工程によつて形成でき、樹脂を用いた
場合に滴下法によらねばならないのに比較すると
顕著に工程が容易になり、歩留まり向上に寄与す
るところが大きい。同時にシリコンゴムのような
柔軟な有機物絶縁層は、外部応力の吸収に効果的
に働く。しかしながら、このような有機物絶縁層
は一般的に下地であるシリコン層との密着性が良
くなく、大きい外力によつては剥離してしまいが
ちである。また、有機物絶縁層は、半導体の破片
がダイシング時に飛び散つたりすると、この破片
がめり込んでしまい、この有機物絶縁層は塑性変
形してしまうことが多い。 Flexible organic insulation layers such as silicone rubber
It can be formed by a normal wafer process of spin coating and patterning, and compared to the drop method that must be used when resin is used, the process is significantly easier and greatly contributes to improved yield. At the same time, a flexible organic insulating layer such as silicone rubber works effectively to absorb external stress. However, such an organic insulating layer generally does not have good adhesion to the underlying silicon layer, and tends to peel off due to large external forces. Furthermore, when semiconductor fragments are scattered during dicing, the organic insulating layer often gets stuck in the organic insulating layer and the organic insulating layer is plastically deformed.
本発明では、このような有機物絶縁層の全面を
無機物絶縁層で覆うから、半導体基板から剥離す
ることを確実に防ぐことができる。さらには、こ
の無機物絶縁層が有機物絶縁層の殻となつて、飛
散した半導体の破片が有機物絶縁層につきささつ
て残るのを防ぐことにもなる。 In the present invention, since the entire surface of such an organic insulating layer is covered with an inorganic insulating layer, peeling from the semiconductor substrate can be reliably prevented. Furthermore, this inorganic insulating layer acts as a shell for the organic insulating layer, and prevents scattered semiconductor fragments from remaining on the organic insulating layer.
シリコーンゴムは耐熱性に乏しいので、CVD
工程は十分低温で行い、被着する膜は極力薄く
し、下層のシリコーンゴムの柔軟性を損なわない
ようにする。 Silicone rubber has poor heat resistance, so CVD
The process is carried out at a sufficiently low temperature, and the applied film is made as thin as possible so as not to impair the flexibility of the underlying silicone rubber.
第１図は本発明による保護膜を有するプラスチ
ツクモールドLSIの断面図である。
FIG. 1 is a sectional view of a plastic molded LSI having a protective film according to the present invention.
図において、１１はｐ型珪素（Si）よりなるチ
ツプ、１２，１３はn+型のソース、ドレイン領
域、１４はゲート酸化膜、１５Ｓ，１５Ｇ，１５
Ｄは多結晶珪素層、１６はPSGよりなる層間絶
縁層、１７はアルミニウムよりなる配線層、１８
はPSGよりなるカバー膜、１９は有機物絶縁層
としてシリコーンゴム層、２０は無機物絶縁層と
してプラズマCVDによる窒化珪素（Si3N4）層
で、チツプ１１の周辺においてSi3N4層２０とシ
リコーンゴム層１９とカバー膜１８が開口されて
配線層１７が露出され、ボンデイングパツドとし
て使用される。 In the figure, 11 is a chip made of p-type silicon (Si), 12 and 13 are n + type source and drain regions, 14 is a gate oxide film, 15S, 15G, 15
D is a polycrystalline silicon layer, 16 is an interlayer insulating layer made of PSG, 17 is a wiring layer made of aluminum, 18
is a cover film made of PSG, 19 is a silicone rubber layer as an organic insulating layer, 20 is a silicon nitride (Si 3 N 4 ) layer made by plasma CVD as an inorganic insulating layer, and the Si 3 N 4 layer 20 and silicone are formed around the chip 11. Rubber layer 19 and cover film 18 are opened to expose wiring layer 17, which is used as a bonding pad.
具体的な製造工程の例はつぎの通りである。 A specific example of the manufacturing process is as follows.
まずすべてのウエハ工程を終えた後、即ち裏面
の金蒸着を終えた後、シリコーンゴムワニスをウ
エハ上にスピン塗布する。シリコーンゴムワニス
は工程短縮のため、感光性のものを用いた。100
℃で30分程度のベークを行つた後、所定のパター
ン（パツドを含むチツプ周辺部を除いて、回路パ
ターンを覆う長方形のパターン）を焼き付け、
UVキユア（紫外線照射）により200℃で２時間
程度の熱処理を行つて、厚さ約5μmのシリコーン
ゴム層１９を得る。 First, after all wafer processes have been completed, that is, gold deposition on the back side has been completed, silicone rubber varnish is spin-coated onto the wafer. A photosensitive silicone rubber varnish was used to shorten the process. 100
After baking at ℃ for about 30 minutes, a prescribed pattern (a rectangular pattern that covers the circuit pattern, excluding the area around the chip including the pads) is baked.
A heat treatment is performed at 200° C. for about 2 hours using UV cure (ultraviolet irradiation) to obtain a silicone rubber layer 19 with a thickness of about 5 μm.
つぎにプラズマCVDにより厚さ300ÅのSi3N4
層２０を被着し、此の上にレジストを塗布し、露
光、現像を経てシリコーンゴム層１９と同じパタ
ーンをレジストに形成し、ドライエツチングによ
りSi3N4層２０のパターンを形成する。 Next, Si 3 N 4 with a thickness of 300 Å was formed by plasma CVD.
A layer 20 is deposited, a resist is applied thereon, exposed and developed to form the same pattern as the silicone rubber layer 19 on the resist, and a pattern of the Si 3 N 4 layer 20 is formed by dry etching.
この後に、ウエハをチツプにスクライブして、
アセンブリ工程に入る。 After this, the wafer is scribed into chips,
Start the assembly process.
実施例では無機物絶縁層としてプラズマCVD
によるSi3N4層を用いたが、これの代わりにプラ
ズマCVDによる二酸化珪素（SiO2）層等を用い
てもよい。 In the example, plasma CVD was used as the inorganic insulating layer.
Although a Si 3 N 4 layer was used, a silicon dioxide (SiO 2 ) layer formed by plasma CVD or the like may be used instead.
以上詳細に説明したように本発明によれば、プ
ラスチツクモールドLSIにおいて、チツプ上の保
護膜の形成をウエハ工程で行い、多数同時処理が
でき生産性が向上し、またリソグラフイ工程を用
いて精度よく形成できる。
As explained in detail above, according to the present invention, in plastic molded LSI, the formation of a protective film on a chip is performed in the wafer process, and a large number of chips can be processed simultaneously, improving productivity. Can be formed well.
以上のように形成した保護膜により、プラスチ
ツクモールド時の樹脂射出による衝撃を緩和して
カバー膜にクラツクを生じさせない信頼性の高い
LSIが得られる。 The protective film formed as described above alleviates the impact caused by resin injection during plastic molding and is highly reliable, preventing cracks from occurring in the cover film.
LSI is obtained.
第１図は本発明による保護膜を有するプラスチ
ツクモールドLSIの断面図、第２図は従来例によ
る保護膜を有するプラスチツクモールドLSIの断
面図である。
図において、１はチツプ、２はパツド、３はス
テージ、４はリード、５はワイヤ５、６は滴下さ
れた樹脂、７はパツケージ、１１はチツプ、１
２，１３はソース、ドレイン領域、１４はゲート
酸化膜、１５Ｓ，１５Ｇ，１５Ｄは多結晶珪素
層、１６は層間絶縁層、１７は配線層、１８はカ
バー膜、１９は有機物絶縁層、２０は無機物絶縁
層を示す。
FIG. 1 is a sectional view of a plastic molded LSI having a protective film according to the present invention, and FIG. 2 is a sectional view of a plastic molded LSI having a conventional protective film. In the figure, 1 is a chip, 2 is a pad, 3 is a stage, 4 is a lead, 5 is a wire 5, 6 is a dropped resin, 7 is a package, 11 is a chip, 1
2 and 13 are source and drain regions, 14 is a gate oxide film, 15S, 15G, and 15D are polycrystalline silicon layers, 16 is an interlayer insulation layer, 17 is a wiring layer, 18 is a cover film, 19 is an organic insulation layer, and 20 is a Shows an inorganic insulating layer.
Claims (1)
ニング形成されてなる有機物絶縁層と、 該有機物絶縁層を損傷しないような低温にて、
該有機物絶縁層表面をすべて覆うように形成され
てなる無機物絶縁層と、 該無機物絶縁層表面を覆うように、また前記半
導体基板を覆うように形成され、絶縁物からなる
パツケージと を有する半導体装置。[Claims] 1. An organic insulating layer formed by spin coating and patterning on a semiconductor substrate; and at a low temperature that does not damage the organic insulating layer.
A semiconductor device comprising: an inorganic insulating layer formed to completely cover the surface of the organic insulating layer; and a package made of an insulator formed to cover the surface of the inorganic insulating layer and the semiconductor substrate. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59212972A JPS6190450A (en) | 1984-10-11 | 1984-10-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59212972A JPS6190450A (en) | 1984-10-11 | 1984-10-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6190450A JPS6190450A (en) | 1986-05-08 |
| JPH0329308B2 true JPH0329308B2 (en) | 1991-04-23 |
Family
ID=16631344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59212972A Granted JPS6190450A (en) | 1984-10-11 | 1984-10-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6190450A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2649157B2 (en) * | 1987-03-10 | 1997-09-03 | 三菱電機株式会社 | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5056164A (en) * | 1973-09-13 | 1975-05-16 | ||
| JPS52104060A (en) * | 1976-02-27 | 1977-09-01 | Hitachi Ltd | Resin mold type semiconductor device |
-
1984
- 1984-10-11 JP JP59212972A patent/JPS6190450A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6190450A (en) | 1986-05-08 |
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