JPS5986246A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the reliability of an element by coating the oxy derivatives of silicon on a PSG film covered on a semiconductor device, heat treating it to covert it into the PSG film, and etching it, thereby enabling to flatten the PSG film at a low temperature and eliminating a slender crack of the insulating film. CONSTITUTION:A PSG films 2 of interlayer insulating film and lower aluminum wirings are formed on a silicon substrate 1, and a PSG film 5 is covered. After oxy derivatives of silicon which contains phosphorus such as silanol is rotatably coated, a heat treatment is performed to convert silanol which contains phosphorus into a PSG film 4. Then, the film 4 which is formed from the silanol by fluoric acid, aqueous ammon fluoride solution is completely etched and removed. At this time, part of the film 5 is simultaneously etched to be flattened. Subsequently, the through hole is opened, and upper aluminum layer wirings are formed to complete it.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for flattening the surface of a film in the device.

Conventional Structure and Problems In semiconductor devices, electrodes are formed on an insulating film, so flatness of the film surface is important.

Conventionally, as an example of flattening technology, there is a reflow technique in which a phosphosilicate glass (hereinafter referred to as PSG) film is heated and melted to flatten the surface. In devices, short channel effects become a problem. In addition, regarding the multilayer wiring technology required for high integration of semiconductor devices, when A4 is used for the wiring, there is
The reflow technique, which requires high temperatures, cannot be applied to planarize the surface of SC. There are various techniques for flattening an element at a relatively low temperature, and an example thereof will be explained with reference to FIG.

FIG. 1 is a diagram showing the step in which planarization is most required in the 62-layer wiring technology, that is, the step of planarizing the PSG film covering the lower layer Al wiring, which is required when forming the upper layer A5 wiring. For the sake of simplicity, the figure shows the step portion caused by the lower layer interconnection, and intentionally does not show the cross section of the transistor region.

As shown in the figure, first, a PSG film 2f is formed as an interlayer insulating film on a silicon substrate 1, and then a lower layer interconnection 3 with a film thickness of 800 l is formed using a photoetching technique (see Fig. 1). ]. After this, silanol containing phosphorus is spin-coated and further heat-treated at 450'C to convert the silanol into a PSG film 4 [Fig. 1(b)]. Next, the film thickness is aooo Depositing the PSG film 6 [Fig. 1(d)
)]. This completes the planarization process, and after that, through holes are opened and upper layer Al wiring is formed to complete the process. However, in the planarization method performed in this way, 45
The heat treatment at 0° C. causes thin cracks in the region of the PSG film 40 formed from silanol that contacts the lower layer Al wiring. In order to prevent this, after forming the lower layer Al wiring, a PSG film 6 is first coated [FIG. 1(d)], and then silanol is spin-coated and heat treated at 460°C to form silanol f PSG. 4 [Figure 1 (C
)] After this, a method of forming through-holes and upper layer interconnections is also performed, but in this case, the PSG film formed from silanol remains in the semiconductor element, so trace amounts of metal ions etc. contained in silanol are left behind. Impurities pose a problem in the reliability of semiconductor devices.

In addition, when Ag sintering treatment at approximately 460°C is performed after forming the upper layer Ag wiring, PSG formed from silanol also
There was a problem in that thin cracks were generated at the contact surface of the upper layer of the film with Al.

Purpose of invention The present invention solves these problems.

That is, the present invention relates to a method of manufacturing a semiconductor device that allows flattening of a PSG film or a silicon oxide film at low temperatures, eliminates thin cracks in the insulating film, and has excellent element reliability.

Structure of the Invention The present invention involves spin-coating a silicon oxy derivative on a silicon oxide film or PEG film deposited on a semiconductor substrate having steps, and then subjecting the silicon oxy derivative to heat treatment 1 [i] to coat the silicon oxide film or PEG film. Planarization is achieved by replacing the silicon oxide film with a PSG film and etching a portion of the silicon oxide film or PSG film deposited on the semiconductor substrate from this silicon oxide film or PSG film.

DESCRIPTION OF EMBODIMENTS As an example, an embodiment of a method for manufacturing an r'Ios type semiconductor device employing the PSG film planarization method according to the present invention in the h12 layer wiring technology will be described with reference to FIG.

As shown in the figure, first, a predetermined ho is placed on a silicon substrate 1.
After forming a cos oxide film, a gate oxide film, a polysilicon gate, a source, and a drain diffusion layer, a PSG film 2, which is an interlayer insulating film, is formed to cover these layers, and then a film with a thickness of 800 μm is formed using photoetching technology. Lower layer wiring 3
[Fig. 2 (!L), l. After this, the film thickness is 16
A PSG film 6 of 000A is deposited [FIG. 2(b)]. Furthermore, after spin-coating a phosphorous-containing silicon oxy derivative, such as silanol, a heat treatment at 460'C is carried out to convert it into an 11-containing silanol Ipsc; film 4 (FIG. 2(0)). Next, the PSG film formed from phosphorus-containing silanol is completely etched away using hydrofluoric acid and ammonium fluoride-based aqueous solution. At this time, a part of the PEG film deposited on the lower layer Al wiring is also etched at the same time.
(FIG. (li)) This completes the planarization process, and after that, through holes are opened and upper layer interconnections are formed to complete the process.

In the case of this example, for example, P formed from silanol
Since the SG film is completely removed by etching, impurities such as metal ions in silanol have little effect on the reliability of the semiconductor device, compared to the conventional example.

Also, naturally, the PSG film formed from silanol does not leak directly onto the lower and upper layer interconnects, and
No thin cracks occur in the PSG film during the heat treatment.

DESCRIPTION OF EMBODIMENTS According to the present invention, as described above, it is possible to flatten a PSG film at a temperature as low as 460'C, and at the same time, it is possible to improve the reliability of a semiconductor device.

Note that although the above embodiments have been described with respect to planarization of a PS film, similar effects can be obtained in the case of planarization of a silicon oxide film that does not contain phosphorus by using an oxy derivative of silicon that does not contain phosphorus, such as silanol. is obtained.

Further, in this embodiment, a case was described in which the A12 layer wiring process was carried out, but the present invention can be applied to the planarization of silicon oxide films or PSG films in general.

[Brief explanation of drawings]

Figure 1 (a), (t)), (C), (d)
, (6) are cross-sectional views showing the manufacturing process for explaining the prior art, and FIGS. 2(a) and 2(b). (C) and (d) are cross-sectional views showing manufacturing steps for explaining one embodiment of the present invention. 1...Silicon substrate, 2.4.5...
Phosphorsilicate glass, 3... Lower layer Al wiring. Name of first substitute Patent attorney Toshio Nakao and one other person Figure 1 No. (d) (
1,) (eJ(CI second factor ta) (d)

Claims (1)

[Claims] a step of depositing a silicon oxide film or a phosphosilicate glass film on a semiconductor substrate surface on which circuit elements and electrode/wiring films are provided; and a step of spin-coating a silicon oxy derivative on the silicon oxide film or phosphosilicate glass film. , a step of converting the applied silicon oxy derivative into a silicon oxide film by heat treatment, and a part of the silicon oxide film or phosphosilicate glass film deposited on the semiconductor substrate surface from the silicon oxide film formed by the conversion. 1. A method for manufacturing a semiconductor device, comprising etching over a wide area.