KR970018689A - MOS field effect transistor manufacturing method - Google Patents

MOS field effect transistor manufacturing method Download PDF

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Publication number
KR970018689A
KR970018689A KR1019950030715A KR19950030715A KR970018689A KR 970018689 A KR970018689 A KR 970018689A KR 1019950030715 A KR1019950030715 A KR 1019950030715A KR 19950030715 A KR19950030715 A KR 19950030715A KR 970018689 A KR970018689 A KR 970018689A
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South Korea
Prior art keywords
gate
sidewall
forming
insulating film
polysilicon
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KR1019950030715A
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Korean (ko)
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KR100206864B1 (en
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김인
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문정환
엘지반도체 주식회사
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Publication of KR970018689A publication Critical patent/KR970018689A/en
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Publication of KR100206864B1 publication Critical patent/KR100206864B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 모스 전계효과트랜지스터 제조방법에 관한 것으로, 반도체 기판 상에 제1 게이트 절연막 및 상기 제1 게이트 절연막 상에 폴리실리콘을 형성하는 공정과; 상기 폴리실리콘 상에 절연막 패턴을 형성하는 공정과; 상기 절연막 패턴 측면에 산화방지막의 제1 측벽을 형성하는 공정과; 상기 절연막 패턴 및 제1 측벽을 마스크로 폴리실리콘을 식각하여 게이트를 형성하는 공정과; 상기 게이트 측면에 제2 측벽을 형성하는 공정과; 산화공정을 실시하여 게이트 에지 영역과 기판위에 제2 게이트 절연막을 형성하는 공정 및; 상기 게이트 및 제2 측벽을 마스크로 하여, 기판에 불순물 이온을 주입하는 공정을 포함하여 소자 제조를 완료하므로써, 1) GBB(gate bird's beak)의 채널 침투 현상을 효과적으로 차단하고, 소오스/드레인 정션의 게이트 오버랩된 영역에만 두꺼운 게이트 산화막을 형성할 수 있게 도어 트랜지스터의 트랜스컨덕턴스 감소 없이도 종래 T형 게이트 MOSFET 기술의 잇점을 그대로 얻을 수 있으며, 2) 산화 공정시 야기되는 트랜지스터의 특성 변화를 최소화할 수 있고, 3) 샤프(sharp)한 GBB 종단면도(profile)로 정션 오버랩된 영역의 전계차단효과를 극대화할 수 있는 고신뢰성의 반도체 소자를 구현할 수 있게 된다.The present invention relates to a method of manufacturing a MOS field effect transistor, comprising: forming a first gate insulating film on a semiconductor substrate and polysilicon on the first gate insulating film; Forming an insulating film pattern on the polysilicon; Forming a first sidewall of the anti-oxidation film on the sidewall of the insulating film pattern; Forming a gate by etching polysilicon using the insulating layer pattern and the first sidewall as a mask; Forming a second sidewall at the gate side; Performing an oxidation process to form a second gate insulating film on the gate edge region and the substrate; By completing the device fabrication process including implanting impurity ions into the substrate using the gate and the second sidewall as a mask, 1) effectively blocking channel penetration of gate bird's beak (GBB) and providing a source / drain junction In order to form a thick gate oxide film only in the region where the gate overlaps, it is possible to take advantage of the conventional T-type gate MOSFET technology without reducing the transconductance of the door transistor, and 2) to minimize the change in characteristics of the transistor caused during the oxidation process. 3) Sharp GBB profile enables high reliability semiconductor devices to maximize the field-blocking effect of junction overlapped areas.

Description

모스 전계효과트랜지스터 제조방법MOS field effect transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2(가)도 내지 제2(다)도는 본 발명에 따른 T형 게이트 모스 전계효과트랜지스터 제조방법을 도시한 공정수순도.2 (a) to 2 (c) are process steps showing a method of manufacturing a T-type gate MOS field effect transistor according to the present invention.

Claims (4)

반도체 기판 상에 제1 게이트 절연막 및 상기 제1 게이트 절연막 상에 폴리실리콘을 형성하는 공정과; 상기 폴리실리콘 상에 절연막 패턴을 형성하는 공정과; 상기 절연막 패턴 측면에 산화방지막의 제1 측벽을 형성하는 공정과; 상기 절연막 패턴 및 제1 측벽을 마스크로 폴리실리콘을 식각하여 게이트를 형성하는 공정과; 상기 게이트 측면에 제2 측벽을 형성하는 공정과; 산화공정을 실시하여 게이트 에지 영역과 기판위에 제2 게이트 절연막을 형성하는 공정 및; 상기 게이트 및 제2 측벽을 마스크로 하여, 기판에 불순물 이온을 주입하는 공정을 포함하여 형성되는 것을 특징으로 하는 모스 전계효과트랜지스터 제조방법.Forming a first gate insulating film on the semiconductor substrate and polysilicon on the first gate insulating film; Forming an insulating film pattern on the polysilicon; Forming a first sidewall of the anti-oxidation film on the sidewall of the insulating film pattern; Forming a gate by etching polysilicon using the insulating layer pattern and the first sidewall as a mask; Forming a second sidewall at the gate side; Performing an oxidation process to form a second gate insulating film on the gate edge region and the substrate; And implanting impurity ions into the substrate using the gate and the second sidewall as a mask. 제1항에 있어서, 상기 제1 측벽은 질화막으로 형성되는 것을 특징으로 하는 모스 전계효과트랜지스터 제조방법.The method of claim 1, wherein the first sidewall is formed of a nitride film. 제1항에 있어서, 상기 제1 측벽은 제1 절연막 패턴 및 폴리실리콘 상에 질화막을 증착한 후, 이를 에치백하여 형성하는 것을 특징으로 하는 모스 전계효과트랜지스터 제조방법.The method of claim 1, wherein the first sidewall is formed by depositing a nitride film on the first insulating film pattern and the polysilicon, and then etching back the nitride film. 제1항에 있어서, 상기 제2 측벽은 산화막으로 형성되는 것을 특징으로 하는 모스 전계효과트랜지스터 제조방법.The method of claim 1, wherein the second sidewall is formed of an oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950030715A 1995-09-19 1995-09-19 Moa field effect transistor and a method of fabricating the same KR100206864B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950030715A KR100206864B1 (en) 1995-09-19 1995-09-19 Moa field effect transistor and a method of fabricating the same

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Application Number Priority Date Filing Date Title
KR1019950030715A KR100206864B1 (en) 1995-09-19 1995-09-19 Moa field effect transistor and a method of fabricating the same

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Publication Number Publication Date
KR970018689A true KR970018689A (en) 1997-04-30
KR100206864B1 KR100206864B1 (en) 1999-07-01

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