KR0143705B1 - Method for preventing ion penetration - Google Patents
Method for preventing ion penetrationInfo
- Publication number
- KR0143705B1 KR0143705B1 KR1019940013543A KR19940013543A KR0143705B1 KR 0143705 B1 KR0143705 B1 KR 0143705B1 KR 1019940013543 A KR1019940013543 A KR 1019940013543A KR 19940013543 A KR19940013543 A KR 19940013543A KR 0143705 B1 KR0143705 B1 KR 0143705B1
- Authority
- KR
- South Korea
- Prior art keywords
- polysilicon
- film
- semiconductor device
- conductive film
- hydrogen ions
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Abstract
본 발명은 반도체 소자 전도막의 이온침투방지방법에 있어서, 전도막 형성 단계; 상기 전도막 상에 수소이온이 침투되는 것을 방지하기 위하여 이온차단막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자 전도막의 이온침투방지방법에 관한 것으로, 보호막 하부의 전도막에 차단막에 캐핑함으로써 수소이온의 침투로 인한 부하저항의 감소를 방지하여 반도체 소자의 전기적인 특성을 유지하고 보다 집적화된 반도체 소자의 구성을 가능케 하는 효과가 있다.The present invention provides a method for preventing ion penetration of a semiconductor device conductive film, the method comprising: forming a conductive film; A method of preventing ion permeation of a semiconductor device conductive film, the method comprising: forming an ion barrier film to prevent hydrogen ions from penetrating on the conductive film, by capping the conductive film under the protective film to a blocking film. By preventing the reduction of the load resistance due to the penetration of hydrogen ions has the effect of maintaining the electrical characteristics of the semiconductor device and enable the construction of a more integrated semiconductor device.
Description
제1도는 종래기술에 따라 형성된 SRAM의 단면도.1 is a cross-sectional view of an SRAM formed in accordance with the prior art.
제2a도 내지 제2c도는 본 발명의 일실시예에 따른 SRAM 제조 공정도.2A through 2C are SRAM manufacturing process diagrams according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10:층간절연막 20:금속 배선10: interlayer insulating film 20: metal wiring
30:패시베이션 질화막 40,50:폴리실리콘 전도 라인30: passivation nitride film 40, 50: polysilicon conduction line
60:폴리실리콘막 70:반도체 기판60: polysilicon film 70: semiconductor substrate
본 발명은 반도체 제조 분야에 관한 것으로, 특히 SRAM 등의 반도체 장치 제조시 수소 이온의 침투에 의한 저항 감소를 방지하는 반도체 장치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method of manufacturing a semiconductor device which prevents a decrease in resistance due to penetration of hydrogen ions in the manufacture of semiconductor devices such as SRAM.
일반적으로, 반도체 소자, 특히 SRAM에서 로드(load) 저항은 중요한 요소 중의 하나이며 SRAM의 집적도가 높아질수록 그 중요성은 증대된다.In general, load resistance is one of the important factors in semiconductor devices, particularly SRAMs, and the importance increases as the degree of integration of the SRAM increases.
첨부된 도면 제1도는 종래 기술에 따라 SRAM의 전도막과 패시베이션(passivation) 질화막을 형성한 후의 상태를 나타낸 단면도로서, 상기 도면에 따라 종래 기술을 설명하면, 먼저 소정의 하부층 공정이 완료된 반도체 기판(7)상의 소정 부분에 제1 폴리실리콘 전도 라인(4)을 형성한 다음, 그 상부에 제1 폴리실리콘 전도막과 절연을 이루는 제2 폴리실리콘 전도 라인(5)을 형성한다. 이때, 제2 폴리실리콘 전도 라인(5)은 그 소정 영역을 로드 저항으로 사용하기 위하여 로드(load) 이온주입을 실시한 상태이며, 전체 라인의 전도성을 부여하기 위하여 상기 로드 이온주입된 영역을 제외한 나머지 부분에 이온주입을 실시한 상태이다. 계속하여, 전체구조 상부에 층간절연막(1)을 증착하고, 사진 및 식각 공정을 실시하여 금속 콘택(metal contact)부분을 오픈(open)시킨 다음, 금속 배선(2)을 형성한다. 이어서, 전체구조 상부에 플라즈마 화학기상증착(plasma enhanced chemical vapor deposition; 이하 PECVD라 칭함) 방식으로 패시베이션 질화막(3)을 증착한다.1 is a cross-sectional view illustrating a state after forming a conductive film and a passivation nitride film of an SRAM according to the prior art. Referring to the prior art according to the drawing, a semiconductor substrate having a predetermined lower layer process is completed first. A first polysilicon conductive line 4 is formed in a predetermined portion on 7), and a second polysilicon conductive line 5 insulated from the first polysilicon conductive film is formed thereon. At this time, the second polysilicon conductive line 5 is a state in which load ion implantation is performed to use the predetermined region as a load resistance, and the rest of the second polysilicon conductive line 5 is excluded except the region in which the load ion implantation is performed to impart conductivity of the entire line. It is a state which ion implantation was performed to the part. Subsequently, the interlayer insulating film 1 is deposited on the entire structure, a photo contact and an etching process are performed to open the metal contact portion, and then the metal wiring 2 is formed. Subsequently, the passivation nitride film 3 is deposited on the entire structure by plasma enhanced chemical vapor deposition (hereinafter referred to as PECVD).
그런데, 상술한 바와 같은 공정을 진행한 경우, 패시베이션 질화막(3) 증착시 플라즈마 장비에서 발생되는 수소 이온이 노출된 제2 폴리실리콘 전도 라인(5)으로 침투하게 되고, 이로 인해 상대적으로 저항이 높은 로드(load) 영역이 영향을 받아 로드 영역의 저항이 감소하여 SRAM의 전기적 특성 유지가 불가능한 문제점이 있었다.However, when the process as described above is performed, hydrogen ions generated in the plasma equipment during the deposition of the passivation nitride film 3 penetrate into the exposed second polysilicon conducting line 5, which causes relatively high resistance. The load region is affected, so the resistance of the load region is reduced, so that the electrical characteristics of the SRAM cannot be maintained.
상기 문제점을 해결하기 위하여 안출된 본 발명은 플라즈마 증착 장비 내에서 발생하는 수소 이온의 폴리실리콘 전도 라인으로의 침투가 억제된 반도체 장치를 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a semiconductor device in which the penetration of hydrogen ions generated in the plasma deposition equipment into the polysilicon conductive line is suppressed.
상기 목적을 달성하기 위하여 본 발명의 반도체 장치는 로드 저항 영역을 포함하는 폴리실리콘 전도 라인; 상기 폴리실리콘 전도 라인 상부에 제공되되, 플라즈마 방식으로 증착된 소정의 절연막; 및 상기 절연막을 통한 상기 폴리실리콘 전도 라인으로의 침투하는 수소 이온을 포휙하기 위하여 상기 폴리실리콘 전도 라인 상부 및 측면에 캐핑된 폴리실리콘막을 포함하여 이루어진다.In order to achieve the above object, the semiconductor device of the present invention includes a polysilicon conductive line including a load resistance region; A predetermined insulating film provided over the polysilicon conductive line and deposited in a plasma manner; And a polysilicon film capped over and on the side of the polysilicon conduction line to trap hydrogen ions penetrating into the polysilicon conduction line through the insulating film.
이하, 첨부된 도면 제2a도 내지 제2c도를 참조하여 본 발명의 일실시예에 따른 반도체 장치 제조 공정을 설명한다.Hereinafter, a semiconductor device manufacturing process according to an exemplary embodiment will be described with reference to FIGS. 2A through 2C.
먼저, 제2a도에 도시된 바와 같이 소정의 하부층 공정을 마친 반도체 기판(70) 상의 소정 부분에 제1 폴리실리콘 전도 라인(40)을 형성한 다음, 그와 절연을 이루는 제2폴리실리콘 전도 라인(50)을 형성한다. 이때, 제2 폴리실리콘 전도 라인(50)은 통상적인 공정을 통해 로드 이온주입 및 전도 라인 형성을 위한 이온주입을 실시한 상태이다.First, as shown in FIG. 2A, a first polysilicon conductive line 40 is formed in a predetermined portion on the semiconductor substrate 70 that has undergone a predetermined lower layer process, and then a second polysilicon conductive line is insulated therefrom. To form (50). At this time, the second polysilicon conductive line 50 is a state in which the ion implantation for the rod ion implantation and the conductive line formation through a conventional process.
다음으로, 제2b도에 도시된 바와 같이 제2 폴리실리콘 전도 라인(50)이 형성된 전체구조 상부에 불순물이 도핑되지 않은 폴리실리콘막(60)을 증착하고, 사진 및 식각 공정을 진행하여 제2 폴리실리콘 전도 라인(50) 표면을 캡핑(capping)한다. 이때, 제2 폴리실리콘 전도 라인(50) 표면을 캐핑하는 폴리실리콘막(60)은 후속 패시베이션 질화막 증착시 발생되는 수소 이온의 침투 방지 효과를 극대화하기 위하여 가급적 치밀한 구조를 갖도록 수소 이온의 침투 방지 효과를 극대화하기 위하여 가급적 치밀한 구조를 갖도록 증착하며, 전체적인 토폴로지(topology)를 고려하여, 500Å 이하의 두께로 형성한다.Next, as illustrated in FIG. 2B, a polysilicon layer 60 which is not doped with impurities is deposited on the entire structure in which the second polysilicon conductive line 50 is formed, and a photo and etching process is performed to perform a second process. Capping the surface of the polysilicon conducting line 50. In this case, the polysilicon film 60 capping the surface of the second polysilicon conductive line 50 has a structure that prevents penetration of hydrogen ions so as to have a compact structure in order to maximize the prevention of penetration of hydrogen ions generated during subsequent passivation nitride deposition. In order to maximize the deposition as possible to have a dense structure, in consideration of the overall topology (topology), to form a thickness of less than 500Å.
이어서, 제2c도에 도시된 바와 같이 전체구조 상부에 층간절연막(10)을 증착하고, 금속 배선(20)을 형성한 다음, 전체구조 상부에 PECVD 방식을 사용하여 패시베이션 질화막(30)을 증착한다. 패시베이션 질화막(30) 증착시 전위차에 의해 플라즈마 장비에서 수소 이온이 발생하게 되나, 제2 폴리실리콘 전도 라인(50) 라인으로 침투하는 수소 이온을 폴리실리콘막(60)이 포휙할 수 있어 제2 폴리실리콘 전도 라인(50)의 로드 영역의 저항 감소를 막을 수 있게 된다.Subsequently, as shown in FIG. 2C, an interlayer insulating film 10 is deposited on the entire structure, a metal wiring 20 is formed, and then a passivation nitride film 30 is deposited on the entire structure by using a PECVD method. . Hydrogen ions are generated in the plasma equipment due to the potential difference during deposition of the passivation nitride film 30, but the polysilicon film 60 may form hydrogen ions penetrating into the second polysilicon conductive line 50 line, thereby causing the second poly It is possible to prevent the resistance of the load region of the silicon conductive line 50 from decreasing.
상기와 같이 이루어지는 본 발명은 플라즈마 장비 내에서 발생하는 수소 이온의 침투에 인한 로드 저항의 감소를 방지하여 반도체 장치의 전기적 특성을 유지할 수 있으며, 이로 인하여 반도체 장치의 고집적화에 기여하는 효과가 있다.The present invention made as described above can prevent the reduction of the load resistance due to the penetration of hydrogen ions generated in the plasma equipment to maintain the electrical characteristics of the semiconductor device, thereby contributing to the high integration of the semiconductor device.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019940013543A KR0143705B1 (en) | 1994-06-15 | 1994-06-15 | Method for preventing ion penetration |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019940013543A KR0143705B1 (en) | 1994-06-15 | 1994-06-15 | Method for preventing ion penetration |
Publications (2)
Publication Number | Publication Date |
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KR960002491A KR960002491A (en) | 1996-01-26 |
KR0143705B1 true KR0143705B1 (en) | 1998-08-17 |
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KR1019940013543A KR0143705B1 (en) | 1994-06-15 | 1994-06-15 | Method for preventing ion penetration |
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KR19990016403A (en) * | 1997-08-14 | 1999-03-05 | 윤종용 | Handler with torsion-resistant transfer |
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1994
- 1994-06-15 KR KR1019940013543A patent/KR0143705B1/en not_active IP Right Cessation
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KR960002491A (en) | 1996-01-26 |
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