JP3113957B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a MOS transistor
Relates to a semiconductor device having, more particularly, it relates to an improved film structure for reducing MOS transistor degradation due to inter-layer insulating film or these water applied to the case of forming a multilayer interconnection on the top.

[0002]

2. Description of the Related Art In the manufacture of semiconductor integrated circuits, a multi-layer wiring technique has become indispensable with an increase in the degree of integration of an element structure. Numerous tools have been developed for technology.

The means for forming this kind of interlayer insulating film, which has been mainly used in the past, is coated with SOG (a solution containing an organic silane) which can obtain required flatness relatively easily, and is annealed. To form a smooth SiO ₂ film, and recently, a TEOS (tetraethoxysilane) -CVD (chemical vapor reaction) method utilizing a chemical reaction has been used together. Was.

Here, a schematic cross-sectional structure of a conventional semiconductor integrated circuit device including a MOS transistor to which an interlayer insulating film formed by such means is applied is shown in FIG.
Shown in

That is, in the structure shown in FIG. 3, in the conventional device, a gate electrode 2 is provided on a gate oxide film 1 and boron (B) or phosphorus as a first interlayer insulating film 3 is formed thereon. A CVD / SiO ₂ film containing an oxide of (P) is formed, and a first layer connected to the active region on the main surface of the substrate and the gate electrode 2 through an opening in the first layer interlayer insulating film 3. Is formed. Further, by forming a second-layer interlayer insulating film 5 made of a TEOS-CVD film, a SOG film, or the like on these, a step formed by the underlying gate electrode 2 or the first-layer metal wiring layer 4 is formed. Is reduced, and a relatively gentle cross-sectional shape is obtained here. Further, the second wiring layer is formed through the opening in the second interlayer insulating film 5 and the second wiring
The metal wiring layer 6 is formed.

[0006]

However, in the case of the conventional interlayer insulating film formed in this manner, the second
TEOS-CVD film or SOG as interlayer insulating film 5
It is known that a large amount of water as a reaction product is contained in a formed film due to a low film formation temperature of a film or the like.

On the other hand, in this type of MOS transistor, the miniaturization of the MOS transistor causes an increase in the drain electric field, which causes a problem of hot carriers. Deterioration is a very important issue in terms of device reliability.

That is, the above-described coating method using SOG,
Since each interlayer insulating film formed by the TEOS-CVD method contains a large amount of moisture in the film, when this moisture diffuses into the underlying gate oxide film 1, an OH group is formed in the gate oxide film 1. And H groups may be formed to accelerate the deterioration of the device due to hot carriers. Therefore, using an interlayer insulating film obtained by each of these forming methods has a problem in the reliability of the device. .

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem.
Even in the interlayer insulating film formed by TEOS-CVD method, and so no a fear of giving a device degradation due to hot carriers, MOS bets with such a layer insulating film
An object of the present invention is to provide a semiconductor device including a transistor .

[0010]

In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor device on a silicon substrate.
MOS consisting of a gate electrode formed through an oxide film
Transistor, silicon substrate and MOS transistor
One of boron and phosphorus formed on the
MOS transistor consisting of silicon oxide film containing both
An interlayer insulating film to protect the
Silicon oxide film formed by ECR plasma CVD method
Water permeation prevention with high ability to block permeation of water
Film and a metal wiring layer formed on the moisture permeation prevention film.
It is provided with .

[0011]

Accordingly, in the present invention, the MOS transistor
The upper side of the motor, one or either of boron or phosphorus
Both oxides forming an interlayer insulating film by a silicon oxide film containing a, and the interlayer insulating film, ECR plasma CV
Since as with high moisture permeation preventing layer capable of preventing the permeation of moisture made of a silicon oxide film by Method D,
Even if an insulating film formed by a coating method containing a large amount of moisture or an insulating film formed by a chemical vapor deposition method centering on a thermochemical reaction is formed as an interlayer insulating film between the metal wirings, the water content in each insulating film can be reduced. Does not reach the lower semiconductor device region, so that hot carrier deterioration of the element due to moisture can be easily avoided.

[0012]

EXAMPLES Hereinafter, actual施例of a semiconductor device according to the present invention will be described in detail with reference to FIGS.

[0013] Figure 1 is a cross-sectional view schematically showing a semiconductor integrated circuit device including a MOS transistor according to the definitive interlayer insulating film to the first embodiment of the present invention.

In the structure shown in FIG. 1, in the device of the first embodiment, a gate electrode 12 made of a phosphorus-doped polysilicon film or the like is provided on a gate oxide film 11, and boron (B) or the like is formed thereon. CVD containing phosphorus (P) oxide
A first interlayer insulating film 13 of a silicon oxide film or the like is formed, and this is annealed at a temperature of about 800 ° C. to 1000 ° C.

One of the important roles of the first interlayer insulating film 13 is to alleviate the step caused by the formation of the gate electrode 2 on the lower layer side. In the silicon oxide film containing an oxide, fluidity is generated by the annealing treatment at a temperature of about 800 ° C. to 1000 ° C., and the film surface becomes smooth. Another important role is that these B and P
Is to effectively utilize the effect of trapping mobile ions such as Na which adversely affect the characteristics of the MOS transistor and inactivating them.

That is, by using such a silicon oxide film containing oxides of B and P as the first interlayer insulating film 13, it is possible to prevent mobile ions such as Na from entering from the upper layer side, During annealing at a temperature of about 800 ° C. to 1000 ° C., mobile ions such as Na that have penetrated in the device forming process into the MOS device region on the lower layer side are also absorbed to protect the device from contamination by the mobile ions. There is an advantage.

Subsequently, a silicon oxide film formed on the first interlayer insulating film 13 by ECR plasma CVD using electron cyclotron resonance or plasma CVD
Of a moisture permeation preventing film 14 such as a silicon nitride film or the like having a high ability to prevent the permeation of water by a thermal decomposition method or a thermal decomposition CVD method, and thereafter formed sequentially on the upper layer side of the moisture permeation preventing film 14. First-layer wiring metal 15, SOG
Regarding the second-layer interlayer insulating film 16 of a film or a TEOS-CVD film or the like, and the second-layer wiring metal 17,
When the second interlayer insulating film 16 is formed, it is possible to effectively prevent moisture in the film from invading the underlying device.

Here, as a simple configuration for preventing deterioration over time due to hot carriers in this type of MOS transistor, for example, a structure directly above the transistor portion, for example,
After forming a film having a high ability to block moisture permeation such as a silicon nitride film, a CVD / silicon oxide film containing a B or P oxide as a first interlayer insulating film 13 is formed thereon. And forming it at 800 ° C. to 1000
It is thought that annealing should be performed at a temperature of about ℃. However, just forming a moisture permeation prevention film such as a silicon nitride film directly on the transistor portion in this way,
It is not preferable from the viewpoint of suppressing diffusion of mobile ions such as Na that have entered in the device forming process on the lower layer side and protecting the device from contamination by the mobile ions.

Therefore, as in the present embodiment, once the first interlayer insulating film 13 is formed by a CVD / silicon oxide film containing an oxide of B or P, a silicon oxide film or a silicon nitride film is formed. It is effective to form a moisture permeation preventing film 14 having a high ability to block the permeation of moisture as in the above.

FIG. 2 is a sectional view schematically showing a semiconductor integrated circuit device including a MOS transistor to which an interlayer insulating film according to a second embodiment of the present invention is applied.

As described above, in the first embodiment, a CVD / silicon oxide film containing an oxide of B or P is formed as the first interlayer insulating film 13 and then the silicon oxide film is formed. Although a moisture permeation preventing film 14 having a high ability to block the permeation of moisture such as a silicon nitride film or the like is formed, it is not necessarily limited to this configuration. On the side, a first interlayer insulating film 13 made of a CVD / silicon oxide film containing an oxide of B or P may be formed. For example, as shown in FIG. After the formation of the first interlayer insulating film 13a, the first interlayer insulating film 13a
It is also effective to form the moisture permeation preventing film 14 thereon and further form the first interlayer insulating film 13b on the moisture permeation preventing film 14 again. In this case, the 800
Annealing at a temperature of about 1000 ° C. to 1000 ° C. may be performed each time the first-layer interlayer insulating films 13a and 13b are formed on the upper and lower layers, respectively. It is sufficient to perform the process only after the formation of the insulating film 13b.

Therefore, in the configuration of the second embodiment, the first interlayer insulating film 13a on the lower side of the one layer sandwiching the moisture permeation preventing film 14 is formed by the Na invading in the device forming process.
And a role of obtaining a smooth and smooth structure for forming the first-layer metal wiring 15 on the other upper layer side of the first-layer interlayer insulating film 13b. In addition to fulfilling the role of trapping mobile ions such as Na invading from the upper side.

In the structure of the second embodiment, when a silicon nitride film having a very high moisture blocking ability is used as the moisture permeation preventing film 14, the first interlayer insulating film on the upper side thereof is used. The annealing after the formation of the CVD / silicon oxide film containing oxides of B and P as 13b is performed in an atmosphere containing water vapor, so that only an annealing temperature of relatively low 750 ° C. to 900 ° C. is used. High fluidity can be obtained, and a smoothly smoothed film structure can be easily formed. In such an annealing process at a relatively low temperature, doping is performed as a process of forming a miniaturized device. This is advantageous because the diffusion of impurities to other components can be suppressed as much as possible. In this case, if the annealing treatment in the water vapor atmosphere is performed without the interposition of the silicon nitride film as the moisture permeation preventing film 14 in the intermediate portion, the moisture is diffused to the lower device region, and the substrate and the gate polysilicon are diffused. Causing oxidation of the silicon and adversely affecting the device,
As in the second embodiment, the moisture permeation preventing film 1
When an annealing process at a relatively low temperature is made possible by interposing the silicon nitride film as No. 4, the influence on the lower device region is small, and the surface smoothed shape is obtained. There is an advantage that it can be. Here, the thickness of the silicon nitride film as the moisture permeation preventing film 14 is sufficient if it is about 100 Å. Could not be stopped.

[0024]

As described above in detail in each embodiment, according to the present invention, an interlayer insulating film such as a silicon oxide film containing an oxide of boron or phosphorus is formed on the upper layer side of a MOS transistor. A silicon oxide film on this interlayer insulating film by ECR plasma CVD.
A water vapor permeation prevention film with a high ability to block the permeation of water is formed, and as a subsequent interlayer insulating film between metal wirings, a chemical vapor phase centering on coating methods with high water content and thermochemical reactions Even if the insulating films are formed by the growth method, there is no possibility that moisture in these insulating films reaches the lower MOS transistor region and is diffused. There is an excellent feature that the hot carrier deterioration of the element due to the above can be easily avoided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing a semiconductor integrated circuit device including a MOS transistor to which an interlayer insulating film according to a first embodiment of the present invention is applied.

FIG. 2 is a cross-sectional view schematically showing a semiconductor integrated circuit device including a MOS transistor to which an interlayer insulating film according to a second embodiment of the present invention is applied.

FIG. 3 is a cross-sectional view schematically showing a conventional semiconductor integrated circuit device including a MOS transistor to which an interlayer insulating film is applied.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 gate oxide film 12 gate electrode 13, 13a, 13b first layer interlayer insulating film 14 moisture permeation preventing film 15 first layer metal wiring 16 second layer interlayer insulating film 17 second layer metal wiring

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-15678 (JP, A) JP-A-5-13404 (JP, A) JP-A-63-181434 (JP, A) JP-A-5-181434 62967 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/316 H01L 21/318

Claims (2)

(57) [Claims] 1. A semiconductor device having a gate oxide film on a silicon substrate.
A MOS transistor comprising a gate electrode formed on the silicon substrate and the MOS transistor;
Containing either or both of boron and phosphorus
Made of silicon oxide film
Protection film and an ECR plasma CVD method formed on the interlayer insulation film
Ability to block the permeation of water consisting of silicon oxide film
With a moisture permeation preventing layer of high strength, and the moisture permeation preventing layer metal wiring layer formed on the
Semiconductor equipment, characterized in that the. 2. A method according to claim 1 , wherein a gate oxide film is formed on the silicon substrate.
A MOS transistor comprising a gate electrode formed on the silicon substrate and the MOS transistor;
Containing either or both of boron and phosphorus
Made of silicon oxide film
First interlayer insulating film for protecting and an ECR plasma CVD method formed on the interlayer insulating film
Ability to block the permeation of water consisting of silicon oxide film
Water permeation prevention film with high power and boron and phosphorus formed on this water permeation prevention film
A silicon oxide film containing one or both
Semiconductor equipment, characterized by comprising a second interlayer insulating film.