JP2937886B2 - Method for forming interlayer insulating film of semiconductor device - Google Patents
Method for forming interlayer insulating film of semiconductor deviceInfo
- Publication number
- JP2937886B2 JP2937886B2 JP8244968A JP24496896A JP2937886B2 JP 2937886 B2 JP2937886 B2 JP 2937886B2 JP 8244968 A JP8244968 A JP 8244968A JP 24496896 A JP24496896 A JP 24496896A JP 2937886 B2 JP2937886 B2 JP 2937886B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- silicon
- oxide film
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子の製造方法に
関し、特に半導体素子の層間絶縁膜形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an interlayer insulating film of a semiconductor device.
【０００２】[0002]
【従来の技術】多層の金属配線構造を有するＣＭＯＳ素
子の平坦化方法において、ＳＯＧ（Spin On Glass)を層
間絶縁膜に用い、最終層の金属配線を形成した後、その
上にＳｉＮx 保護膜を蒸着することが従来から一般的で
あった。2. Description of the Related Art In a method of planarizing a CMOS device having a multi-layered metal wiring structure, SOG (Spin On Glass) is used as an interlayer insulating film, a metal wiring of a final layer is formed, and a SiNx protective film is formed thereon. Deposition has conventionally been common.
【０００３】この際、後続熱工程によりＳＯＧ膜とＳｉ
Ｎx 膜に含まれたＨ、ＯＨ、Ｈ2 Ｏ等が半導体素子の内
部に浸透することにより、寄生ＭＯＳＦＥＴのドレイン
とソース間の絶縁性が低下したり破壊されるフィールド
極性反転（field inversion)現象が発生する。At this time, the SOG film and the Si
A field inversion phenomenon in which H, OH, H 2 O, etc. contained in the Nx film penetrates into the inside of the semiconductor device, thereby deteriorating or destroying insulation between the drain and source of the parasitic MOSFET. Occurs.
【０００４】そのため、ドレインとソース間の臨界電圧
が低下し、漏洩電流が増加して素子の動作特性が不安定
となる問題が生じる。As a result, there arises a problem that the critical voltage between the drain and the source decreases, the leakage current increases, and the operation characteristics of the device become unstable.
【０００５】このような観点から、従来技術による２層
金属配線構造のＣＭＯＳ素子の形成方法を図１を参照し
て説明すれば次の通りである。From this viewpoint, a method of forming a CMOS device having a two-layer metal wiring structure according to the prior art will be described with reference to FIG.
【０００６】図１は、従来技術による半導体素子の層間
絶縁膜が適用された２層配線構造の半導体素子断面図で
ある。FIG. 1 is a sectional view of a semiconductor device having a two-layer wiring structure to which an interlayer insulating film of a conventional semiconductor device is applied.
【０００７】図１に示すように、半導体基板１にＰ型ウ
ェル３を形成し、Ｐ型ウェル３の表面に活性領域とフィ
ルード領域を定義するフィールド酸化膜５を形成する。As shown in FIG. 1, a P-type well 3 is formed in a semiconductor substrate 1, and a field oxide film 5 defining an active region and a field region is formed on the surface of the P-type well 3.
【０００８】次いで、Ｐ型ウェル３の活性領域上にゲー
ト酸化膜７と、このゲート酸化膜７上にゲート電極９を
順次形成する。Next, a gate oxide film 7 is formed on the active region of the P-type well 3 and a gate electrode 9 is formed on the gate oxide film 7 in this order.
【０００９】その次に、ゲート電極９両側の半導体基板
１に不純物をイオン注入してソース／ドレイン領域１３
を形成する。Then, impurities are ion-implanted into the semiconductor substrate 1 on both sides of the gate electrode 9 to form source / drain regions 13.
To form
【００１０】このようにして、二つの正常的なＭＯＳＦ
ＥＴ（９ａ，１３ａ，１３ｂ），（９ｃ，１３ａ，１３
ｂ）と寄生ＭＯＳＦＥＴ（９ｂ，１３ａ，１３ｂ）を形
成する。In this manner, two normal MOSFs
ET (9a, 13a, 13b), (9c, 13a, 13
b) and a parasitic MOSFET (9b, 13a, 13b).
【００１１】次いで、全体構造上部にＢＰＳＧ膜１５を
蒸着して平坦化させ、ＢＰＳＧ膜１５の所定部分に第１
層金属配線１７を形成する。Next, a BPSG film 15 is deposited on the entire structure and flattened, and a first portion is formed on a predetermined portion of the BPSG film 15.
The layer metal wiring 17 is formed.
【００１２】その次に、全体構造の上部にＰＥＣＶＤ方
法で第１層間絶縁膜１９を形成し、この第１層間絶縁膜
１９上にＳＯＧ膜から成る平坦化用第２層間絶縁膜２１
を形成し、さらに、この第２層間絶縁膜２１上にＰＥＣ
ＶＤ方法で第３層間絶縁膜２３を順次積層する。Then, a first interlayer insulating film 19 is formed on the entire structure by the PECVD method, and a second planarizing interlayer insulating film 21 made of an SOG film is formed on the first interlayer insulating film 19.
Is formed, and a PEC is formed on the second interlayer insulating film 21.
The third interlayer insulating film 23 is sequentially stacked by the VD method.
【００１３】次いで、第３層間絶縁膜２３の上部に第２
層金属配線２５を形成し、第２層金属配線２５上にＳｉ
Ｎx を蒸着して表面保護膜２７を形成しなければならな
い。Next, a second layer is formed on the third interlayer insulating film 23.
A layer metal wiring 25 is formed, and Si is formed on the second layer metal wiring 25.
The surface protection film 27 must be formed by depositing Nx.
【００１４】[0014]
【発明が解決しようとする課題】しかし、従来半導体素
子の層間絶縁膜形成方法においてはＳｉＮx でなる表面
保護膜を蒸着後の熱処理工程の際に、ｎ−チャンネル寄
生ＭＯＳＦＥＴのドレインとソース間にフィールド極性
反転現象が発生する問題点がある。However, in a conventional method for forming an interlayer insulating film of a semiconductor device, a field protection film is formed between a drain and a source of an n-channel parasitic MOSFET during a heat treatment step after deposition of a surface protection film made of SiNx. There is a problem that the polarity inversion phenomenon occurs.
【００１５】このようなフィールド極性反転現象は、保
護膜内部に含有された水素が下側に拡散されながらＳＯ
Ｇ膜内部のＯＨ、ＣＨ3 、Ｈ2 Ｏ等と相互作用を起こし
て反応物を形成し、この反応物は層間絶縁膜を通過して
素子内部に浸透することにより発生する。Such a field polarity reversal phenomenon is caused by the fact that hydrogen contained in the protective film is diffused downward while SO
It interacts with OH, CH 3 , H 2 O, etc. in the G film to form a reactant, and this reactant is generated by permeating the inside of the device through the interlayer insulating film.
【００１６】なお、フィールド極性反転現象はＳＯＧ膜
内部のＯＨ、Ｈ2 Ｏも層間絶縁膜を介して半導体素子内
部に浸透しドナー（donor)型不純物に作用したり、フィ
ールド酸化膜にポジティブ電荷（positive charge)を誘
発するため生じる。In the field polarity reversal phenomenon, OH and H 2 O inside the SOG film also penetrate into the semiconductor device through the interlayer insulating film and act on donor-type impurities, or the field oxide film has a positive charge ( Positive charge).
【００１７】即ち、フィールド極性反転現象は下部層間
絶縁膜が工程中に生じる不純物が素子内部に浸透するこ
とを遮断できないため生じる。That is, the field polarity inversion phenomenon occurs because the lower interlayer insulating film cannot prevent impurities generated during the process from penetrating into the device.
【００１８】そのため、ｎ−チャンネル寄生ＭＯＳＦＥ
Ｔのドレインとソース間の臨界電圧が落ち、漏洩電流が
増加することにより半導体素子の動作特性が不安定とな
り動作不良を誘発する。Therefore, the n-channel parasitic MOSFE
As the critical voltage between the drain and the source of T drops and the leakage current increases, the operating characteristics of the semiconductor device become unstable, leading to operation failure.
【００１９】ここに、本発明は寄生ＭＯＳＦＥＴのドレ
インとソース間のフィールド極性反転現象を防止するこ
とができる、半導体素子の層間絶縁膜形成方法を提供す
ることにその目的がある。It is an object of the present invention to provide a method of forming an interlayer insulating film of a semiconductor device, which can prevent a field polarity reversal between a drain and a source of a parasitic MOSFET.
【００２０】さらに、本発明の他の目的は層間絶縁膜の
特性を改良し半導体素子の信頼性を向上させ得るように
した。半導体素子の層間絶縁膜形成方法を提供すること
にある。Still another object of the present invention is to improve characteristics of an interlayer insulating film and improve reliability of a semiconductor device. An object of the present invention is to provide a method for forming an interlayer insulating film of a semiconductor device.
【００２１】なお、本発明のさらに他の目的は、高集積
半導体素子の適用に適した層間絶縁膜を形成することが
できる半導体素子の層間絶縁膜形成方法を提供すること
にある。It is a still further object of the present invention to provide a method for forming an interlayer insulating film of a semiconductor device which can form an interlayer insulating film suitable for application of a highly integrated semiconductor device.
【００２２】[0022]
【００２３】[0023]
【課題を解決するための手段】このような目的を達成す
るために本発明による半導体素子の層間絶縁膜形成方法
は上面に下層金属配線が形成された半導体基板を提供す
る段階と、基板全体構造の露出した表面上にシリコン−
リッチ酸化膜とシリコン−リッチ酸化膜上にシリコン窒
化酸化膜を順次形成する段階と、シリコン窒化膜上にＳ
ＯＧ膜を形成する段階と、ＳＯＧ膜上に酸化膜を形成す
る段階を含み構成されたことを特徴とする。In order to achieve the above object, a method for forming an interlayer insulating film of a semiconductor device according to the present invention comprises the steps of providing a semiconductor substrate having a lower metal wiring formed on an upper surface thereof, and an entire structure of the substrate. Silicon on the exposed surface of
Forming a silicon oxynitride film sequentially on the rich oxide film and the silicon-rich oxide film;
The method is characterized by including a step of forming an OG film and a step of forming an oxide film on the SOG film.
【００２４】[0024]
【発明の実施の形態】以下、本発明の一実施形態を添付
の図面を参照して詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the accompanying drawings.
【００２５】図２は、本発明による半導体素子の層間絶
縁膜形成方法が適用された２層金属配線構造の半導体素
子断面図である。FIG. 2 is a sectional view of a semiconductor device having a two-layer metal wiring structure to which the method of forming an interlayer insulating film of a semiconductor device according to the present invention is applied.
【００２６】図２に示すように、半導体基板１０１上に
Ｐ型ウェル１０３を形成し、Ｐ型ウェル１０３の表面に
活性領域とフィールド領域を定義するフィールド酸化膜
１０５を形成する。As shown in FIG. 2, a P-type well 103 is formed on a semiconductor substrate 101, and a field oxide film 105 defining an active region and a field region is formed on the surface of the P-type well 103.
【００２７】次いでＰ型ウェル１０３の活性領域上にゲ
ート酸化膜１０７と、ゲート酸化膜１０７上にゲート電
極１０９ａ，１０９ｂ，１０９ｃを順次形成する。Next, a gate oxide film 107 is formed on the active region of the P-type well 103, and gate electrodes 109a, 109b, and 109c are sequentially formed on the gate oxide film 107.
【００２８】この際、Ｐ型ウェル１０３は半導体基板１
０１の導電性タイプに従いＮ型ウェルを用いることもで
きる。At this time, the P-type well 103 is in the semiconductor substrate 1
An N-type well can also be used according to a conductivity type of 01.
【００２９】その次に、ゲート電極１０９ａ，１０９
ｂ，１０９ｃの側面に側壁スペーサ１１１を形成する。Next, the gate electrodes 109a, 109
Side wall spacers 111 are formed on the side surfaces of b and 109c.
【００３０】次いで、ゲート電極１０９ａ，１０９ｂ，
１０９ｃと側壁スペーサ（spacer)をマスクにし、ゲー
ト電極１０９ａ，１０９ｂ，１０９ｃ両側の半導体基板
１０１に、Ｐ型ウェル１０３と反対導電性タイプを有す
る不純物をイオン注入してソース領域１１３ａとドレイ
ン領域１１３ｂを形成する。Next, the gate electrodes 109a, 109b,
The source region 113a and the drain region 113b are ion-implanted into the semiconductor substrate 101 on both sides of the gate electrodes 109a, 109b, and 109c using the mask 109c and the sidewall spacers as a mask. Form.
【００３１】こうして、二つの正常的なＭＯＳＦＥＴ
（１０９ａ，１１３ａ，１１３ｂ），（１０９ｃ，１１
３ａ，１１３ｃ）と寄生ＭＯＳＦＥＴ（１０９ｂ，１１
３ａ，１１３ｂ）を完成する。Thus, two normal MOSFETs
(109a, 113a, 113b), (109c, 11
3a, 113c) and the parasitic MOSFET (109b, 11c).
3a, 113b) are completed.
【００３２】その次に、全体構造の上部にＢＰＳＧ膜１
１５を形成して表面を平坦化させた後、ＢＰＳＧ膜１１
５の所定部分上に第１層金属配線１１７を形成する。Next, a BPSG film 1 is formed on the entire structure.
15 is formed and the surface is planarized, and then the BPSG film 11 is formed.
The first layer metal wiring 117 is formed on the predetermined portion of No. 5.
【００３３】次いで、全体構造、即ち、ＢＰＳＧ膜１１
５と第１層金属配線１１７の露出した表面、上部にＰＥ
ＣＶＤ（Plasma Enhanced Chemical Vapor Deposition)
方法を用いて第１酸化膜１１９とシリコン−リッチ（Si
-rich)酸化膜１２１を順次積層する。Next, the entire structure, that is, the BPSG film 11
5 and the exposed surface of the first layer metal wiring 117,
CVD (Plasma Enhanced Chemical Vapor Deposition)
The first oxide film 119 and the silicon-rich (Si)
-rich) The oxide films 121 are sequentially stacked.
【００３４】この際、シリコン−リッチ酸化膜１２１は
約５００〜３０００オングストローム厚さに蒸着する。
この第１酸化膜１１９とシリコン−リッチ（Si-rich)酸
化膜１２１は下部層間絶縁膜に用いる。At this time, the silicon-rich oxide film 121 is deposited to a thickness of about 500-3000 Å.
The first oxide film 119 and the silicon-rich (Si-rich) oxide film 121 are used as a lower interlayer insulating film.
【００３５】一方、半導体素子の集積度が増加すること
により第１金属配線の間の間隔が例えば、現在２５６Ｍ
ＤＲＡＭ級素子の場合に第１層金属配線の間隔が約０．
４μｍ以下程度に減少することを鑑みる時、本発明の他
の実施形態として、第１酸化膜とシリコン−リッチ酸化
膜を形成する代りに、シリコン−リッチ酸化膜のみ形成
して下部層間絶縁膜に用いることもできる。On the other hand, as the integration degree of the semiconductor device increases, the distance between the first metal wirings is, for example, 256M.
In the case of a DRAM-class element, the distance between the first-layer metal wirings is about 0.
In view of the reduction to about 4 μm or less, as another embodiment of the present invention, instead of forming the first oxide film and the silicon-rich oxide film, only the silicon-rich oxide film is formed and the lower interlayer insulating film is formed. It can also be used.
【００３６】なぜならば、第１酸化膜とシリコン−リッ
チ酸化膜を積層する場合に、金属配線の間の間隔が非常
に狭くなりＳＯＧ膜の塗布が難しいためである。This is because, when the first oxide film and the silicon-rich oxide film are stacked, the distance between the metal wirings becomes very narrow, and it is difficult to apply the SOG film.
【００３７】また、シリコン−リッチ酸化膜１２１の蒸
着は通常のＰＥＣＶＤ法によるシリコン酸化膜蒸着の際
にＳｉソースであるＳｉＨ4 の流入量を増加させ、Ｏの
ソーースであるＮ2 Ｏ量を減少させ蒸着する。The deposition of the silicon-rich oxide film 121 increases the inflow of SiH 4 as a Si source and decreases the amount of N 2 O as a source of O when depositing a silicon oxide film by a normal PECVD method. And vapor deposition.
【００３８】この際、Ｎ2 Ｏに対するＳｉＨ4 の入力比
が増加するに伴い膜の屈折率が約１．５５以上に増加す
る。At this time, as the input ratio of SiH 4 to N 2 O increases, the refractive index of the film increases to about 1.55 or more.
【００３９】なお、膜の応力状態はＲＦ（Radio Freque
ncy)パワー（power)を調節して−０．５乃至−１．５dy
ne/cm2の圧縮応力状態に調節する。The stress state of the film is RF (Radio Frequent).
ncy) Adjust power (-0.5 to -1.5dy)
Adjust to a compressive stress state of ne / cm 2 .
【００４０】そして、シリコン窒化酸化膜１２１は通常
のＰＥＣＶＤ法により蒸着し、ＳｉＨ4 ／Ｎ2 Ｏ／ＮＨ
3 ／Ｎ2 の反応気体を用いて蒸着することもできる。Then, the silicon oxynitride film 121 is deposited by a normal PECVD method, and is made of SiH 4 / N 2 O / NH.
Vapor deposition can also be performed using a 3 / N 2 reaction gas.
【００４１】即ち、シリコン−リッチ酸化膜１２１の蒸
着条件でＳｉＨ4 流量は約３００〜６００sccm、Ｎ2 Ｏ
流量は４０００〜７０００sccm、Ｎ2 流量は約３００〜
６０００sccmに調節する。[0041] That is, the silicon - SiH 4 flow rate in the deposition condition of the rich oxide film 121 is about 300~600sccm, N 2 O
The flow rate 4000~7000sccm, N 2 flow rate of about 300
Adjust to 6000 sccm.
【００４２】また、約２〜３torrの蒸着圧力と、１３．
５６ＭＨｚのＲＦ（Radio Frequency)の約０．３〜０．
７ｋＷの電力と、ＬＦ（Low Frequency)の約０．４〜
０．８ｋＷの電力を用いる。Also, a deposition pressure of about 2-3 torr, and 13.
RF (Radio Frequency) of about 56 to about 0.3 to 0.3.
7kW power and LF (Low Frequency) 0.4 ~
A power of 0.8 kW is used.
【００４３】また、膜の応力状態はＲＦパワーを適切に
調節して−０．５乃至−１．５dyne/cm2にする。The stress state of the film is adjusted to -0.5 to -1.5 dyne / cm 2 by appropriately adjusting the RF power.
【００４４】この際、ＮＨ3 ／Ｎ2 Ｏ／Ｎ2 の流入比が
増加することにより膜の屈折率が約１．６８以上に増加
する。At this time, as the inflow ratio of NH 3 / N 2 O / N 2 increases, the refractive index of the film increases to about 1.68 or more.
【００４５】さらに、シリコン−リッチ酸化膜１２１の
代りにシリコン窒化酸化膜を用いても同様の効果を得る
ことができる。Further, the same effect can be obtained by using a silicon nitride oxide film instead of the silicon-rich oxide film 121.
【００４６】シリコン窒化酸化膜を用いる場合に、シリ
コン窒化酸化膜１２１は約５００〜３０００オングスト
ローム厚さに蒸着する。When a silicon oxynitride film is used, the silicon oxynitride film 121 is deposited to a thickness of about 500 to 3000 angstroms.
【００４７】この際、シリコン窒化酸化膜の蒸着条件と
して、ＳｉＨ4 流量は約２００〜３５０sccm、Ｎ2 Ｏ流
量は１０００〜４０００sccm、ＮＨ3 流量は約１０００
〜４０００sccm、Ｎ2 流量は約３０００〜６０００sccm
に調節する。At this time, the deposition conditions of the silicon oxynitride film are as follows: SiH 4 flow rate is about 200-350 sccm, N 2 O flow rate is 1000-4000 sccm, NH 3 flow rate is about 1000 sccm.
~4000sccm, N 2 flow rate of about 3000~6000sccm
Adjust to.
【００４８】この際、ＮＨ3 に対するＳｉＨ4 の流量比
を適切に調節して膜の屈折率が約１．５５〜１．８５程
度に調節することが好ましい。At this time, it is preferable to appropriately adjust the flow ratio of SiH 4 to NH 3 to adjust the refractive index of the film to about 1.55 to 1.85.
【００４９】なお、膜の応力状態はＲＦ（Radio Freque
ncy)とパワー（power)を調節して−０．５乃至−１．５
dyne/cm2の圧縮応力に調節する。The stress state of the film is RF (Radio Frequent).
ncy) and power (-0.5 to -1.5
Adjust to a compressive stress of dyne / cm 2 .
【００５０】そして、約２〜３torrの蒸着圧力と、１
３．５６ＭＨｚのＲＦ（Radio Frequency)の約０．４〜
０．６ｋＷの電力と、２８０ｋＨｚのＬＦ（Low Freque
ncy)の約０．４〜０．７ｋＷの電力を用いる。Then, a deposition pressure of about 2-3 torr and 1
Approximately 0.4 to 3.56 MHz RF (Radio Frequency)
0.6kW power and 280kHz LF (Low Frequency
ncy) of about 0.4 to 0.7 kW.
【００５１】さらに、膜の応力状態はＲＦパワーを適切
に調節して−０．５乃至−１．５dyne/cm2となるように
する。Further, the stress state of the film is adjusted so as to be -0.5 to -1.5 dyne / cm 2 by appropriately adjusting the RF power.
【００５２】一方、障壁層（barrier)を用いるための一
例として、シリコン−リッチ酸化膜１２１とシリコン−
リッチ酸化膜１２１上にシリコン窒化酸化膜（未図示）
を積層して障壁層に用いることができる。On the other hand, as an example for using a barrier layer, a silicon-rich oxide film 121 and a silicon-rich oxide film 121 are used.
A silicon oxynitride film (not shown) on the rich oxide film 121
Can be used as a barrier layer.
【００５３】この際、各層の蒸着は障壁層でシリコン−
リッチ酸化膜１２１とシリコン窒化酸化膜を選択的に用
いる時の蒸着条件と同様の条件下で行う。At this time, the deposition of each layer is performed by using a silicon layer in the barrier layer.
The deposition is performed under the same conditions as the deposition conditions when the rich oxide film 121 and the silicon oxynitride film are selectively used.
【００５４】その次に、シリコン−リッチ酸化膜１２１
の上部にＳＯＧ膜１２３を形成して硬化させる。Next, a silicon-rich oxide film 121 is formed.
An SOG film 123 is formed on top of the substrate and cured.
【００５５】この際、ＳＯＧ膜１２３は平坦化用層間絶
縁膜に用いる。At this time, the SOG film 123 is used as an interlayer insulating film for planarization.
【００５６】次いで、ＳＯＧ膜１２３の上部にＰＥＣＶ
Ｄ方法を用いて第２酸化膜１２５を蒸着する。この第２
酸化膜１２５は上部層間絶縁膜に用いる。Next, a PECV is formed on the SOG film 123.
The second oxide film 125 is deposited using the D method. This second
The oxide film 125 is used as an upper interlayer insulating film.
【００５７】その次に、第２酸化膜１２５の上部に第２
層金属配線１２７を形成する。Next, a second oxide film 125
The layer metal wiring 127 is formed.
【００５８】次いで、第２層金属配線１２７の上部にＳ
ｉＮx を蒸着して表面保護膜１２９を形成した後、これ
を熱処理する。Next, an S layer is formed on the upper part of the second-layer metal wiring 127.
After a surface protection film 129 is formed by depositing iNx, this is heat-treated.
【００５９】この際、シリコン窒化膜は約５００〜１５
００オングストローム厚さに蒸着する。At this time, the silicon nitride film has a thickness of about 500 to 15
Deposit to a thickness of 00 Å.
【００６０】なお、シリコン窒化膜の蒸着条件として、
ＳｉＨ4 流量は約４５０〜５５０sccm、ＮＨ3 流量は３
０００〜６０００sccm、Ｎ2 流量は約２０００〜３００
０sccmに調節する。The conditions for depositing the silicon nitride film are as follows:
The SiH 4 flow rate is about 450-550 sccm, and the NH 3 flow rate is 3
000~6000sccm, N 2 flow rate of about 2,000 to 300
Adjust to 0 sccm.
【００６１】この際、ＮＨ3 に対するＳｉＨ4 の流量比
を適切に調節して膜の屈折率が約１．９５〜２．１程度
に調節することが好ましい。At this time, it is preferable to appropriately adjust the flow ratio of SiH 4 to NH 3 to adjust the refractive index of the film to about 1.95 to 2.1.
【００６２】そして、約２〜３torrの蒸着圧力と、１
３．５６ＭＨｚのＲＦ（Radio Frequency)の約０．４〜
０．６ｋＷの電力と，２８０ｋＨｚのＬＦ（Low Freque
ncy)の約０．４〜０．７ｋＷの電力を用いる。Then, a deposition pressure of about 2-3 torr and 1
Approximately 0.4 to 3.56 MHz RF (Radio Frequency)
0.6kW power and 280kHz LF (Low Frequency
ncy) of about 0.4 to 0.7 kW.
【００６３】また、膜の応力状態はＲＦ（Radio Freque
ncy)パワー（power)を調節して−０．５乃至−１．５dy
ne/cm2の圧縮応力状態に調節する。The stress state of the film is RF (Radio Frequent
ncy) Adjust power (-0.5 to -1.5dy)
Adjust to a compressive stress state of ne / cm 2 .
【００６４】一方、図３は絶縁膜の屈折率とソース（ｎ
+ ）とドレイン（ｎ+ ）間の絶縁破壊臨界電圧との関係
を示したグラフである。FIG. 3 shows the refractive index of the insulating film and the source (n
4 is a graph showing the relationship between the breakdown voltage between the drain (n + ) and the drain (n + ).
【００６５】図３に示すように、屈折率が高くなること
によりソースとドレイン絶縁破壊臨界電圧（critical v
oltage) が増加することが分かる。As shown in FIG. 3, as the refractive index increases, the critical voltage between the source and drain breakdown (critical v) increases.
oltage) increases.
【００６６】従来技術においては第１酸化膜の屈折率が
約１．４７程度であるが、本発明においてはシリコン−
リッチ酸化膜の屈折率が１．５５乃至１．６５に測定さ
れ、シリコン−リッチ酸化膜の応力が−０．５乃至−
１．５dyne/cm2に測定される。In the prior art, the refractive index of the first oxide film is about 1.47.
The refractive index of the rich oxide film was measured between 1.55 and 1.65, and the stress of the silicon-rich oxide film was between -0.5 and-.
Measured to 1.5 dyne / cm 2 .
【００６７】なお、シリコン窒化酸化膜の場合に屈折率
が１．６８乃至１．８に測定され、応力は−０．５乃至
−１．５dyne/cm2に測定される。In the case of a silicon oxynitride film, the refractive index is measured between 1.68 and 1.8, and the stress is measured between -0.5 and -1.5 dyne / cm 2 .
【００６８】さらに、図４は絶縁膜の屈折率とＭＯＳＦ
ＥＴのホットキャリア動作寿命との関係を示すグラフで
ある。FIG. 4 shows the refractive index of the insulating film and the MOSF.
4 is a graph showing a relationship between ET and a hot carrier operation life.
【００６９】図４に示すように、屈折率が高い場合にホ
ットキャリア（hot carrier)動作寿命が増加することが
分かる。As shown in FIG. 4, when the refractive index is high, the operating life of the hot carrier increases.
【００７０】[0070]
【発明の効果】前記で説明したように、本発明による半
導体素子の絶縁膜形成方法においては次のような効果が
ある。As described above, the method for forming an insulating film of a semiconductor device according to the present invention has the following effects.
【００７１】本発明による半導体素子の絶縁膜形成方法
においてはシリコン−リッチ酸化膜、又はシリコン窒化
酸化膜を下部層間絶縁膜に用いることにより、寄生ＭＯ
ＳＦＥＴのドレインとソース間のフィールド極性反転現
象を防止することができる。In the method for forming an insulating film of a semiconductor device according to the present invention, a silicon-rich oxide film or a silicon oxynitride film is used as a lower interlayer insulating film, so that a parasitic MO can be formed.
Field polarity reversal between the drain and source of the SFET can be prevented.
【００７２】なお、本発明による半導体素子の絶縁膜形
成方法においては、ホットキャリアの信頼性が確保され
るので半導体素子の動作特性を向上させることができ
る。In the method for forming an insulating film of a semiconductor device according to the present invention, the operating characteristics of the semiconductor device can be improved because the reliability of hot carriers is ensured.
【００７３】さらに、本発明による半導体素子の絶縁膜
形成方法においては層間絶縁膜の障壁（barrier)特性が
改良されるため高集積半導体素子への使用が適切であ
る。Further, in the method for forming an insulating film of a semiconductor device according to the present invention, the barrier characteristic of the interlayer insulating film is improved, so that it is suitable for use in a highly integrated semiconductor device.
【図１】従来技術による半導体素子の層間絶縁膜形成方
法が適用された２層金属配線構造の半導体素子断面図。FIG. 1 is a cross-sectional view of a semiconductor device having a two-layer metal wiring structure to which a method for forming an interlayer insulating film of a semiconductor device according to a conventional technique is applied.
【図２】本発明による半導体素子の層間絶縁膜形成方法
が適用された２層金属配線構造の半導体素子断面図。FIG. 2 is a cross-sectional view of a semiconductor device having a two-layer metal wiring structure to which a method for forming an interlayer insulating film of a semiconductor device according to the present invention is applied.
【図３】本発明による絶縁膜の屈折率と絶縁破壊臨界電
圧との関係を示すグラフ。FIG. 3 is a graph showing the relationship between the refractive index of an insulating film according to the present invention and the critical voltage for dielectric breakdown.
【図４】本発明による絶縁膜の屈折率とホットキャリア
の動作寿命との関係を示すグラフ。FIG. 4 is a graph showing the relationship between the refractive index of an insulating film according to the present invention and the operating lifetime of hot carriers.
１０１…半導体基板 １０３…Ｐ型ウェル １０５…フィールド酸化膜 １０７…ゲート酸化膜 １０９ａ，１０９ｂ，１０９ｃ…ゲート電極 １１１…側壁スペーサ １１３ａ…ソース領域 １１３ｂ…ドレイン領域 １１５…ＢＰＳＧ膜 １１７…第１層金属配線 １１９…第１酸化膜 １２１…ＳＯＧ膜 １２３…第２酸化膜 １２５…シリコン−リッチ酸化膜 １２７…第２層金属配線 １２９…保護膜 DESCRIPTION OF SYMBOLS 101 ... Semiconductor substrate 103 ... P-type well 105 ... Field oxide film 107 ... Gate oxide film 109a, 109b, 109c ... Gate electrode 111 ... Side wall spacer 113a ... Source region 113b ... Drain region 115 ... BPSG film 117 ... 1st layer metal wiring 119: first oxide film 121: SOG film 123: second oxide film 125: silicon-rich oxide film 127: second-layer metal wiring 129: protective film
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/31 H01L 21/316 H01L 21/768 ──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. 6 , DB name) H01L 21/31 H01L 21/316 H01L 21/768
Claims (8)
基板を提供する段階と、 前記基板全体構造の露出した表面上にシリコン−リッチ
酸化膜及び、前記シリコン−リッチ酸化膜上にシリコン
窒化酸化膜を順次形成する段階と、 前記シリコン窒化膜上にＳＯＧ膜を形成する段階と、 前記ＳＯＧ膜上に酸化膜を形成する段階と、 を含み構成されることを特徴とする半導体素子の層間絶
縁膜形成方法。Providing a semiconductor substrate having a lower metal wiring formed on an upper surface thereof, a silicon-rich oxide film on an exposed surface of the entire substrate structure, and a silicon nitride oxide film on the silicon-rich oxide film. Forming a film sequentially; forming an SOG film on the silicon nitride film; and forming an oxide film on the SOG film. Film formation method.
／Ｎ2 Ｏ／Ｎ2 反応気体中、ＳｉＨ4 流量は３００〜６
００sccm、Ｎ2 Ｏ流量は４０００〜７０００sccm、Ｎ2
流量は３０００〜６０００sccmを用い、ＰＥＣＶＤ方法
で蒸着することを特徴とする請求項１記載の半導体素子
の層間絶縁膜形成方法。2. The method according to claim 1, wherein the silicon-rich oxide film is SiH 4.
/ N 2 O / N 2 reaction gas, SiH 4 flow rate is 300-6
00sccm, N 2 O flow rate 4000~7000sccm, N 2
2. The method according to claim 1, wherein the flow rate is 3000 to 6000 sccm and the deposition is performed by PECVD.
５〜１．６５の屈折率と−０．５〜−１．５dyne／cm2
の圧縮応力状態を有することを特徴とする請求項１記載
の半導体素子の層間絶縁膜形成方法。3. The silicon-rich oxide film has a thickness of 1.5
Refractive index of from 5 to 1.65 and -0.5~-1.5dyne / cm 2
2. The method for forming an interlayer insulating film of a semiconductor device according to claim 1, wherein said method has a compressive stress state of:
Ｈ3 ／Ｎ2 Ｏ／Ｎ2反応気体中、ＳｉＨ4 流量は２００
〜３５０sccm、Ｎ2 Ｏ流量は１０００〜４０００sccm、
ＮＨ3 流量は１０００〜４０００sccm、Ｎ2 流量は５０
００〜８０００sccmを用い、ＰＥＣＶＤ方法で蒸着する
ことを特徴とする請求項１記載の半導体素子の層間絶縁
膜形成方法。4. The method according to claim 1, wherein the silicon oxynitride film is SiH 4 / N
In the H 3 / N 2 O / N 2 reaction gas, the SiH 4 flow rate is 200
~350sccm, N 2 O flow rate 1000～4000Sccm,
The NH 3 flow rate is 1000-4000 sccm, and the N 2 flow rate is 50
2. The method according to claim 1, wherein the film is deposited by PECVD using a thickness of 100 to 8000 sccm.
１．８５の屈折率と−０．５〜−１．５dyne／cm2 の圧
縮応力状態を有することを特徴とする請求項１記載の半
導体素子の層間絶縁膜形成方法。5. The silicon oxynitride film according to claim 1, wherein
2. The method according to claim 1, wherein the method has a refractive index of 1.85 and a compressive stress state of -0.5 to -1.5 dyne / cm < 2 >.
形成する段階と、前記上部金属配線を含む全体構造の露
出した上面に保護膜を形成する段階をさらに含むことを
特徴とする請求項１記載の半導体素子の層間絶縁膜形成
方法。6. The method of claim 1, further comprising: forming an upper metal line on the silicon oxide film; and forming a protective layer on an exposed upper surface of the entire structure including the upper metal line. The method for forming an interlayer insulating film of a semiconductor device according to the above.
半導体基板上に多数個のＭＯＳ素子及び絶縁膜を形成す
る段階をさらに含むことを特徴とする請求項１記載の半
導体素子の層間絶縁膜形成方法。7. The method of claim 1, further comprising forming a plurality of MOS devices and insulating films on the semiconductor substrate before forming the lower metal wiring. Film formation method.
と、−０．５〜−１．５dyne／cm2 の圧縮応力状態を有
することを特徴とする請求項１記載の半導体素子の層間
絶縁膜形成方法。8. The semiconductor according to claim 1, wherein said protective film has a refractive index of 1.95 to 2.1 and a compressive stress state of -0.5 to -1.5 dyne / cm 2. A method for forming an interlayer insulating film of a device.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950030005A KR100197980B1 (en) | 1995-09-14 | 1995-09-14 | Method of manufacturing a semiconductor device |
| KR95-30005 | 1995-09-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09129625A JPH09129625A (en) | 1997-05-16 |
| JP2937886B2 true JP2937886B2 (en) | 1999-08-23 |
Family
ID=19426789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8244968A Expired - Fee Related JP2937886B2 (en) | 1995-09-14 | 1996-09-17 | Method for forming interlayer insulating film of semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2937886B2 (en) |
| KR (1) | KR100197980B1 (en) |
| DE (1) | DE19637458A1 (en) |
| GB (1) | GB2305295B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156952A (en) * | 2004-10-28 | 2006-06-15 | Renesas Technology Corp | Semiconductor device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002313968A (en) * | 2001-02-08 | 2002-10-25 | Seiko Epson Corp | Semiconductor device and its manufacturing method |
| CN111725180A (en) * | 2020-07-23 | 2020-09-29 | 华虹半导体(无锡)有限公司 | Interlayer dielectric layer structure for power MOS device and manufacturing method thereof |
| CN112635329A (en) * | 2020-12-14 | 2021-04-09 | 华虹半导体(无锡)有限公司 | Interlayer dielectric layer of DMOS device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4676867A (en) * | 1986-06-06 | 1987-06-30 | Rockwell International Corporation | Planarization process for double metal MOS using spin-on glass as a sacrificial layer |
| US5003062A (en) * | 1990-04-19 | 1991-03-26 | Taiwan Semiconductor Manufacturing Co. | Semiconductor planarization process for submicron devices |
-
1995
- 1995-09-14 KR KR1019950030005A patent/KR100197980B1/en not_active IP Right Cessation
-
1996
- 1996-09-12 GB GB9619116A patent/GB2305295B/en not_active Expired - Fee Related
- 1996-09-13 DE DE19637458A patent/DE19637458A1/en not_active Ceased
- 1996-09-17 JP JP8244968A patent/JP2937886B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156952A (en) * | 2004-10-28 | 2006-06-15 | Renesas Technology Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| DE19637458A1 (en) | 1997-03-20 |
| GB2305295A (en) | 1997-04-02 |
| JPH09129625A (en) | 1997-05-16 |
| GB9619116D0 (en) | 1996-10-23 |
| GB2305295B (en) | 2000-05-10 |
| KR970018399A (en) | 1997-04-30 |
| KR100197980B1 (en) | 1999-06-15 |
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