KR970018399A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR970018399A
KR970018399A KR1019950030005A KR19950030005A KR970018399A KR 970018399 A KR970018399 A KR 970018399A KR 1019950030005 A KR1019950030005 A KR 1019950030005A KR 19950030005 A KR19950030005 A KR 19950030005A KR 970018399 A KR970018399 A KR 970018399A
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KR
South Korea
Prior art keywords
film
oxide film
silicon
forming
layer metal
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KR1019950030005A
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Korean (ko)
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KR100197980B1 (en
Inventor
김시범
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019950030005A priority Critical patent/KR100197980B1/en
Priority to GB9619116A priority patent/GB2305295B/en
Priority to DE19637458A priority patent/DE19637458A1/en
Priority to JP8244968A priority patent/JP2937886B2/en
Publication of KR970018399A publication Critical patent/KR970018399A/en
Application granted granted Critical
Publication of KR100197980B1 publication Critical patent/KR100197980B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 다층 금속 배선 구조를 갖는 반도체 소자에 있어서, 다층 금속 배선 사이에 형성되는 층간절연막의 굴절율을 향상시켜서 후속 공정의 열처리 공정으로 인하여 소자 내부로 불순물이 침투하여 드레인과 소오스 간의 절연성이 저하되거나 파괴되는 현상이 방지한다.In the semiconductor device having the multi-layered metal wiring structure, the present invention improves the refractive index of the interlayer insulating film formed between the multi-layered metal wires, and impurity penetrates into the device due to a heat treatment process in a subsequent process, thereby reducing the insulation between the drain and the source. To prevent it from being destroyed.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 실시예에 의해 층간절연막이 적용된 2층 금속배선 구조의 CMOS단면도.2 is a CMOS sectional view of a two-layer metal wiring structure to which an interlayer insulating film is applied according to an embodiment of the present invention.

제3도는 절연막의 굴절율과 절연파괴 임계전압과의 관계를 도시한 그래프다.3 is a graph showing the relationship between the refractive index of the insulating film and the breakdown threshold voltage.

제4도는 절연막의 굴절율과 MOSFET의 핫캐리어 동작수명과의 관계를 도시한 그리프도.4 is a glyph diagram showing the relationship between the refractive index of the insulating film and the hot carrier operation life of the MOSFET.

Claims (8)

기판 상부에 MOSFET가 형성되고, 그 상부에 평탄화용 절연막이 형성된 다음, 제1층 금속배선, 층간 절연막, 제2층 금속배선 보호막이 구비되는 반도체소자의 제조 방법에 있어서, 평탄화용 절연막 상부에 제1층 금속배선을 형성하는 단계와, 하부 층간 절연막으로 실리콘-리치 산화막을 전면에 걸쳐 형성하는 단계와, 평탄화용 층간 절연막으로 SOG막을 상기 실리콘 리치 산화막 상부에 도포하는 단계와, 상부 층간 절연막으로 산화막을 상기 SOG막 상부에 증착하는 단계와, 제2층 금속배선을 상기 산화막 상부에 형성하고, 표면 보호막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 제조 방법.A MOSFET is formed over a substrate, and a planarization insulating film is formed over the substrate, and then a first layer metal wiring, an interlayer insulating film, and a second layer metal wiring protective film are provided. Forming a one-layer metal wiring, forming a silicon-rich oxide film over the entire surface with a lower interlayer insulating film, applying a SOG film over the silicon rich oxide film with a planarization interlayer insulating film, and an oxide film with the upper interlayer insulating film. Depositing an upper portion of the SOG film, and forming a second layer metal wiring on the oxide film, and forming a surface protective film. 제1항에 있어서, 상기 실리콘-리치 산화막 대신에 실리콘 질화산화막으로 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 제조 방법.The method of claim 1, further comprising forming a silicon nitride oxide film instead of the silicon-rich oxide film. 제2항에 있어서, 상기 실리콘 질화 산화막은 PECVD 법에 의하여 증착되며, SiH4/N2O/NH3/N2의 반응 기체를 사용하고 막의 응력상태는 -0.5 내지 -1.5dyne/㎠로 하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 2, wherein the silicon nitride oxide film is deposited by PECVD, using a reaction gas of SiH 4 / N 2 O / NH 3 / N 2 and the stress state of the film is -0.5 to -1.5 dyne / ㎠ The manufacturing method of the semiconductor element characterized by the above-mentioned. 제1항에 있어서, 상기 실리콘-리치 산화막은 PECVD법에 의하여 Si 소오스인 SiH4의 유입량을 증가시키고, O의 소오스인 N2O 양을 감소시켜 증착되며, 막의 응력상태는 -0.5 내지 -1.5dyne/㎠로 하는 것을 특징으로 하는 반도체 소자의 제조 방법.The silicon-rich oxide film of claim 1, wherein the silicon-rich oxide film is deposited by increasing the inflow rate of SiH 4, which is a Si source, and reducing the amount of N 2 O, which is a source of O, by PECVD, and has a stress state of -0.5 to -1.5. dyne / cm <2>, The manufacturing method of the semiconductor element characterized by the above-mentioned. 기판 상부에 MOSFET가 형성되고, 그 상부에 평탄화용 절연막이 형성된 다음, 제1층 금속배선, 층간 절연막, 제2층 금속배선 보호막이 구비되는 반도체소자의 제조 방법에 있어서, 평탄화용 절연막 상부에 제1층 금속배선을 형성하는 단계와, 상기 제1층 급속배선 상부에 제2산화막을 형성하는 단계와, 하부 층간 절연막으로 실리콘-리치 한화막을 전면에 걸쳐 형성하는 단계와, 평탄화용 층간 절연막으로 SOG막을 상기 실리콘 리치 산화막 상부에 도포하는 단계와, 상부 층간 절연막으로 산화막을 상기 SOG막 상부에 증착하는 단계와, 제2층 금속배선을 상기 산화막 상부에 형성하고, 표면 보호막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 제조 방법.A MOSFET is formed over a substrate, and a planarization insulating film is formed over the substrate, and then a first layer metal wiring, an interlayer insulating film, and a second layer metal wiring protective film are provided. Forming a one-layer metal interconnection, forming a second oxide film on the first layer rapid interconnection, forming a silicon-rich Hanhwa film across the entire surface with a lower interlayer insulation film, and SOG as a planarization interlayer insulation film Applying a film over the silicon rich oxide film, depositing an oxide film over the SOG film with an upper interlayer insulating film, forming a second layer metal wiring over the oxide film, and forming a surface protective film. A method of manufacturing a semiconductor device, characterized in that. 제5항에 있어서, 상기 실리콘-리치 산화막 대신에 실리콘 질화산화막으로 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 제조 방법.The method of manufacturing a semiconductor device according to claim 5, comprising forming a silicon nitride oxide film instead of the silicon-rich oxide film. 제6도에 있어서, 상기 실리콘 질화 산화막은 PECVD 법에 의하여 증착되며, SiH4/N2O/NH3/N2의 반응 기체를 사용하고 막의 응력상태는 -0.5 내지 -1.5dyne/㎠로 하는 것을 특징으로 하는 반도체 소자의 제조 방법.In Figure 6, the silicon nitride oxide film is deposited by PECVD, using a reaction gas of SiH 4 / N 2 O / NH 3 / N 2 and the stress state of the film is -0.5 to -1.5 dyne / ㎠ The manufacturing method of the semiconductor element characterized by the above-mentioned. 제5항에 있어서, 상기 실리콘-리치 산화막은 PECVD 법에 의하여 Si 소오스인 Sih4의 유입량을 증가시키고, O의 소오스인 N2O 양을 감소시켜 증착되며, 막의 응력상태는 -0.5 내지 -1.5dyne/㎠으로 하는 것을 특징으로 하는 반도체 소자의 제조 방법.The silicon-rich oxide film of claim 5, wherein the silicon-rich oxide film is deposited by increasing the inflow rate of Sih 4, which is a Si source, and reducing the amount of N 2 O, which is a source of O, by PECVD, and has a stress state of -0.5 to -1.5. dyne / cm <2>, The manufacturing method of the semiconductor element characterized by the above-mentioned.
KR1019950030005A 1995-09-14 1995-09-14 Method of manufacturing a semiconductor device KR100197980B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019950030005A KR100197980B1 (en) 1995-09-14 1995-09-14 Method of manufacturing a semiconductor device
GB9619116A GB2305295B (en) 1995-09-14 1996-09-12 Method for forming interlayer insulating film of semiconductor device
DE19637458A DE19637458A1 (en) 1995-09-14 1996-09-13 Method of manufacturing an interlayer insulation film of a semiconductor device
JP8244968A JP2937886B2 (en) 1995-09-14 1996-09-17 Method for forming interlayer insulating film of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950030005A KR100197980B1 (en) 1995-09-14 1995-09-14 Method of manufacturing a semiconductor device

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KR970018399A true KR970018399A (en) 1997-04-30
KR100197980B1 KR100197980B1 (en) 1999-06-15

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KR (1) KR100197980B1 (en)
DE (1) DE19637458A1 (en)
GB (1) GB2305295B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002313968A (en) * 2001-02-08 2002-10-25 Seiko Epson Corp Semiconductor device and its manufacturing method
JP5110783B2 (en) 2004-10-28 2012-12-26 ルネサスエレクトロニクス株式会社 Semiconductor device
CN111725180A (en) * 2020-07-23 2020-09-29 华虹半导体(无锡)有限公司 Interlayer dielectric layer structure for power MOS device and manufacturing method thereof
CN112635329A (en) * 2020-12-14 2021-04-09 华虹半导体(无锡)有限公司 Interlayer dielectric layer of DMOS device and manufacturing method thereof
CN115745417B (en) * 2022-11-08 2024-07-19 福建华佳彩有限公司 Silicon oxynitride film forming method used on indium gallium zinc oxide

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4676867A (en) * 1986-06-06 1987-06-30 Rockwell International Corporation Planarization process for double metal MOS using spin-on glass as a sacrificial layer
US5003062A (en) * 1990-04-19 1991-03-26 Taiwan Semiconductor Manufacturing Co. Semiconductor planarization process for submicron devices

Also Published As

Publication number Publication date
GB9619116D0 (en) 1996-10-23
DE19637458A1 (en) 1997-03-20
JPH09129625A (en) 1997-05-16
JP2937886B2 (en) 1999-08-23
GB2305295A (en) 1997-04-02
KR100197980B1 (en) 1999-06-15
GB2305295B (en) 2000-05-10

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