JPWO2024053215A5 - - Google Patents

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Publication number
JPWO2024053215A5
JPWO2024053215A5 JP2024545454A JP2024545454A JPWO2024053215A5 JP WO2024053215 A5 JPWO2024053215 A5 JP WO2024053215A5 JP 2024545454 A JP2024545454 A JP 2024545454A JP 2024545454 A JP2024545454 A JP 2024545454A JP WO2024053215 A5 JPWO2024053215 A5 JP WO2024053215A5
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JP
Japan
Prior art keywords
output transistor
level
gate
output
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024545454A
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English (en)
Japanese (ja)
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JPWO2024053215A1 (https=
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Application filed filed Critical
Priority claimed from PCT/JP2023/023587 external-priority patent/WO2024053215A1/ja
Publication of JPWO2024053215A1 publication Critical patent/JPWO2024053215A1/ja
Publication of JPWO2024053215A5 publication Critical patent/JPWO2024053215A5/ja
Pending legal-status Critical Current

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JP2024545454A 2022-09-08 2023-06-26 Pending JPWO2024053215A1 (https=)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022143089 2022-09-08
PCT/JP2023/023587 WO2024053215A1 (ja) 2022-09-08 2023-06-26 信号送信装置

Publications (2)

Publication Number Publication Date
JPWO2024053215A1 JPWO2024053215A1 (https=) 2024-03-14
JPWO2024053215A5 true JPWO2024053215A5 (https=) 2025-05-21

Family

ID=90192342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024545454A Pending JPWO2024053215A1 (https=) 2022-09-08 2023-06-26

Country Status (2)

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JP (1) JPWO2024053215A1 (https=)
WO (1) WO2024053215A1 (https=)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4971848B2 (ja) * 2006-03-22 2012-07-11 株式会社豊田中央研究所 低スイッチング損失、低ノイズを両立するパワーｍｏｓ回路
DE102006058889B3 (de) * 2006-12-04 2008-05-21 Atmel Germany Gmbh Verfahren zur Flankenformung von Signalen und Sender-/Empfänger-Baustein für ein Bussystem
US8183885B2 (en) * 2009-04-08 2012-05-22 Broadcom Corporation Circuit for digitally controlling line driver current
JP2017200103A (ja) * 2016-04-28 2017-11-02 ローム株式会社 信号処理装置及びバス通信システム

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