WO2024053215A1 - 信号送信装置 - Google Patents

信号送信装置 Download PDF

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Publication number
WO2024053215A1
WO2024053215A1 PCT/JP2023/023587 JP2023023587W WO2024053215A1 WO 2024053215 A1 WO2024053215 A1 WO 2024053215A1 JP 2023023587 W JP2023023587 W JP 2023023587W WO 2024053215 A1 WO2024053215 A1 WO 2024053215A1
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WIPO (PCT)
Prior art keywords
voltage
charging
gate
output transistor
signal
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Ceased
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PCT/JP2023/023587
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English (en)
French (fr)
Japanese (ja)
Inventor
将希 板坂
信也 増田
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2024545454A priority Critical patent/JPWO2024053215A1/ja
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Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements

Definitions

  • the present disclosure relates to a signal transmitting device.
  • One type of signal transmitter attempts to reduce radiation noise by controlling the slew rate of an output signal.
  • An object of the present disclosure is to provide a signal transmitting device that contributes to reducing radiated noise.
  • a signal transmitting device includes: an output terminal configured to be connected to an application end of a power supply voltage via a pull-up resistor; an output transistor provided between the output terminal and ground; charging the gate of the output transistor, comprising: a capacitor connected between the gate of the transistor and the output terminal; and a charging/discharging circuit configured to charge or discharge the gate of the output transistor according to an input signal. or, by turning on or off the output transistor through discharging, an output signal corresponding to the input signal is generated at the output terminal, and the charging/discharging circuit turns on or off the output transistor when the input signal has a first level.
  • the charging/discharging circuit turns off the output transistor by decreasing the voltage, and the charging/discharging circuit controls the value of the charging current or the discharging when switching the output transistor between on and off in response to a change in the level of the input signal. Set the current value variably.
  • FIG. 1 is an overall configuration diagram of a communication system according to an embodiment of the present disclosure.
  • FIG. 2 is an external perspective view of a transceiver according to an embodiment of the present disclosure.
  • FIG. 3 is a configuration diagram of a transmitting circuit in a transceiver according to an embodiment of the present disclosure.
  • FIG. 4 is a timing chart related to the reference operation.
  • FIG. 5 is a waveform diagram of a control input signal, a charging current, and a discharging current according to a first example belonging to an embodiment of the present disclosure.
  • FIG. 6 is a timing chart relating to the operation of the transmitting circuit according to the first example belonging to the embodiment of the present disclosure.
  • FIG. 7 is a configuration diagram of a charging/discharging circuit according to a first example belonging to an embodiment of the present disclosure.
  • FIG. 8 is a diagram showing several waveforms related to the operation of the charging/discharging circuit of FIG. 7.
  • FIG. 9 is an explanatory diagram of the operation of the charging/discharging circuit of FIG. 7.
  • FIG. 10 is an explanatory diagram of the operation of the charging/discharging circuit of FIG. 7.
  • FIG. 11 is an explanatory diagram of the operation of the charging/discharging circuit of FIG. 7.
  • FIG. 12 is a modified configuration diagram of a charging/discharging circuit according to a first example belonging to an embodiment of the present disclosure.
  • FIG. 12 is a modified configuration diagram of a charging/discharging circuit according to a first example belonging to an embodiment of the present disclosure.
  • FIG. 13 is a waveform diagram of a control input signal, a charging current, and a discharging current according to a second example belonging to an embodiment of the present disclosure.
  • FIG. 14 is a configuration diagram of a charging/discharging circuit according to a second example belonging to the embodiment of the present disclosure.
  • FIG. 15 is a diagram showing several waveforms related to the operation of the charging/discharging circuit of FIG. 14.
  • FIG. 16 is a configuration diagram of a transmitting circuit according to a third example belonging to the embodiment of the present disclosure.
  • FIG. 17 is a diagram showing the waveform of the gate voltage in relation to the control input signal S IN according to a third example belonging to the embodiment of the present disclosure.
  • FIG. 18 is a configuration diagram of a boost circuit according to a third example belonging to the embodiment of the present disclosure.
  • FIG. 19 is a configuration diagram of a charging circuit according to a fourth example belonging to the embodiment of the present disclosure.
  • FIG. 20 is a diagram showing some waveforms related to the operation of the charging circuit of FIG. 19.
  • FIG. 21 is a configuration diagram of a discharge circuit according to a fifth example belonging to the embodiment of the present disclosure.
  • FIG. 22 is a diagram showing some waveforms related to the operation of the discharge circuit of FIG. 21.
  • bus connection terminal BUS referred to by "BUS" below (see Figure 1) may be written as bus connection terminal BUS or may be abbreviated as terminal BUS, but all of them are refer to the same thing.
  • Line refers to wiring through which electrical signals are propagated or applied.
  • the ground refers to a reference conductive portion having a reference potential of 0V (zero volts), or refers to the 0V potential itself.
  • the reference conductive part may be formed using a conductor such as metal.
  • the potential of 0V is sometimes referred to as a ground potential.
  • voltages shown without particular reference represent potentials as seen from ground.
  • Level refers to the level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level.
  • a signal or voltage being at a high level strictly means that the level of the signal or voltage is at a high level, and a signal or voltage being at a low level does not strictly mean that the level of the signal or voltage is at a high level. It means that the signal or voltage level is at low level.
  • the level of a signal may be expressed as a signal level, and the level of a voltage may be expressed as a voltage level.
  • the inverted signal of the signal takes a low level, and when the signal is at a low level, the inverted signal of the signal takes a high level.
  • a switch from a low level to a high level in any signal or voltage of interest is called an up edge.
  • the timing at which an up edge occurs is called an up edge timing. You can read up edge as rising edge.
  • the transition from a high level to a low level in any signal or voltage of interest is called a down edge.
  • the timing at which a down edge occurs is referred to as down edge timing. You can read down edge as falling edge.
  • an on state refers to a state in which the drain and source of the transistor are electrically connected
  • an off state refers to a state in which the drain and source of the transistor are electrically connected. Refers to the state where there is no conduction between the two (blocked state).
  • the MOSFET is understood to be an enhancement type MOSFET unless otherwise specified.
  • MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor.”
  • the back gate of any MOSFET may be considered to be short-circuited to the source.
  • Any switch can be composed of one or more FETs (field effect transistors), and when a switch is on, conduction occurs between both ends of the switch, while when the switch is off, the switch is electrically conductive. There is no conduction between both ends.
  • FETs field effect transistors
  • the period during which the signal level is high is referred to as the high level period
  • the period during which the signal level is low is referred to as the low level period.
  • Connections between multiple parts forming a circuit such as arbitrary circuit elements, wiring (lines), and nodes, may be understood to refer to electrical connections, unless otherwise specified.
  • FIG. 1 shows an overall configuration diagram of a communication system 1 according to an embodiment of the present disclosure.
  • the communication system 1 includes a transceiver 10, a microcomputer 20, and a counterpart device 30.
  • the bus line 51, pull-up resistor 52, backflow prevention diode 53, capacitor 54, data line 61, data line 62, and pull-up resistor 63 are also included in the components of the communication system 1.
  • FIG. 2 is an external perspective view of the transceiver 10.
  • the transceiver 10 includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals exposed to the outside of the transceiver 10 from the housing. It is an electronic component equipped with The transceiver 10 is formed by enclosing a semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the transceiver 10 and the type of casing of the transceiver 10 shown in FIG. 2 are merely examples, and they can be designed arbitrarily. FIG.
  • a power supply terminal VIN shows a power supply terminal VIN, a bus connection terminal BUS, a ground terminal GND, a reception data output terminal RXD, and a transmission data input terminal TXD, which are included in the plurality of external terminals.
  • External terminals other than these may also be provided in the transceiver 10.
  • a power supply voltage VDD is supplied from a voltage source (not shown) to the power supply terminal VIN.
  • Power supply voltage VDD has a predetermined positive DC voltage value.
  • Transceiver 10 is driven based on power supply voltage VDD.
  • a ground terminal GND is connected to ground.
  • the bus connection terminal BUS is connected to one end of the bus line 51, and the other end of the bus line 51 is connected to the counterpart device 30. That is, the bus connection terminal BUS is connected to the counterpart device 30 via the bus line 51.
  • the counterpart device 30 also has a terminal receiving the power supply voltage VDD and a terminal connected to the ground, and is driven based on the power supply voltage VDD.
  • the bus line 51 is connected to the application end 50 of the power supply voltage VDD via a pull-up resistor 52 and a backflow prevention diode 53.
  • the application terminal 50 is a terminal to which the power supply voltage VDD is applied.
  • the backflow prevention diode 53 has a forward direction from the application end 50 toward the bus line 51 and the bus connection terminal BUS.
  • the backflow prevention diode 53 prevents current from flowing from the bus line 51 to the application end 50 . More specifically, the anode of the backflow prevention diode 53 is connected to the application terminal 50, the cathode of the backflow prevention diode 53 is connected to one end of the pull-up resistor 52, and the other end of the pull-up resistor 52 is connected to the bus line 51. connected to.
  • the application end 50 may be connected to the anode of the backflow prevention diode 53 via the pull-up resistor 52, and the cathode of the backflow prevention diode 53 may be connected to the bus line 51.
  • the bus line 51 is connected to the application end 50 only via the pull-up resistor 52 without providing the backflow prevention diode 53.
  • a capacitor 54 is connected between the bus line 51 and ground. That is, one end of the capacitor 54 is connected to the bus line 51, and the other end of the capacitor 54 is connected to the ground. Note that the capacitor 54 may be composed of a plurality of capacitors separated from each other. Capacitor 54 may be omitted.
  • the received data output terminal RXD is connected to one end of the data line 61, and the other end of the data line 61 is connected to the microcomputer 20.
  • the transmission data input terminal TXD is connected to one end of the data line 62, and the other end of the data line 62 is connected to the microcomputer 20. That is, terminals RXD and TXD are connected to microcomputer 20 via data lines 61 and 62.
  • Data line 61 is connected to the application terminal of power supply voltage VCC via pull-up resistor 63.
  • Power supply voltage VCC has a predetermined positive DC voltage value. It does not matter whether the values of the power supply voltages VCC and VDD match or do not match.
  • the microcomputer 20 has a terminal receiving the power supply voltage VCC and a terminal connected to the ground, and is driven based on the power supply voltage VCC.
  • the transceiver 10 includes a receiving circuit RX and a transmitting circuit TX.
  • the receiving circuit RX is connected to a received data output terminal RXD and a bus connection terminal BUS.
  • the transmission circuit TX is connected to a transmission data input terminal TXD and a bus connection terminal BUS.
  • the transceiver 10 and the other device 30 perform bidirectional communication via the bus line 51 in a half-duplex manner.
  • the bidirectional communication assumed in this embodiment is serial communication using a single wire method (that is, serial communication using the bus line 51, which is one wire).
  • the transceiver 10 may function as a master and the other device 30 may function as a slave, or the other device 30 may function as a master and the transceiver 10 may function as a slave.
  • the two-way communication between the transceiver 10 and the other device 30 may be, for example, two-way communication based on the LIN (Local Interconnect Network) standard or the CXPI (Clock Extension Peripheral Interface) standard.
  • one of the transceiver 10 and the other device 30 operates as a transmitting device, and the other functions as a receiving device.
  • the transceiver 10 When the transceiver 10 functions as a receiving device, the counterpart device 30 transmits a signal (hereinafter referred to as signal S R ) via the bus line 51, and the receiving circuit RX transmits a signal to the counterpart device 30 via the bus connection terminal BUS. Receives the signal S R transmitted from the terminal. The receiving circuit RX transmits the received signal S R from the terminal RXD to the microcomputer 20 via the data line 61.
  • the bus connection terminal BUS functions as an input terminal (signal receiving terminal) that receives a signal transmitted from the counterpart device 30.
  • transceiver 10 When transceiver 10 functions as a transmitting device, microcomputer 20 transmits a signal (hereinafter referred to as signal S T ) to transceiver 10 via data line 62 . A signal S T from the microcomputer 20 is received at the terminal TXD.
  • the transmitting circuit TX transmits the signal S T received from the microcomputer 20 to the counterpart device 30 via the bus line 51.
  • the counterpart device 30 may be configured with a transceiver and microcomputer set equivalent to the transceiver 10 and the microcomputer 20, and in this case, the signal S T received from the transceiver 10 is transmitted from the transceiver in the counterpart device 30 to the counterpart device. The information is transmitted to the microcomputer in the side device 30.
  • the bus connection terminal BUS functions as an output terminal (signal transmission terminal) at which a signal to be transmitted from the transceiver 10 appears.
  • Transmission of a signal via the bus line 51 is realized by controlling the level of the bus line 51 to a high level or a low level.
  • the level of the bus line 51 and the level of the bus connection terminal BUS are the same.
  • the level of the bus line 51 is higher than 0V and lower than the power supply voltage VDD.
  • VDD ⁇ k H the level of the bus line 51 corresponds to a high level
  • VDD ⁇ k L the voltage (VDD ⁇ k L )
  • Level 51 corresponds to the low level.
  • the voltage V BUS corresponds to the output voltage (output voltage of the transmitting circuit TX). Therefore, the voltage V BUS when focusing on the configuration or operation of the transmitting circuit TX may be referred to as an output voltage hereinafter.
  • the signal indicated by the output voltage V BUS can be referred to as an output signal.
  • the transmission circuit TX in the transceiver 10 adjusts the slew rate of the output voltage V BUS in order to reduce radiation noise when the level of the bus line 51 changes between a high level and a low level when transmitting a signal via the bus line 51. It has the ability to control.
  • FIG. 3 shows the basic configuration of the transmitting circuit TX.
  • the transmission circuit TX according to the basic configuration includes an output transistor 111, a capacitor (feedback capacitor) 112, a backflow prevention diode 113, a charging/discharging circuit 120, a control input signal supply circuit 130, and a gate voltage limiting circuit 140. Be prepared.
  • the backflow prevention diode 53 see FIG. 1 is not provided in the basic configuration of FIG. 3, the installation or non-installation of the backflow prevention diode 53 is optional. (The same applies to) In the following, the presence of a backflow prevention diode 53 that may be provided in the communication system 1 will be ignored unless otherwise stated.
  • the output transistor 111 is an N-channel MOSFET.
  • the output transistor 111 is provided between the bus connection terminal BUS functioning as an output terminal and the ground, and the transmission circuit TX transmits a signal using the output transistor 111 having an open drain configuration.
  • a backflow prevention diode 113 is provided between the output transistor 111 and the bus connection terminal BUS to prevent the flow of current from the ground toward the bus line 51 via the output transistor 111 and the bus connection terminal BUS.
  • the drain of the output transistor 111 is connected to the cathode of the backflow prevention diode 113, and the anode of the backflow prevention diode 113 is connected to the bus connection terminal BUS.
  • the source of output transistor 111 is connected to ground.
  • the gate voltage of the output transistor 111 (that is, the voltage applied to the gate of the output transistor 111) is represented by the symbol “V G ".
  • the gate threshold voltage of the output transistor 111 is represented by the symbol “V G_TH “.
  • the gate threshold voltage V G_TH has a positive voltage value that depends on the characteristics of the output transistor 111.
  • a capacitor 112 is connected between the gate of the output transistor 111 and the bus connection terminal BUS. That is, one end of the capacitor 112 is connected to the gate of the output transistor 111, and the other end of the capacitor 112 is connected to the bus connection terminal BUS.
  • the charging/discharging circuit 120 charges or discharges the gate of the output transistor 111 according to the control input signal S IN .
  • the charging/discharging circuit 120 can control the output transistor 111 to turn on by charging the gate of the output transistor 111, and can control the output transistor 111 to turn off by discharging the gate of the output transistor 111.
  • the control input signal S IN is a binary signal having a high or low signal level.
  • the high level control input signal S IN has substantially the potential of the internal power supply voltage V REG
  • the low level control input signal S IN has substantially the ground potential.
  • a regulator (not shown) within transceiver 10 generates internal power supply voltage V REG , which is a positive DC voltage, from power supply voltage VDD.
  • the charging/discharging circuit 120 includes a charging circuit 121 and a discharging circuit 122.
  • the charging circuit 121 increases the gate voltage V G of the output transistor 111 by supplying a charging current to the gate of the output transistor 111 during the high level period of the control input signal S IN .
  • the gate voltage V G has an upper limit, and the gate voltage V G does not rise beyond the upper limit voltage.
  • the upper limit voltage of the gate voltage V G is the internal power supply voltage V REG or a predetermined voltage lower than the internal power supply voltage V REG .
  • the upper limit voltage of the gate voltage V G is higher than the gate threshold voltage V G_TH of the output transistor 111.
  • the output transistor 111 switches from the off state to the on state. Specifically, in the process of increasing the gate voltage V G from a sufficiently low voltage (for example, 0 V), when the gate voltage V G becomes equal to or higher than the gate threshold voltage V G_TH , the resistance value of the channel of the output transistor 111 sharply decreases. When the resistance value of the channel of the output transistor 111 becomes sufficiently smaller than the resistance value of the pull-up resistor 52, the voltage V BUS decreases to substantially 0V.
  • the resistance value of the channel of the output transistor 111 refers to the resistance value between the drain and source of the output transistor 111.
  • the discharging circuit 122 lowers the gate voltage V G of the output transistor 111 by drawing a discharge current from the gate of the output transistor 111 during the low level period of the control input signal S IN .
  • the gate voltage V G has a lower limit, and the gate voltage V G does not fall below the lower limit voltage.
  • the lower limit voltage of the gate voltage V G is 0V. In the process of decreasing the gate voltage V G from a voltage higher than the gate threshold voltage V G_TH , when the gate voltage V G becomes lower than the gate threshold voltage V G_TH , the output transistor 111 switches from the on state to the off state.
  • the resistance value of the channel of the output transistor 111 increases sharply.
  • the output voltage V BUS increases to the power supply voltage VDD (However, if the reverse current prevention diode 53 is provided, In this case, the output voltage V BUS increases to a voltage lower than the power supply voltage VDD by the forward voltage of the reverse current prevention diode 53).
  • the charging circuit 121 is configured by a series circuit of a charging current source 121a and a switch 121b
  • the discharging circuit 122 is configured by a series circuit of a discharging current source 122a and a switch 122b.
  • the charging current source 121a is provided between the application end of the internal power supply voltage V REG and the switch 121b, and generates a current I C based on the internal power supply voltage V REG .
  • Switch 121b is provided between charging current source 121a and node 123.
  • the discharge current source 122a is provided between the ground and the switch 122b, and generates a current I D based on the internal power supply voltage V REG .
  • Switch 122b is provided between discharge current source 122a and node 123. Node 123 is connected to the gate of output transistor 111. Switches 121b and 122b are controlled to be turned on or off based on a control input signal S IN .
  • a current I C (hereinafter referred to as charging current I C ) for increasing the gate voltage V G is output from the charging current source 121a via the switch 121b and the node 123. It is supplied to the gate of transistor 111.
  • charging current I C a current I C for increasing the gate voltage V G is output from the charging current source 121a via the switch 121b and the node 123. It is supplied to the gate of transistor 111.
  • the low level period of the control input signal S IN there is no charge exchange between the gate of the output transistor 111 and the charging circuit 121.
  • the switch 121b is turned off while the switch 122b is turned on. Therefore, during the low level period of the control input signal S IN , the current I D (hereinafter referred to as discharge current I D ) for lowering the gate voltage V G is discharged from the gate of the output transistor 111 via the node 123 and the switch 122b. current source 122a.
  • discharge current I D for lowering the gate voltage V G is discharged from the gate of the output transistor 111 via the node 123 and the switch 122b. current source 122a.
  • the high level period of the control input signal S IN there is no charge exchange between the gate of the output transistor 111 and the discharge circuit 122.
  • the control input signal supply circuit 130 generates a control input signal S IN based on the signal S T received from the microcomputer 20 and supplies the control input signal S IN to the charging/discharging circuit 120 .
  • the control input signal supply circuit 130 may generate, for example, a binary signal obtained by shaping the waveform of the signal S T as the control input signal S IN .
  • the configuration of the charging circuit 121 is arbitrary as long as the charging current I C can be supplied to the gate of the output transistor 111 during the high level period of the control input signal S IN .
  • the charging circuit 121 may stop generating the charging current I C during the low level period of the control input signal S IN . In any case, the charging current I C flowing from the charging circuit 121 to the gate of the output transistor 111 is zero during the low level period of the control input signal S IN .
  • the configuration of the discharge circuit 122 is arbitrary as long as the discharge current ID can be drawn from the gate of the output transistor 111 during the low level period of the control input signal S IN .
  • the discharge circuit 122 may stop generating the discharge current ID during the high level period of the control input signal S IN . In any case, the discharge current ID flowing from the gate of the output transistor 111 to the discharge circuit 122 is zero during the high level period of the control input signal S IN .
  • Gate voltage limiting circuit 140 is connected to the gate of output transistor 111 and ground.
  • Gate voltage limiting circuit 140 has two diodes 141 and 142.
  • the anode of diode 141 is connected to the gate of output transistor 111
  • the cathode of diode 141 is connected to the anode of diode 142
  • the cathode of diode 142 is connected to ground.
  • the gate voltage limiting circuit 140 has a function of suppressing the gate voltage V G from exceeding a predetermined limit voltage V LIM , and may be any circuit having this function.
  • the limiting voltage V LIM here is higher than the gate threshold voltage V G_TH , and corresponds to the sum of the forward voltages of the diodes 141 and 142 in the configuration example of FIG.
  • the circuit 140 may be formed by a series circuit of three or more diodes.
  • the output transistor 111 In the process in which the output transistor 111 is switched from the OFF state to the ON state due to an increase in the gate voltage V G based on the charging current I C , the output voltage V BUS decreases, and the decrease in the output voltage V BUS is transferred to the output transistor 111 via the capacitor 112 . feedback to the gate. Conversely, in the process in which the output transistor 111 is switched from the on state to the off state due to a decrease in the gate voltage V G based on the discharge current ID, the output voltage V BUS increases, and the increase in the output voltage V BUS is caused through the capacitor 112. It is fed back to the gate of the output transistor 111. Therefore, to the charge/discharge circuit 120, the capacitance value of the capacitor 112 appears to be equivalently larger than the actual capacitance value of the capacitor 112 due to the Miller effect. In other words, the capacitor 112 functions as a Miller capacitance.
  • FIG. 4 shows a timing chart of reference operation.
  • the reference operation is a signal transmission operation realized using the transmission circuit TX having the basic configuration shown in FIG. Assume that times t 0 , t 1 , t 2 , t 3 , t 4 , t 5 , t 6 and t 7 arrive in this order as time passes.
  • the control input signal S IN has a low level
  • the gate voltage V G is 0V
  • the output voltage V BUS is equal to the power supply voltage VDD.
  • the charging current I C is controlled to have a constant value during the high level period of the control input signal S IN
  • the discharging current I D is controlled to have a constant value during the low level period of the control input signal S IN . be done.
  • the gate voltage V G drops to 0V during the low level period of the control input signal S IN
  • the next up edge occurs in the control input signal S IN , the same operations as those after time t1 described above are repeated.
  • the output signal indicated by the output voltage V BUS is a signal according to the control input signal S IN , and specifically, a signal that is a logical inversion signal of the control input signal S IN and whose slew rate is appropriately controlled. It is.
  • the control input signal S IN (therefore, the signal S T from the microcomputer 20) can be recognized and restored. Radiation noise from the bus line 51 can be suppressed by appropriately controlling the slew rate of the output signal.
  • Time t 2 corresponds to the start time of the decrease in the output voltage V BUS
  • time t 3 corresponds to the end time of the decrease in the output voltage V BUS
  • Time t 5 corresponds to the start time of the increase in the output voltage V BUS
  • time t 6 corresponds to the end time of the increase in the output voltage V BUS .
  • the gate voltage V G changes sharply at each of times t 2 , t 3 , t 5 and t 6 . Therefore, in the waveform of the output voltage V BUS related to the reference operation, angles E1, E2, E3, and E4 occur at times t 2 , t 3 , t 5 , and t 6 , respectively. Angles included in the waveform of the output voltage V BUS increase radiated noise. If these corners can be removed from the waveform of the output voltage V BUS , radiation noise can be further suppressed. However, among the angles E1 to E4, the angle E4 may not actually occur due to the action of a low-pass filter by the pull-up resistor 52 and the capacitor 54.
  • the charging current source 121a is configured as a variable current source that has the function of continuously varying the value of the current I C , and the discharging current source 122a continuously varies the value of the current I D. It is configured as a functional variable current source.
  • FIG. 5 shows waveforms of the control input signal S IN , the charging current I C and the discharging current ID according to the first embodiment.
  • the charging current I C is zero during the low level period of the control input signal S IN .
  • the charging current source 121 a supplies a charging current I C larger than 0 to the gate of the output transistor 111 .
  • the value of the charging current I C is set to the charging initial value VAL C1 , and thereafter, charging is started as time passes.
  • the value of the current I C is continuously increased (that is, gradually increased) from the charging initial value VAL C1 toward the charging reference value VAL C2 .
  • the value of the charging current I C may be maintained at the charging reference value VAL C2 .
  • a lower limit may be set for the length of the high level period of the control input signal S IN .
  • the discharge current ID is zero during the high level period of the control input signal S IN .
  • the discharge current source 122 a draws a discharge current ID larger than 0 from the gate of the output transistor 111 .
  • the discharge current source 122a sets the value of the discharge current ID to the discharge initial value VAL D1 when a down edge occurs in the control input signal S IN , and then discharges as time passes.
  • the value of the current ID is continuously increased (that is, gradually increased) from the discharge initial value VAL D1 toward the discharge reference value VAL D2 .
  • the value of the discharge current ID may be maintained at the discharge reference value VAL D2 .
  • a lower limit may be set for the length of the low level period of the control input signal S IN .
  • the charging initial value VAL C1 may be the same value as the discharging initial value VAL D1 , or may be different.
  • the charging reference value VAL C2 may be the same value as the discharging reference value VAL D2 , or may be different.
  • FIG. 6 is a timing chart according to the first embodiment.
  • the sharp change in gate voltage V G near time t 2 is more relaxed than in the reference operation.
  • the waveform at the angle E1 observed in the reference operation is smoother in the first embodiment than in FIG. 4, and radiation noise is reduced.
  • the sharp change in gate voltage V G near time t 5 is more relaxed than in the reference operation.
  • the waveform at the angle E3 observed in the reference operation is smoother in the first embodiment than in FIG. 4, and radiation noise is reduced.
  • the charging/discharging circuit 200 shown in FIG. 7 can be used as the charging/discharging circuit 120 in FIG. 3.
  • the charging/discharging circuit 200 includes switches 121b and 122b and components referenced by 201-212. It can be considered that the components referenced 201-212 form the current sources 121a and 122a of FIG. 3.
  • the constant voltage generation circuit 201 generates and outputs a voltage V REF having a constant positive voltage value.
  • a voltage V REF is applied to the non-inverting input terminal of the operational amplifier 202 .
  • the inverting input terminal and output terminal of operational amplifier 202 are short-circuited. Therefore, the operational amplifier 202 functions as a voltage follower and outputs the voltage V REF from its own output terminal at low impedance.
  • the output terminal of operational amplifier 202 is connected to one end of resistor 204 and to node 213 via resistor 203.
  • the other end of resistor 204 is connected to node 214.
  • Node 213 is connected to ground via capacitor 205.
  • node 213 is connected to one end of the switch 209, and the other end of the switch 209 is connected to ground. Further, node 213 is connected to one end of switch 207, and the other end of switch 207 is connected to node 215. Node 214 is connected to ground via capacitor 206. Further, node 214 is connected to one end of switch 210, and the other end of switch 210 is connected to node 215. One end of switch 208 is connected to node 214, and the other end of switch 208 is connected to ground.
  • V CNT1 The voltage applied to node 215 is represented by the symbol “V CNT1 ”.
  • V/I conversion circuits 211 and 212 are connected to node 215 and receive voltage V CNT1 .
  • the V/I conversion circuit 211 converts the voltage V CNT1 into a current I C .
  • the V/I conversion circuit 212 converts the voltage V CNT1 into a current ID .
  • a switch 121b is interposed between the V/I conversion circuit 211 and the node 123 (see FIG. 3). By turning on the switch 121b only during the high level period of the control input signal S IN , the current I C obtained by conversion by the V/I conversion circuit 211 is supplied to the gate of the output transistor 111 as a charging current I C. Ru.
  • a switch 122b is interposed between the V/I conversion circuit 212 and the node 123 (see FIG. 3). By turning on the switch 122b only during the low level period of the control input signal S IN , the current I D obtained by conversion by the V/I conversion circuit 212 is extracted from the gate of the output transistor 111 as a discharge current I D. .
  • FIG. 8 shows some waveforms related to the operation of the charging/discharging circuit 200 of FIG. 7.
  • the waveform shown at the bottom of FIG. 8 is a composite of the waveform of the charging current I C during the high level period of the control input signal S IN and the waveform of the discharging current I D during the low level period of the control input signal S IN . corresponds to something.
  • signals T_A and T_B are generated based on the control input signal S IN .
  • Signal T_A is the same signal as control input signal S IN
  • signal T_B is an inverted signal of control input signal S IN .
  • a signal T_A is provided to switches 207 and 208 (ie, a control input signal S IN is provided).
  • the switches 207 and 208 are turned on during the high level period of the signal T_A, and turned off during the low level period of the signal T_A.
  • a signal T_B is supplied to the switches 209 and 210 (ie, an inverted signal of the control input signal S IN ).
  • the switches 209 and 210 are turned on during the high level period of the signal T_B and turned off during the low level period of the signal T_B.
  • the V/I conversion circuit 211 sets the value of the current I C to the charging initial value VAL C1 when the voltage V CNT1 is 0V, increases the value of the current I C as the voltage V CNT1 rises from 0V, and increases the voltage
  • V CNT1 is equal to voltage V REF
  • the value of current I C is set to charging reference value VAL C2 .
  • the V/I conversion circuit 212 sets the value of the current I D to the discharge initial value VAL D1 when the voltage V CNT1 is 0V, increases the value of the current I D as the voltage V CNT1 rises from 0V, and adjusts the voltage.
  • V CNT1 is equal to voltage V REF
  • the value of current ID is set to discharge reference value VAL D2 .
  • the circuit configuration of the charging/discharging circuit 120 is arbitrary as long as the change characteristics of the charging current I C and the discharging current ID described with reference to FIG. 5 can be obtained.
  • the charging/discharging circuit 200a in FIG. 12 may be used as the charging/discharging circuit 120.
  • the resistor 203, capacitor 205, switches 207, 209, and 210 are removed from the charging/discharging circuit 200, and the one-shot pulse generation circuit 218 is added to the charging/discharging circuit 200.
  • the discharge circuit 200 is transformed into a charge/discharge circuit 200a.
  • One-shot pulse generation circuit 218 outputs signal T_A' based on control input signal S IN .
  • Signal T_A' has a low level in principle.
  • the one-shot pulse generation circuit 218 keeps the signal T_A' at a high level for a predetermined minute period at each timing when an up edge occurs and a down edge occurs in the control input signal S IN .
  • the signal T_A' is supplied to the switch 208, and the switch 208 is turned on during the high level period of the signal T_A' and turned off during the low level period of the signal T_A'.
  • the voltage at the node 214 sharply drops to 0V every time an up edge or down edge occurs in the control input signal S IN , and then at a time constant determined by the values of the resistor 204 and capacitor 206. It gradually (and therefore continuously) increases towards the voltage V REF .
  • the voltage at the node 214 always matches the voltage V CNT1 . Therefore, the waveforms of the currents I C and ID generated in the V/I conversion circuits 211 and 212 of the charge/discharge circuit 200a are equivalent to those in the charge/discharge circuit 200.
  • the charging current source 121a is configured as a variable current source that has a function of varying the value of the current I C in stages, and the discharging current source 122a varies the value of the current I D in stages. It is configured as a functional variable current source. In other words, a gradual change is a discontinuous change.
  • FIG. 13 shows waveforms of the control input signal S IN , the charging current I C and the discharging current ID according to the second embodiment.
  • the charging current I C is zero during the low level period of the control input signal S IN .
  • the charging current source 121 a supplies a charging current I C larger than 0 to the gate of the output transistor 111 .
  • the charging current source 121a sets the value of the charging current I C to the charging initial value VAL C1 when an up edge occurs in the control input signal S IN , and sets the value of the charging current I C to the charging initial value VAL C1 when the up edge of the control input signal S IN
  • the value of the charging current I C is increased from the charging initial value VAL C1 to the charging reference value VAL C2 (that is, it is increased in stages).
  • the value of the charging current I C may be maintained at the charging reference value VAL C2 .
  • a lower limit may be set for the length of the high level period of the control input signal S IN .
  • the discharge current ID is zero during the high level period of the control input signal S IN .
  • the discharge current source 122 a draws a discharge current ID larger than 0 from the gate of the output transistor 111 .
  • the discharge current source 122a sets the value of the discharge current ID to the discharge initial value VAL D1 when a down edge occurs in the control input signal S IN , and sets the value of the discharge current ID to the discharge initial value VAL D1 when the down edge of the control input signal S IN
  • the value of the discharge current ID is increased from the discharge initial value VAL D1 to the discharge reference value VAL D2 (that is, it is increased in stages).
  • the value of the discharge current ID may be maintained at the discharge reference value VAL D2 .
  • a lower limit may be set for the length of the low level period of the control input signal S IN .
  • the circuit configuration of the charging/discharging circuit 120 is arbitrary as long as the change characteristics of the charging current I C and the discharging current ID described with reference to FIG. 13 can be obtained.
  • the charging/discharging circuit 250 shown in FIG. 14 can be used as the charging/discharging circuit 120 in FIG. 3.
  • FIG. 15 shows some waveforms related to the operation of the charging/discharging circuit 250.
  • the waveform shown at the bottom of FIG. 15 is a composite of the waveform of the charging current I C during the high level period of the control input signal S IN and the waveform of the discharging current I D during the low level period of the control input signal S IN . corresponds to something.
  • the charging/discharging circuit 250 includes switches 121b and 122b and components referenced by 251-257. It can be considered that the components referenced by 251-257 form the current sources 121a and 122a of FIG.
  • the constant voltage generation circuit 251 generates and outputs a voltage V REF1 having a constant positive voltage value.
  • the constant voltage generation circuit 252 generates and outputs a voltage V REF2 having a constant positive voltage value.
  • the voltage V REF2 is higher than the voltage V REF1 .
  • Voltage V REF1 is applied to one end of switch 253, and the other end of switch 253 is connected to node 258.
  • a voltage V REF2 is applied to one end of switch 254, and the other end of switch 254 is connected to node 258.
  • the voltage applied to node 258 is represented by the symbol "V CNT2 ".
  • V/I conversion circuits 255 and 256 are connected to node 258 and receive voltage V CNT2 .
  • the V/I conversion circuit 255 converts the voltage V CNT2 into a current I C.
  • V/I conversion circuit 256 converts voltage V CNT2 into current ID .
  • the switch control circuit 257 generates signals T_A and T_B for controlling on or off of the switches 253 and 254 based on the control input signal S IN .
  • the switch 253 is turned on during the high level period of the signal T_A, and turned off during the low level period of the signal T_A.
  • the switch 254 is turned on during the high level period of the signal T_B and turned off during the low level period of the signal T_B.
  • the switch control circuit 257 is provided with a timer that measures the elapsed time from the up-edge timing or down-edge timing of the control input signal S IN .
  • the switch control circuit 257 has a first period from the up edge timing of the control input signal S IN until a predetermined time Tup_C2 has elapsed, and a second period from the down edge timing of the control input signal S IN to the elapse of a predetermined time Tup_D2.
  • the signal T_A is set to high level and the signal T_B is set to low level.
  • a switch 121b is interposed between the V/I conversion circuit 255 and the node 123 (see FIG. 3). By turning on the switch 121b only during the high level period of the control input signal S IN , the current I C obtained by conversion by the V/I conversion circuit 255 is supplied to the gate of the output transistor 111 as a charging current I C. Ru.
  • a switch 122b is interposed between the V/I conversion circuit 256 and the node 123 (see FIG. 3). By turning on the switch 122b only during the low level period of the control input signal S IN , the current I D obtained through conversion by the V/I conversion circuit 256 is extracted from the gate of the output transistor 111 as a discharge current I D. .
  • the value of the charging current I C or the discharging current I D may be set variably in three or more stages. That is, for example, when an up edge occurs in the control input signal S IN , the charging current source 121a first sets the value of the charging current I C to the charging initial value VAL C1, and then sets the value of the charging current I C to the charging initial value VAL C1 from the up edge timing of the control input signal S IN .
  • the value of the charging current I C is increased from the charging initial value VAL C1 to the charging intermediate value, and then, after a second predetermined time has elapsed, the value of the charging current I C is increased from the charging intermediate value to the charging value. It may be increased to the reference value VAL C2 .
  • the intermediate charging value is larger than the initial charging value VAL C1 and smaller than the charging reference value VAL C2 .
  • the discharge current source 122a first sets the value of the discharge current ID to the discharge initial value VAL D1 , and After a first predetermined time has elapsed, the value of the discharge current I D is increased from the initial discharge value VAL D1 to the intermediate discharge value, and then, after a further second predetermined time has elapsed, the value of the discharge current I D is increased to the intermediate discharge value.
  • the discharge reference value VAL D2 may be increased from the discharge reference value VAL D2.
  • the discharge intermediate value is larger than the discharge initial value VAL D1 and smaller than the discharge reference value VAL D2 .
  • a third embodiment will be explained. If it takes a long time to raise the gate voltage V G of the output transistor 111 from 0 V to around the gate threshold voltage V G_TH , the time from the rising edge timing of the control input signal S IN to the time when the output voltage V BUS starts to decrease will become longer. become longer. That is, the responsiveness of the transceiver 10 involved in transmission is reduced. This can be particularly noticeable when the method of the first or second embodiment is adopted. This is because when the method of the first or second embodiment is adopted, the charging current I C can be held low for a certain period of time from the up-edge timing of the control input signal S IN .
  • a technique for quickly increasing the gate voltage V G will be described.
  • the third embodiment can especially be implemented in combination with the first or second embodiment. However, it is not essential to combine the third embodiment with the first or second embodiment, and the third embodiment can also be combined with other embodiments described below.
  • Boost circuit 150 is connected to the gate of output transistor 111.
  • the boost circuit 150 is activated when an up edge occurs in the control input signal S IN , and supplies a boost current to the gate of the output transistor 111 until the gate voltage V G reaches a predetermined voltage (for example, gate threshold voltage V G_TH ). supply.
  • the boost current is supplied to the gate of the output transistor 111 separately from the charging current I C from the charging circuit 121, thereby increasing the speed at which the gate voltage V G rises. Specifically, in comparison with the case where the gate voltage V G is increased only by the charging current I C from the charging circuit 121, the rate of increase in the gate voltage V G is increased by additionally supplying the boost current.
  • the gate voltage V G rises significantly exceeding the gate threshold voltage V G_TH after the output transistor 111 is switched from the OFF state to the ON state, then the gate voltage V G increases in response to the down edge of the control input signal S IN . It takes a relatively long time to lower V G to around the gate threshold voltage V G_TH . This also becomes a factor in reducing the responsiveness of the transceiver 10 involved in transmission.
  • a rise suppression diode 114 is provided in the transmission circuit TX, the anode of the rise suppression diode 114 is connected to the gate of the output transistor 111, and the cathode of the rise suppression diode 114 is connected to the drain of the output transistor 111. Connect to.
  • the gate voltage V G is limited to the voltage (V D111 +Vf 114 ) or less.
  • the voltage (V D111 +Vf 114 ) represents a voltage higher than the drain voltage (V D111 ) of the output transistor 111 by the forward voltage (Vf 114 ) of the rise suppression diode 114 . Therefore, in a state where the output transistor 111 is turned on and the drain voltage of the output transistor 111 drops to substantially 0V, the gate voltage V G is limited to the forward voltage of the rise suppressing diode 114 or less.
  • a diode having a forward voltage equal to or slightly larger than the gate threshold voltage V G_TH can be used as the rise suppression diode 114 . This prevents the gate voltage V G from rising significantly beyond the gate threshold voltage V G_TH after the output transistor 111 is switched from the off state to the on state. Therefore, the responsiveness of the transceiver 10 related to transmission can be improved.
  • FIG. 17 shows the waveform of the gate voltage V G in relation to the control input signal S IN .
  • a waveform 611 represents the waveform of the gate voltage V G in the transmitting circuit TX according to the first or second embodiment.
  • a waveform 612 represents the waveform of the gate voltage V G in the transmitting circuit TX that is a combination of the first or second embodiment and the third embodiment.
  • the waveform of signal T_B shown in FIG. 17 will be referred to later. It can be seen from the comparison between the waveforms 611 and 612 that the installation of the boost circuit 150 increases the rate of rise of the gate voltage V G to around the gate threshold voltage V G_TH . Furthermore, it can be seen that the provision of the rise suppressing diode 114 makes it difficult for the gate voltage V G to increase beyond the gate threshold voltage V G_TH .
  • FIG. 18 shows a configuration example of the boost circuit 150.
  • the boost circuit 150 in FIG. 18 includes a current source 151, transistors 152 to 154 that are N-channel MOSFETs, and a resistor 155.
  • Current source 151 outputs a constant current toward node 156 from the application end of internal power supply voltage V REG based on internal power supply voltage V REG . However, when the voltage at node 156 reaches internal power supply voltage V REG due to constant current output, current source 151 stops further outputting constant current.
  • Internal power supply voltage V REG is applied to the drain of transistor 152.
  • the source of transistor 152 is connected to one end of resistor 155 and also to the gate of output transistor 111.
  • the other end of resistor 155 is connected to the gate of transistor 153.
  • the gate of transistor 152 and the drains of transistors 153 and 154 are connected to node 156. Each source of transistors 153 and 154 is connected to ground.
  • a signal T_B is supplied to the gate of the transistor 154.
  • the signal T_B is an inverted signal of the control input signal S IN as described in the first embodiment (see FIG. 17).
  • boost circuit 150 in FIG. 18 Since the signal T_B has a high level during the low level period of the control input signal S IN , the transistor 154 is turned on. When the transistor 154 is on, the constant current output from the current source 151 flows through the channel of the transistor 154, so the potential of the node 156 is sufficiently low, and as a result, the transistor 152 is maintained in the off state. Since the boost current is supplied to the gate of the output transistor 111 via the transistor 152 only when the transistor 152 is on, no boost current is supplied when the transistor 152 is off. Further, immediately before the rising edge timing of the control input signal S IN , the gate voltage V G is set to 0V by the function of the discharging circuit 122, so the transistor 153 is in an off state.
  • the signal T_B becomes low level and the transistor 154 is turned off.
  • the transistor 153 is also off. Therefore, as the potential of the node 156 increases due to the constant current from the current source 151, the transistor 152 is switched from off to on, and the drain current of the transistor 152 flows from the application terminal of the internal power supply voltage V REG through the transistor 152 as a boost current. It is supplied to the gate of output transistor 111.
  • the gate threshold voltage (predetermined voltage) of the transistor 153 is preferably the same as the gate threshold voltage V G_TH of the output transistor 111 or slightly higher than the gate threshold voltage V G_TH .
  • FIG. 19 shows a charging circuit 300C according to the fourth embodiment.
  • the charging circuit 300C can be used as the charging circuit 121 in FIG. 3.
  • FIG. 20 shows some waveforms when the charging circuit 300C of FIG. 19 is used as the charging circuit 121. Note that the waveform of the output voltage V BUS shown in FIG. 20 is a waveform when viewed from the reference operation of FIG. 4 and assuming that only measures to smooth the corner E2 have been taken.
  • the charging circuit 300C includes a switch 121b and components referenced by 301 to 308. It can be considered that the charging current source 121a of FIG. 3 is formed by the components referred to by numerals 301 to 308.
  • the constant voltage generation circuit 301 generates and outputs a voltage V REF having a constant positive voltage value.
  • a voltage V REF is applied to the non-inverting input terminal of the operational amplifier 302 .
  • the inverting input terminal and output terminal of operational amplifier 302 are short-circuited. Therefore, the operational amplifier 302 functions as a voltage follower and outputs the voltage V REF from its own output terminal at low impedance.
  • the output terminal of the operational amplifier 302 is connected to one end of the resistor 303.
  • the other end of resistor 303 is connected to node 311.
  • Node 311 is connected to ground via capacitor 304. Further, the node 311 is connected to one end of the switch 305, and the other end of the switch 305 is connected to ground.
  • V/I conversion circuit 306 is connected to node 311 and receives voltage V CNT4 .
  • V/I conversion circuit 306 converts voltage V CNT4 into current I C .
  • One-shot pulse generation circuit 308 outputs signal T_C based on the output signal of comparator 307.
  • Signal T_C has a low level in principle.
  • the one-shot pulse generation circuit 308 sets the signal T_C to a high level for a predetermined minute time at the timing when an up edge occurs in the output signal of the comparator 307.
  • the signal T_C is supplied to the switch 305, and the switch 305 is turned on during the high level period of the signal T_C and turned off during the low level period of the signal T_C. Therefore, in the charging circuit 300C, the voltage at the node 311 sharply drops to 0V every time an up edge occurs in the output signal of the comparator 307, and then the voltage V REF gradually (and therefore continuously) increases towards .
  • the V/I conversion circuit 306 sets the value of the current I C to the charging initial value VAL C1 when the voltage V CNT4 is 0V, increases the value of the current I C as the voltage V CNT4 rises from 0V, and increases the voltage.
  • V CNT4 is equal to voltage V REF
  • the value of current I C is set to charging reference value VAL C2 .
  • a switch 121b is interposed between the V/I conversion circuit 306 and the node 123 (see FIG. 3). By turning on the switch 121b only during the high level period of the control input signal S IN , the current I C obtained by conversion by the V/I conversion circuit 306 is supplied to the gate of the output transistor 111 as a charging current I C. Ru.
  • the value of the charging current I C can be changed. will temporarily decrease from the charging reference value VAL C2 .
  • the value of the charging current I C decreases from the charging reference value VAL C2 to the initial charging value VAL C1 with the establishment of “V BUS ⁇ V DET_L ”, the value of the charging current I C decreases gradually (therefore continuously) over a predetermined period of time. ) Return to charging reference value VAL C2 .
  • the value of the charging current I C is lowered from the charging reference value VAL C2 to the charging initial value VAL C1 when "V BUS ⁇ V DET_L " is satisfied, and the value of the charging current I C is decreased for a predetermined period of time.
  • the value of the charging current I C may be returned from the charging initial value VAL C1 to the charging reference value VAL C2 . That is, the value of the charging current I C may be returned to the charging reference value VAL C2 stepwise (discontinuously). At this time, the value of the charging current I C may be returned to the charging reference value VAL C2 from the initial charging value VAL C1 through a plurality of stages.
  • the steep change in gate voltage V G near time t 3 in FIG. 4 is more relaxed than in the reference operation.
  • the waveform at the angle E2 observed in the reference operation is smoother in the fourth embodiment than in FIG. 4, and radiation noise is reduced.
  • the fourth embodiment can be combined with the first or second embodiment, and can also be combined with the third embodiment.
  • the charge/discharge circuit 120 changes the value of the charging current I C to the charging initial value VAL C1 (FIG. 5) in response to the rising edge of the control input signal S IN . (or see FIG. 13), the value of the charging current I C is changed continuously or discontinuously ( step by step).
  • the charging/discharging circuit 120 determines the value of the charging current I C. is lowered from the charge reference value VAL C2 to the charge initial value VAL C1 , and then returned to the charge reference value VAL C2 over a second predetermined period of time (see FIG. 20).
  • a fifth embodiment will be explained.
  • a technique for smoothing the corner E4 in FIG. 4 (in other words, removing the corner E4 from the waveform of the output signal) will be described.
  • FIG. 19 shows a discharge circuit 350D according to the fifth embodiment.
  • the discharge circuit 350D can be used as the discharge circuit 122 in FIG. 3.
  • FIG. 20 shows some waveforms when the discharge circuit 350D of FIG. 19 is used as the discharge circuit 122. Note that the waveform of the output voltage V BUS shown in FIG. 20 is a waveform when viewed from the reference operation of FIG. 4 and assuming that only measures to smooth the corner E4 have been taken.
  • the discharge circuit 350D includes a switch 122b and components referenced by 351 to 358. It can be considered that the components referred to by numerals 351 to 358 form the discharge current source 122a of FIG. 3.
  • the constant voltage generation circuit 351 generates and outputs a voltage V REF having a constant positive voltage value.
  • a voltage V REF is applied to the non-inverting input terminal of the operational amplifier 352 .
  • the inverting input terminal and output terminal of operational amplifier 352 are shorted. Therefore, the operational amplifier 352 functions as a voltage follower and outputs the voltage V REF from its own output terminal at low impedance.
  • the output terminal of the operational amplifier 352 is connected to one end of the resistor 353.
  • the other end of resistor 353 is connected to node 361.
  • Node 361 is connected to ground via capacitor 354. Further, the node 361 is connected to one end of the switch 355, and the other end of the switch 355 is connected to ground.
  • V CNT5 The voltage applied to node 361 is represented by the symbol "V CNT5 ".
  • V/I conversion circuit 356 is connected to node 361 and receives voltage V CNT5 .
  • V/I conversion circuit 356 converts voltage V CNT5 to current ID .
  • One-shot pulse generation circuit 358 outputs signal T_D based on the output signal of comparator 357.
  • Signal T_D has a low level in principle.
  • the one-shot pulse generation circuit 358 sets the signal T_D to a high level for a predetermined minute time at the timing when an up edge occurs in the output signal of the comparator 357.
  • the signal T_D is supplied to the switch 355, and the switch 355 is turned on during the high level period of the signal T_D and turned off during the low level period of the signal T_D. Therefore, in the discharging circuit 350D, the voltage at the node 361 sharply drops to 0V every time an up edge occurs in the output signal of the comparator 357, and then the voltage V REF gradually (and therefore continuously) increases towards .
  • the V/I conversion circuit 356 sets the value of the current ID to the discharge initial value VAL D1 when the voltage V CNT5 is 0V, increases the value of the current ID as the voltage V CNT5 rises from 0V, and increases the voltage.
  • V CNT5 is equal to voltage V REF
  • the value of current ID is set to discharge reference value VAL D2 .
  • a switch 122b is interposed between the V/I conversion circuit 356 and the node 123 (see FIG. 3). By turning on the switch 122b only during the low level period of the control input signal S IN , the current I D obtained through conversion by the V/I conversion circuit 356 is extracted from the gate of the output transistor 111 as a discharge current I D. .
  • the value of the discharge current I D will temporarily decrease from the discharge reference value VAL D2 .
  • the value of the discharge current I D decreases from the discharge reference value VAL D2 to the initial discharge value VAL D1 with the establishment of “V BUS > V DET_H ”, the value of the discharge current ID decreases gradually (therefore continuously) over a predetermined period of time. ) Return to discharge reference value VAL D2 .
  • the value of the discharge current I D is decreased from the discharge reference value VAL D2 to the discharge initial value VAL D1 , and the discharge current I D is decreased for a predetermined period of time.
  • the value of the discharge current ID may be returned from the discharge initial value VAL D1 to the discharge reference value VAL D2 . That is, the value of the discharge current ID may be returned to the discharge reference value VAL D2 stepwise (discontinuously). At this time, the value of the discharge current ID may be returned to the discharge reference value VAL D2 from the initial discharge value VAL D1 through a plurality of stages.
  • the steep change in gate voltage V G near time t 6 in FIG. 4 is more relaxed than in the reference operation.
  • the waveform of the corner E4 observed in the reference operation is smoother in the fifth embodiment than in FIG. 4, and radiation noise is reduced.
  • the waveform at the corner E4 can be sufficiently smooth without taking any measures on the transceiver 10 side. . Therefore, the measures according to the fifth embodiment are not necessarily required in the transceiver 10.
  • the fifth embodiment can be combined with the first or second embodiment, and can also be combined with the third embodiment.
  • the charging/discharging circuit 120 changes the value of the discharge current ID to the discharge initial value VAL D1 (FIG. 5) in response to the down edge of the control input signal S IN . (or see FIG. 13), the value of the discharge current ID is changed from the initial discharge value VAL D1 to the discharge reference value VAL D2 continuously or discontinuously ( step by step).
  • the charging/discharging circuit 120 calculates the value of the discharge current I D. is lowered from the discharge reference value VAL D2 to the discharge initial value VAL D1 , and then returned to the discharge reference value VAL D2 over a second predetermined period of time (see FIG. 22).
  • the communication system 1 can be mounted on a vehicle such as an automobile.
  • the communication system 1 can be used as a system for performing bidirectional communication in accordance with the LIN standard or the CXPI standard. More specifically, for example, communication between the transceiver 10 and the other device 30 can be used to communicate signals for realizing body control of power windows, mirrors, electric seats, door locks, etc. installed in a car. can.
  • the communication system 1 is not limited to in-vehicle use.
  • the communication system 1 can be applied to any application where relatively low-speed communication is performed.
  • the transceiver 10 includes a signal transmitting device that generates an output signal corresponding to an input signal at a bus connection terminal BUS functioning as an output terminal (in other words, transmits it from the bus connection terminal BUS).
  • the components of the signal transmitting device include a transmitting circuit TX, and may also include a bus connection terminal BUS.
  • the input signal for the signal transmitting device can be understood as the control input signal S IN . Since the control input signal S IN is a signal based on the signal S T from the microcomputer 20, it may be understood that the input signal to the signal transmitting device is the signal S T .
  • a semiconductor device including the functions of the transceiver 10 and the microcomputer 20 may be formed, and in this case, a signal transmitting device will be provided within the semiconductor device.
  • channels of FETs field effect transistors
  • the channel type of any FET may be varied between P-channel and N-channel.
  • any transistor mentioned above may be any type of transistor as long as no inconvenience occurs.
  • any transistor described above as a MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor, as long as no inconvenience occurs.
  • Any transistor has a first electrode, a second electrode, and a control electrode.
  • a FET one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate.
  • an IGBT one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate.
  • a bipolar transistor that does not belong to an IGBT one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.
  • a signal transmitting device (10) includes an output terminal (BUS) configured to be connected to an application terminal (50) of a power supply voltage (VDD) via a pull-up resistor (52); an output transistor (111) provided between the output terminal and ground; a capacitor (112) connected between the gate of the output transistor and the output terminal; a charging/discharging circuit (120) configured to charge or discharge a gate of a transistor; producing an output signal at the output terminal, the charging/discharging circuit supplying a charging current (I C ) to the gate of the output transistor when the input signal has a first level (e.g., a high level) to produce the output signal at the output terminal;
  • the output transistor is turned on by increasing the gate voltage of the transistor, and when the input signal has a second level (eg, low level), a discharge current (I D ) is drawn from the gate of the output transistor to increase the gate voltage.
  • the charging/discharging circuit turns off the output transistor by decreasing the value of the charging current or the discharging current when switching the output transistor between on and off in response to a change in the level of the input signal.
  • This is a configuration (first configuration) in which the value of is variably set.
  • the corner portion of the gate voltage waveform of the output transistor can be removed.
  • the corner portions of the output signal waveform can also be removed, and radiation noise can be reduced.
  • the charging/discharging circuit changes the value of the charging current to a predetermined charging initial value (A configuration (second configuration) may be adopted in which, after setting VAL C1 ), the charging reference value (VAL C2 ) is increased to a predetermined charging reference value (VAL C2 ).
  • the charging/discharging circuit changes the value of the discharge current to a predetermined discharge level in response to switching of the level of the input signal from a first level to a second level.
  • a configuration (third configuration) may be adopted in which the initial value (VAL D1 ) is set and then increased to a predetermined discharge reference value (VAL D2 ).
  • the signal transmitting device according to any one of the first to third configurations, further comprising a boost circuit (150) connected to the gate of the output transistor, wherein the boost circuit has a level of the input signal at a second level.
  • a configuration (fourth configuration) that increases the rate of increase in the gate voltage of the output transistor by supplying a boost current to the gate of the output transistor separately from the charging current by the charging/discharging circuit when the voltage is switched to the first level. configuration).
  • the boost circuit outputs the output signal until the gate voltage of the output transistor increases to a predetermined voltage after the level of the input signal switches from the second level to the first level.
  • a configuration may be used in which the boost current is supplied to the gate of the transistor.
  • a rise suppressing diode (114) having a forward direction from the gate of the output transistor to the drain of the output transistor is connected to the gate and drain of the output transistor.
  • a configuration (sixth configuration) provided in between may also be used.
  • the charging/discharging circuit may be configured to reduce the value of the charging current (seventh configuration).
  • the corresponding angle portion (E2) that may be included in the output signal waveform can be removed, thereby reducing radiation noise.
  • the charging/discharging circuit may be configured to reduce the value of the discharge current (eighth configuration).
  • the corresponding angle portion (E4) that may be included in the output signal waveform can be removed, thereby reducing radiation noise.
  • the charging/discharging circuit is configured to supply the charging current to the gate of the output transistor during a period in which the input signal has a first level.
  • a charging circuit (121), and a discharging circuit (122) configured to draw the discharge current from the gate of the output transistor during a period in which the input signal has a second level (a ninth embodiment) configuration).
  • the drain of the output transistor is connected to the output terminal via a backflow prevention diode (113) having a forward direction from the output terminal to the ground.
  • the drain of the output transistor may be directly connected to the output terminal (a tenth structure).
  • the output terminal includes the pull-up resistor and a backflow prevention diode (53) having a forward direction from the power supply voltage application end to the output terminal. ), and may be connected to the application end of the power supply voltage (an eleventh configuration).

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
PCT/JP2023/023587 2022-09-08 2023-06-26 信号送信装置 Ceased WO2024053215A1 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007288774A (ja) * 2006-03-22 2007-11-01 Toyota Central Res & Dev Lab Inc 低スイッチング損失、低ノイズを両立するパワーｍｏｓ回路
JP2010512081A (ja) * 2006-12-04 2010-04-15 アトメル オートモーティヴ ゲゼルシャフト ミット ベシュレンクテル ハフツング 信号のエッジ形成の方法、及びバスシステムの送信機／受信機構成部品
US20100259300A1 (en) * 2009-04-08 2010-10-14 Broadcom Corporation Circuit for digitally controlling line driver current
JP2017200103A (ja) * 2016-04-28 2017-11-02 ローム株式会社 信号処理装置及びバス通信システム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007288774A (ja) * 2006-03-22 2007-11-01 Toyota Central Res & Dev Lab Inc 低スイッチング損失、低ノイズを両立するパワーｍｏｓ回路
JP2010512081A (ja) * 2006-12-04 2010-04-15 アトメル オートモーティヴ ゲゼルシャフト ミット ベシュレンクテル ハフツング 信号のエッジ形成の方法、及びバスシステムの送信機／受信機構成部品
US20100259300A1 (en) * 2009-04-08 2010-10-14 Broadcom Corporation Circuit for digitally controlling line driver current
JP2017200103A (ja) * 2016-04-28 2017-11-02 ローム株式会社 信号処理装置及びバス通信システム

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