JPWO2024053215A1 - - Google Patents
Info
- Publication number
- JPWO2024053215A1 JPWO2024053215A1 JP2024545454A JP2024545454A JPWO2024053215A1 JP WO2024053215 A1 JPWO2024053215 A1 JP WO2024053215A1 JP 2024545454 A JP2024545454 A JP 2024545454A JP 2024545454 A JP2024545454 A JP 2024545454A JP WO2024053215 A1 JPWO2024053215 A1 JP WO2024053215A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2022143089 | 2022-09-08 | ||
| PCT/JP2023/023587 WO2024053215A1 (ja) | 2022-09-08 | 2023-06-26 | 信号送信装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2024053215A1 true JPWO2024053215A1 (https=) | 2024-03-14 |
| JPWO2024053215A5 JPWO2024053215A5 (https=) | 2025-05-21 |
Family
ID=90192342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024545454A Pending JPWO2024053215A1 (https=) | 2022-09-08 | 2023-06-26 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPWO2024053215A1 (https=) |
| WO (1) | WO2024053215A1 (https=) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4971848B2 (ja) * | 2006-03-22 | 2012-07-11 | 株式会社豊田中央研究所 | 低スイッチング損失、低ノイズを両立するパワーｍｏｓ回路 |
| DE102006058889B3 (de) * | 2006-12-04 | 2008-05-21 | Atmel Germany Gmbh | Verfahren zur Flankenformung von Signalen und Sender-/Empfänger-Baustein für ein Bussystem |
| US8183885B2 (en) * | 2009-04-08 | 2012-05-22 | Broadcom Corporation | Circuit for digitally controlling line driver current |
| JP2017200103A (ja) * | 2016-04-28 | 2017-11-02 | ローム株式会社 | 信号処理装置及びバス通信システム |
-
2023
- 2023-06-26 JP JP2024545454A patent/JPWO2024053215A1/ja active Pending
- 2023-06-26 WO PCT/JP2023/023587 patent/WO2024053215A1/ja not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024053215A1 (ja) | 2024-03-14 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20250131 |