JPWO2023166657A1 - - Google Patents

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Publication number
JPWO2023166657A1
JPWO2023166657A1 JP2022561541A JP2022561541A JPWO2023166657A1 JP WO2023166657 A1 JPWO2023166657 A1 JP WO2023166657A1 JP 2022561541 A JP2022561541 A JP 2022561541A JP 2022561541 A JP2022561541 A JP 2022561541A JP WO2023166657 A1 JPWO2023166657 A1 JP WO2023166657A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2022561541A
Other languages
Japanese (ja)
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JP7337469B1 (ja
JPWO2023166657A5 (https=
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Publication of JP7337469B1 publication Critical patent/JP7337469B1/ja
Publication of JPWO2023166657A1 publication Critical patent/JPWO2023166657A1/ja
Publication of JPWO2023166657A5 publication Critical patent/JPWO2023166657A5/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/668Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107Buried supplementary regions, e.g. buried guard rings 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126Top-view geometrical layouts of the regions or the junctions
    • H10D62/127Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393Body regions of DMOS transistors or IGBTs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325Silicon carbide
JP2022561541A 2022-03-03 2022-03-03 半導体装置および電力変換装置 Active JP7337469B1 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/009114 WO2023166657A1 (ja) 2022-03-03 2022-03-03 半導体装置および電力変換装置

Publications (3)

Publication Number Publication Date
JP7337469B1 JP7337469B1 (ja) 2023-09-04
JPWO2023166657A1 true JPWO2023166657A1 (https=) 2023-09-07
JPWO2023166657A5 JPWO2023166657A5 (https=) 2024-02-06

Family

ID=87882047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022561541A Active JP7337469B1 (ja) 2022-03-03 2022-03-03 半導体装置および電力変換装置

Country Status (2)

Country Link
JP (1) JP7337469B1 (https=)
WO (1) WO2023166657A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7783598B2 (ja) * 2022-03-17 2025-12-10 株式会社東芝 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機
US20250241040A1 (en) * 2024-01-19 2025-07-24 Wolfspeed, Inc. Gate trench power semiconductor devices having deep trench shield connection patterns

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4738562B2 (ja) * 2000-03-15 2011-08-03 三菱電機株式会社 半導体装置の製造方法
JP2007134625A (ja) * 2005-11-14 2007-05-31 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2014003191A (ja) * 2012-06-20 2014-01-09 Hitachi Ltd 半導体装置
JP6715567B2 (ja) * 2014-12-16 2020-07-01 富士電機株式会社 半導体装置
DE102014119465B3 (de) * 2014-12-22 2016-05-25 Infineon Technologies Ag Halbleitervorrichtung mit streifenförmigen trenchgatestrukturen, transistormesas und diodenmesas
DE112017001788B4 (de) * 2016-03-30 2024-05-08 Mitsubishi Electric Corporation Halbleitereinheit, Verfahren zur Herstellung derselben und Leistungswandler
JP6848382B2 (ja) * 2016-11-16 2021-03-24 富士電機株式会社 半導体装置および半導体装置の製造方法
DE102017108738B4 (de) * 2017-04-24 2022-01-27 Infineon Technologies Ag SiC-HALBLEITERVORRICHTUNG MIT EINEM VERSATZ IN EINEM GRABENBODEN UND HERSTELLUNGSVERFAHREN HIERFÜR
DE112018002873T5 (de) * 2017-06-06 2020-02-27 Mitsubishi Electric Corporation Halbleitereinheit und leistungswandler
JP7029364B2 (ja) * 2018-08-20 2022-03-03 株式会社東芝 半導体装置
DE112019006587T5 (de) * 2019-01-08 2021-12-23 Mitsubishi Electric Corporation Halbleitereinheit und leistungswandlereinheit

Also Published As

Publication number Publication date
JP7337469B1 (ja) 2023-09-04
WO2023166657A1 (ja) 2023-09-07

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