JPWO2022215157A1 - - Google Patents
Info
- Publication number
- JPWO2022215157A1 JPWO2022215157A1 JP2022556246A JP2022556246A JPWO2022215157A1 JP WO2022215157 A1 JPWO2022215157 A1 JP WO2022215157A1 JP 2022556246 A JP2022556246 A JP 2022556246A JP 2022556246 A JP2022556246 A JP 2022556246A JP WO2022215157 A1 JPWO2022215157 A1 JP WO2022215157A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
- G11C14/0036—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/036—Making the capacitor or connections thereto the capacitor extending under the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Databases & Information Systems (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2021/014601 WO2022215157A1 (ja) | 2021-04-06 | 2021-04-06 | メモリ素子を有する半導体装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JPWO2022215157A1 true JPWO2022215157A1 (ja) | 2022-10-13 |
JPWO2022215157A5 JPWO2022215157A5 (ja) | 2023-03-08 |
JP7381145B2 JP7381145B2 (ja) | 2023-11-15 |
Family
ID=83450170
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2022556246A Active JP7381145B2 (ja) | 2021-04-06 | 2021-04-06 | メモリ素子を有する半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US12016172B2 (ja) |
JP (1) | JP7381145B2 (ja) |
TW (1) | TWI806510B (ja) |
WO (1) | WO2022215157A1 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022219696A1 (ja) * | 2021-04-13 | 2022-10-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003188279A (ja) * | 2001-12-14 | 2003-07-04 | Toshiba Corp | 半導体メモリ装置およびその製造方法 |
JP2008147514A (ja) * | 2006-12-12 | 2008-06-26 | Renesas Technology Corp | 半導体記憶装置 |
JP2010519770A (ja) * | 2007-02-26 | 2010-06-03 | マイクロン テクノロジー, インク. | パストランジスタと、垂直読み出し/書き込み有効化トランジスタを含む、キャパシタレスフローティングボディ揮発性メモリセル、およびその製造法とプログラミング法 |
US20170330623A1 (en) * | 2016-05-12 | 2017-11-16 | Korea University Research And Business Foundation | Dual gate semiconductor memory device with vertical semiconductor column |
US20200135863A1 (en) * | 2015-04-29 | 2020-04-30 | Zeno Semiconductor, Inc. | MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2703970B2 (ja) | 1989-01-17 | 1998-01-26 | 株式会社東芝 | Mos型半導体装置 |
JPH03171768A (ja) | 1989-11-30 | 1991-07-25 | Toshiba Corp | 半導体記憶装置 |
JP3957774B2 (ja) | 1995-06-23 | 2007-08-15 | 株式会社東芝 | 半導体装置 |
US6137128A (en) * | 1998-06-09 | 2000-10-24 | International Business Machines Corporation | Self-isolated and self-aligned 4F-square vertical fet-trench dram cells |
JP4919767B2 (ja) * | 2006-11-10 | 2012-04-18 | 株式会社東芝 | 半導体記憶装置 |
US8576628B2 (en) | 2008-01-18 | 2013-11-05 | Sharp Kabushiki Kaisha | Nonvolatile random access memory |
JP2011165815A (ja) | 2010-02-08 | 2011-08-25 | Toshiba Corp | 不揮発性半導体記憶装置 |
WO2014136728A1 (ja) * | 2013-03-05 | 2014-09-12 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその製造方法 |
WO2014184933A1 (ja) * | 2013-05-16 | 2014-11-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Sgtを有する半導体装置の製造方法 |
JP5938529B1 (ja) * | 2015-01-08 | 2016-06-22 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 柱状半導体装置と、その製造方法 |
JP6104477B2 (ja) * | 2015-04-06 | 2017-03-29 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 柱状半導体メモリ装置と、その製造方法 |
US12048140B2 (en) * | 2020-12-25 | 2024-07-23 | Unisantis Electronics Singapore Pte. Ltd. | Memory device using semiconductor element |
WO2022239099A1 (ja) * | 2021-05-11 | 2022-11-17 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | メモリ素子を有する半導体装置 |
-
2021
- 2021-04-06 JP JP2022556246A patent/JP7381145B2/ja active Active
- 2021-04-06 WO PCT/JP2021/014601 patent/WO2022215157A1/ja active Application Filing
-
2022
- 2022-03-22 TW TW111110594A patent/TWI806510B/zh active
- 2022-04-05 US US17/713,839 patent/US12016172B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003188279A (ja) * | 2001-12-14 | 2003-07-04 | Toshiba Corp | 半導体メモリ装置およびその製造方法 |
JP2008147514A (ja) * | 2006-12-12 | 2008-06-26 | Renesas Technology Corp | 半導体記憶装置 |
JP2010519770A (ja) * | 2007-02-26 | 2010-06-03 | マイクロン テクノロジー, インク. | パストランジスタと、垂直読み出し/書き込み有効化トランジスタを含む、キャパシタレスフローティングボディ揮発性メモリセル、およびその製造法とプログラミング法 |
US20200135863A1 (en) * | 2015-04-29 | 2020-04-30 | Zeno Semiconductor, Inc. | MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application |
US20170330623A1 (en) * | 2016-05-12 | 2017-11-16 | Korea University Research And Business Foundation | Dual gate semiconductor memory device with vertical semiconductor column |
Also Published As
Publication number | Publication date |
---|---|
TWI806510B (zh) | 2023-06-21 |
US12016172B2 (en) | 2024-06-18 |
WO2022215157A1 (ja) | 2022-10-13 |
JP7381145B2 (ja) | 2023-11-15 |
TW202247351A (zh) | 2022-12-01 |
US20220320098A1 (en) | 2022-10-06 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220916 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20220916 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20230926 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20231026 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7381145 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |