JPWO2021038363A1 - - Google Patents
Info
- Publication number
- JPWO2021038363A1 JPWO2021038363A1 JP2021541742A JP2021541742A JPWO2021038363A1 JP WO2021038363 A1 JPWO2021038363 A1 JP WO2021038363A1 JP 2021541742 A JP2021541742 A JP 2021541742A JP 2021541742 A JP2021541742 A JP 2021541742A JP WO2021038363 A1 JPWO2021038363 A1 JP WO2021038363A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
- H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2025016608A JP2025069338A (ja) | 2019-08-29 | 2025-02-04 | 半導体装置 |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019156245 | 2019-08-29 | ||
| JP2019156245 | 2019-08-29 | ||
| JP2019220154 | 2019-12-05 | ||
| JP2019220154 | 2019-12-05 | ||
| PCT/IB2020/057716 WO2021038363A1 (ja) | 2019-08-29 | 2020-08-17 | 半導体装置、電子機器 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2025016608A Division JP2025069338A (ja) | 2019-08-29 | 2025-02-04 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2021038363A1 true JPWO2021038363A1 (https=) | 2021-03-04 |
| JPWO2021038363A5 JPWO2021038363A5 (https=) | 2023-08-07 |
| JP7630430B2 JP7630430B2 (ja) | 2025-02-17 |
Family
ID=74683610
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021541742A Active JP7630430B2 (ja) | 2019-08-29 | 2020-08-17 | 半導体装置、電子機器 |
| JP2025016608A Pending JP2025069338A (ja) | 2019-08-29 | 2025-02-04 | 半導体装置 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2025016608A Pending JP2025069338A (ja) | 2019-08-29 | 2025-02-04 | 半導体装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20220328487A1 (https=) |
| JP (2) | JP7630430B2 (https=) |
| WO (1) | WO2021038363A1 (https=) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20230074757A (ko) | 2020-10-02 | 2023-05-31 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
| KR20230106849A (ko) * | 2022-01-07 | 2023-07-14 | 삼성전자주식회사 | 반도체 장치 |
| CN116206643B (zh) * | 2022-07-25 | 2024-03-15 | 北京超弦存储器研究院 | 动态随机存储单元、存储器、存储装置及读取方法 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63121194A (ja) * | 1986-11-11 | 1988-05-25 | Hitachi Ltd | 半導体記憶装置 |
| JP2017168809A (ja) * | 2015-10-22 | 2017-09-21 | 株式会社半導体エネルギー研究所 | 半導体装置、又は該半導体装置を有する記憶装置 |
| JP2018157208A (ja) * | 2017-03-16 | 2018-10-04 | 東芝メモリ株式会社 | 半導体メモリ |
| JP2018206828A (ja) * | 2017-05-31 | 2018-12-27 | 株式会社半導体エネルギー研究所 | 半導体装置、および半導体装置の作製方法 |
| JP2019008862A (ja) * | 2017-06-26 | 2019-01-17 | 株式会社半導体エネルギー研究所 | 半導体装置、電子機器 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7710765B2 (en) * | 2007-09-27 | 2010-05-04 | Micron Technology, Inc. | Back gated SRAM cell |
| WO2011081000A1 (en) * | 2009-12-28 | 2011-07-07 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and semiconductor device |
| US8588000B2 (en) * | 2010-05-20 | 2013-11-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device having a reading transistor with a back-gate electrode |
| US8902637B2 (en) * | 2010-11-08 | 2014-12-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device comprising inverting amplifier circuit and driving method thereof |
| US9998119B2 (en) * | 2016-05-20 | 2018-06-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, electronic component, and electronic device |
| KR20180055701A (ko) * | 2016-11-17 | 2018-05-25 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 반도체 장치의 제작 방법 |
| US10497712B2 (en) * | 2017-03-16 | 2019-12-03 | Toshiba Memory Corporation | Semiconductor memory |
-
2020
- 2020-08-17 WO PCT/IB2020/057716 patent/WO2021038363A1/ja not_active Ceased
- 2020-08-17 US US17/634,270 patent/US20220328487A1/en active Pending
- 2020-08-17 JP JP2021541742A patent/JP7630430B2/ja active Active
-
2025
- 2025-02-04 JP JP2025016608A patent/JP2025069338A/ja active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63121194A (ja) * | 1986-11-11 | 1988-05-25 | Hitachi Ltd | 半導体記憶装置 |
| JP2017168809A (ja) * | 2015-10-22 | 2017-09-21 | 株式会社半導体エネルギー研究所 | 半導体装置、又は該半導体装置を有する記憶装置 |
| JP2018157208A (ja) * | 2017-03-16 | 2018-10-04 | 東芝メモリ株式会社 | 半導体メモリ |
| JP2018206828A (ja) * | 2017-05-31 | 2018-12-27 | 株式会社半導体エネルギー研究所 | 半導体装置、および半導体装置の作製方法 |
| JP2019008862A (ja) * | 2017-06-26 | 2019-01-17 | 株式会社半導体エネルギー研究所 | 半導体装置、電子機器 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP7630430B2 (ja) | 2025-02-17 |
| US20220328487A1 (en) | 2022-10-13 |
| JP2025069338A (ja) | 2025-04-30 |
| WO2021038363A1 (ja) | 2021-03-04 |
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