JPWO2020255655A1 - - Google Patents
Info
- Publication number
- JPWO2020255655A1 JPWO2020255655A1 JP2021527511A JP2021527511A JPWO2020255655A1 JP WO2020255655 A1 JPWO2020255655 A1 JP WO2020255655A1 JP 2021527511 A JP2021527511 A JP 2021527511A JP 2021527511 A JP2021527511 A JP 2021527511A JP WO2020255655 A1 JPWO2020255655 A1 JP WO2020255655A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019115209 | 2019-06-21 | ||
PCT/JP2020/020976 WO2020255655A1 (ja) | 2019-06-21 | 2020-05-27 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2020255655A1 true JPWO2020255655A1 (ja) | 2020-12-24 |
JPWO2020255655A5 JPWO2020255655A5 (ja) | 2022-03-16 |
Family
ID=74037091
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2021527511A Pending JPWO2020255655A1 (ja) | 2019-06-21 | 2020-05-27 |
Country Status (4)
Country | Link |
---|---|
US (2) | US11915744B2 (ja) |
JP (1) | JPWO2020255655A1 (ja) |
CN (1) | CN114008762A (ja) |
WO (1) | WO2020255655A1 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220231134A1 (en) * | 2021-01-18 | 2022-07-21 | Samsung Electronics Co., Ltd. | Selective single diffusion/electrical barrier |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2665644B2 (ja) * | 1992-08-11 | 1997-10-22 | 三菱電機株式会社 | 半導体記憶装置 |
JP2003218238A (ja) * | 2001-11-14 | 2003-07-31 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP5726770B2 (ja) | 2012-01-12 | 2015-06-03 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2014222740A (ja) * | 2013-05-14 | 2014-11-27 | 株式会社東芝 | 半導体記憶装置 |
JP5612237B1 (ja) | 2013-05-16 | 2014-10-22 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Sgtを有する半導体装置の製造方法 |
US9362292B1 (en) * | 2015-04-17 | 2016-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Two-port SRAM cell structure for vertical devices |
US10707218B2 (en) * | 2018-07-26 | 2020-07-07 | Globalfoundries Inc. | Two port SRAM cell using complementary nano-sheet/wire transistor devices |
WO2020246344A1 (ja) * | 2019-06-03 | 2020-12-10 | 株式会社ソシオネクスト | 半導体記憶装置 |
WO2020255801A1 (ja) * | 2019-06-17 | 2020-12-24 | 株式会社ソシオネクスト | 半導体記憶装置 |
WO2020255656A1 (ja) * | 2019-06-21 | 2020-12-24 | 株式会社ソシオネクスト | 半導体記憶装置 |
-
2020
- 2020-05-27 WO PCT/JP2020/020976 patent/WO2020255655A1/ja active Application Filing
- 2020-05-27 CN CN202080044702.3A patent/CN114008762A/zh active Pending
- 2020-05-27 JP JP2021527511A patent/JPWO2020255655A1/ja active Pending
-
2021
- 2021-12-20 US US17/556,268 patent/US11915744B2/en active Active
-
2024
- 2024-01-16 US US18/413,959 patent/US20240153549A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
WO2020255655A1 (ja) | 2020-12-24 |
US20220115388A1 (en) | 2022-04-14 |
CN114008762A (zh) | 2022-02-01 |
US11915744B2 (en) | 2024-02-27 |
US20240153549A1 (en) | 2024-05-09 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20211209 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20230414 |